Готові списки джерел за темами / Software and hardware security

Добірка наукової літератури з теми "Software and hardware security"

Автор: Grafiati
Опубліковано: 23 вересня 2022
Оновлено: 28 січня 2023

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Статті в журналах з теми "Software and hardware security"

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Gilmont, T., J. D. Legat, and J. J. Quisquater. "Hardware security for software privacy support." Electronics Letters 35, no. 24 (1999): 2096. http://dx.doi.org/10.1049/el:19991424.

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2

Lamparth, Oliver, and Frank Bähren. "Hardware and Software Security in Infotainment Systems." Auto Tech Review 4, no. 12 (December 2015): 24–27. http://dx.doi.org/10.1365/s40112-015-1050-2.

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Lamparth, Oliver, and Frank Bähren. "Hardware and Software Security in Infotainment Systems." ATZelektronik worldwide 10, no. 3 (May 30, 2015): 34–37. http://dx.doi.org/10.1007/s38314-015-0522-0.

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4

Sidhu, Simranjeet, Bassam J. Mohd, and Thaier Hayajneh. "Hardware Security in IoT Devices with Emphasis on Hardware Trojans." Journal of Sensor and Actuator Networks 8, no. 3 (August 10, 2019): 42. http://dx.doi.org/10.3390/jsan8030042.

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Анотація:
Security of IoT devices is getting a lot of attention from researchers as they are becoming prevalent everywhere. However, implementation of hardware security in these devices has been overlooked, and many researches have mainly focused on software, network, and cloud security. A deeper understanding of hardware Trojans (HTs) and protection against them is of utmost importance right now as they are the prime threat to the hardware. This paper emphasizes the need for a secure hardware-level foundation for security of these devices, as depending on software security alone is not adequate enough. These devices must be protected against sophisticated attacks, especially if the groundwork for the attacks is already laid in devices during design or manufacturing process, such as with HTs. This paper will discuss the stealthy nature of these HT, highlight HT taxonomy and insertion methods, and provide countermeasures.
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5

MACHER*, Georg, Harald SPORER, Eugen BRENNER, and Christian KREINER. "Signal-Layer Security and Trust-Boundary Identification based on Hardware-Software Interface Definition." Journal of Ubiquitous Systems and Pervasive Networks 10, no. 1 (March 7, 2018): 1–9. http://dx.doi.org/10.5383/juspn.10.01.001.

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6

Granado-Criado, José M., Miguel A. Vega-Rodríguez, Juan M. Sánchez-Pérez, and Juan A. Gómez-Pulido. "Hardware security platform for multicast communications." Journal of Systems Architecture 60, no. 1 (January 2014): 11–21. http://dx.doi.org/10.1016/j.sysarc.2013.11.007.

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7

Konikiewicz, Wojciech, and Marcin Markowski. "Analysis of Performance and Efficiency of Hardware and Software Firewalls." Journal of Applied Computer Science Methods 9, no. 1 (June 1, 2017): 49–63. http://dx.doi.org/10.1515/jacsm-2017-0003.

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Abstract Firewalls are key elements of network security infrastructure. They should guarantee the proper level of security and, at the same time, the satisfying performance in order to not increase the packet delay in the network. In the paper, we present the comparative study on performance and security of a few firewall technologies including hardware, software and virtual solutions. Three important criteria are considered: the maximal throughput of firewall, the introduced delay and the ability to resist Denial of Service attacks. We report results of experiments, present analysis and formulate a few practical conclusions.
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8

Kitsos, P., N. Sklavos, K. Papadomanolakis, and O. Koufopavlou. "Hardware implementation of bluetooth security." IEEE Pervasive Computing 2, no. 1 (January 2003): 21–29. http://dx.doi.org/10.1109/mprv.2003.1186722.

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9

Dadashzadeh, Mohammad. "Choosing IT Platforms In The Age Of Stuxnet." Journal of Cybersecurity Research (JCR) 2, no. 1 (December 1, 2017): 17–26. http://dx.doi.org/10.19030/jcr.v2i1.10076.

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Анотація:
This paper addresses the question of choosing/investing in IT (hardware/software) platforms that avoid quick obsolescence and the underlying dilemmas of choosing proprietary software versus open source software, and opting for managed services such as public cloud computing versus in-house hardware/communication infrastructures. These dilemmas in strategic information systems planning have become more significant in light of the recent revelations of security backdoors in commercial software, encryption backdoors in communication software, and governmental access to private data on managed services for national security reasons. This paper considers enterprise-wide challenges and strategies for adopting open source software/hardware in response to these security concerns.
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Zhang, Yan Kun. "Computer Network Security Threats and Security Technology Research." Advanced Materials Research 971-973 (June 2014): 1440–43. http://dx.doi.org/10.4028/www.scientific.net/amr.971-973.1440.

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Анотація:
Networksecurity network system is presented, including hardware, software, and itstransmission in the network information security, network security threatsmainly include: software vulnerabilities, improper configuration, safetyconsciousness is not strong, virus, hacker attacks, etc. Is not only afirewall, network security is not anti-virus, intrusion monitoring, firewall,identity authentication, encryption, and other products of simple stack, butfrom the system to the application, from the device to the service ofrelatively complete, the system of the combination of security products.
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Дисертації з теми "Software and hardware security"

1

Edmison, Joshua Nathaniel. "Hardware Architectures for Software Security." Diss., Virginia Tech, 2006. http://hdl.handle.net/10919/29244.

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The need for hardware-based software protection stems primarily from the increasing value of software coupled with the inability to trust software that utilizes or manages shared resources. By correctly utilizing security functions in hardware, trust can be removed from software. Existing hardware-based software protection solutions generally suffer from utilization of trusted software, lack of implementation, and/or extreme measures such as processor redesign. In contrast, the research outlined in this document proposes that substantial, hardware-based software protection can be achieved, without trusting software or redesigning the processor, by augmenting existing processors with security management hardware placed outside of the processor boundary. Benefits of this approach include the ability to add security features to nearly any processor, update security features without redesigning the processor, and provide maximum transparency to the software development and distribution processes. The major contributions of this research include the the augmentation methodology, design principles, and a graph-based method for analyzing hardware-based security systems.
Ph. D.
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2

Patel, Krutartha Computer Science &amp Engineering Faculty of Engineering UNSW. "Hardware-software design methods for security and reliability of MPSoCs." Awarded by:University of New South Wales. Computer Science & Engineering, 2009. http://handle.unsw.edu.au/1959.4/44854.

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Security of a Multi-Processor System on Chip (MPSoC) is an emerging area of concern in embedded systems. MPSoC security is jeopardized by Code Injection attacks. Code Injection attacks, which are the most common types of software attacks, have plagued single processor systems. Design of MPSoCs must therefore incorporate security as one of the primary objectives. Code Injection attacks exploit vulnerabilities in \trusted" and legacy code. An architecture with a dedicated monitoring processor (MONITOR) is employed to simultaneously supervise the application processors on an MPSoC. The program code in the application processors is divided into basic blocks. The basic blocks in the application processors are statically instrumented with special instructions that allow communication with the MONITOR at runtime. The MONITOR verifies the execution of all the processors at runtime using control flow checks and either a timing or instruction count check. This thesis proposes a monitoring system called SOFTMON, a design methodology called SHIELD, a design flow called LOCS and an architectural framework called CUFFS for detecting Code Injection attacks. SOFTMON, a software monitoring system, uses a software algorithm in the MONITOR. SOFTMON incurs limited area overheads. However, the runtime performance overhead is quite high. SHIELD, an extension to the work in SOFTMON overcomes the limitation of high runtime overhead using a MONITOR that is predominantly hardware based. LOCS uses only one special instruction per basic block compared to two, as was the case in SOFTMON and SHIELD. Additionally, profile information is generated for all the basic blocks in all the application processors for the MPSoC designer to tune the design by increasing or decreasing the frequency of loop basic blocks. CUFFS detects attacks even without application processors communicating to the MONITOR. The SOFTMON, SHIELD and LOCS approaches can only detect attacks if the application processors communicate to the MONITOR. CUFFS relies on the exact number of instructions in basic blocks to determine an attack, rather than time-frame based measures used in SOFTMON, SHIELD and LOCS. The lowest runtime performance overhead was achieved by LOCS (worst case of 37.5%), while the SOFTMON monitoring system had the least amount of area overheads of about 25%. The CUFFS approach employed an active MONITOR and hence detected a greater range of attacks. The CUFFS framework also detects bit flip errors (reliability errors) in the control flow instructions of the application processors on an MPSoC. CUFFS can detect nearly 70% of all bit flip errors in the control flow instructions. Additionally, a modified CUFFS approach is proposed to ensure reliable inter-processor communication on an MPSoC. The modified CUFFS approach uses a hardware based checksum approach for reliable inter-processor communication and incurred a runtime performance overhead of up to 25% and negligible area overheads compared to CUFFS. Thus, the approaches proposed in this thesis equip an MPSoC designer with tools to embed security features during an MPSoC's design phase. Incorporating security measures at the processor design level provides security against software attacks in MPSoCs and incurs manageable runtime, area and code-size overheads.
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Chakraborty, Rajat Subhra. "Hardware Security through Design Obfuscation." Cleveland, Ohio : Case Western Reserve University, 2010. http://rave.ohiolink.edu/etdc/view?acc_num=case1270133481.

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Анотація:
Thesis (Doctor of Philosophy)--Case Western Reserve University, 2010
Department of EECS - Computer Engineering Title from PDF (viewed on 2010-05-25) Includes abstract Includes bibliographical references and appendices Available online via the OhioLINK ETD Center
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4

Fießler, Andreas Christoph Kurt. "Hybrid Hardware/Software Architectures for Network Packet Processing in Security Applications." Doctoral thesis, Humboldt-Universität zu Berlin, 2019. http://dx.doi.org/10.18452/20023.

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Die Menge an in Computernetzwerken verarbeiteten Daten steigt stetig, was Netzwerkgeräte wie Switches, Bridges, Router und Firewalls vor Herausfordungen stellt. Die Performance der verbreiteten, CPU/softwarebasierten Ansätze für die Implementierung dieser Aufgaben ist durch den inhärenten Overhead in der sequentiellen Datenverarbeitung limitiert, weshalb solche Funktionalitäten vermehrt auf dedizierten Hardwarebausteinen realisiert werden. Diese bieten eine schnelle, parallele Verarbeitung mit niedriger Latenz, sind allerdings aufwendiger in der Entwicklung und weniger flexibel. Nicht jede Anwendung kann zudem für parallele Verarbeitung optimiert werden. Diese Arbeit befasst sich mit hybriden Ansätzen, um eine bessere Ausnutzung der jeweiligen Stärken von Soft- und Hardwaresystemen zu ermöglichen, mit Schwerpunkt auf der Paketklassifikation. Es wird eine Firewall realisiert, die sowohl Flexibilität und Analysetiefe einer Software-Firewall als auch Durchsatz und Latenz einer Hardware-Firewall erreicht. Der Ansatz wird auf einem Standard-Rechnersystem, welches für die Hardware-Klassifikation mit einem rekonfigurierbaren Logikbaustein (FPGA) ergänzt wird, evaluiert. Eine wesentliche Herausforderung einer hybriden Firewall ist die Identifikation von Abhängigkeiten im Regelsatz. Es werden Ansätze vorgestellt, welche den redundanten Klassifikationsaufwand auf ein Minimum reduzieren, wie etwa die Wiederverwendung von Teilergebnissen der hybriden Klassifikatoren oder eine exakte Abhängigkeitsanalyse mittels Header Space Analysis. Für weitere Problemstellungen im Bereich der hardwarebasierten Paketklassifikation, wie dynamisch konfigurierbare Filterungsschaltkreise und schnelle, sichere Hashfunktionen für Lookups, werden Machbarkeit und Optimierungen evaluiert. Der hybride Ansatz wird im Weiteren auf ein System mit einer SDN-Komponente statt einer FPGA-Erweiterung übertragen. Auch hiermit können signifikante Performancegewinne erreicht werden.
Network devices like switches, bridges, routers, and firewalls are subject to a continuous development to keep up with ever-rising requirements. As the overhead of software network processing already became the performance-limiting factor for a variety of applications, also former software functions are shifted towards dedicated network processing hardware. Although such application-specific circuits allow fast, parallel, and low latency processing, they require expensive and time-consuming development with minimal possibilities for adaptions. Security can also be a major concern, as these circuits are virtually a black box for the user. Moreover, the highly parallel processing capabilities of specialized hardware are not necessarily an advantage for all kinds of tasks in network processing, where sometimes a classical CPU is better suited. This work introduces and evaluates concepts for building hybrid hardware-software-systems that exploit the advantages of both hardware and software approaches in order to achieve performant, flexible, and versatile network processing and packet classification systems. The approaches are evaluated on standard software systems, extended by a programmable hardware circuit (FPGA) to provide full control and flexibility. One key achievement of this work is the identification and mitigation of challenges inherent when a hybrid combination of multiple packet classification circuits with different characteristics is used. We introduce approaches to reduce redundant classification effort to a minimum, like re-usage of intermediate classification results and determination of dependencies by header space analysis. In addition, for some further challenges in hardware based packet classification like filtering circuits with dynamic updates and fast hash functions for lookups, we describe feasibility and optimizations. At last, the hybrid approach is evaluated using a standard SDN switch instead of the FPGA accelerator to prove portability.
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5

Mendoza, Jose Antonio. "Hardware and Software Codesign of a JPEG2000 Watermarking Encoder." Thesis, University of North Texas, 2008. https://digital.library.unt.edu/ark:/67531/metadc9752/.

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Analog technology has been around for a long time. The use of analog technology is necessary since we live in an analog world. However, the transmission and storage of analog technology is more complicated and in many cases less efficient than digital technology. Digital technology, on the other hand, provides fast means to be transmitted and stored. Digital technology continues to grow and it is more widely used than ever before. However, with the advent of new technology that can reproduce digital documents or images with unprecedented accuracy, it poses a risk to the intellectual rights of many artists and also on personal security. One way to protect intellectual rights of digital works is by embedding watermarks in them. The watermarks can be visible or invisible depending on the application and the final objective of the intellectual work. This thesis deals with watermarking images in the discrete wavelet transform domain. The watermarking process was done using the JPEG2000 compression standard as a platform. The hardware implementation was achieved using the ALTERA DSP Builder and SIMULINK software to program the DE2 ALTERA FPGA board. The JPEG2000 color transform and the wavelet transformation blocks were implemented using the hardware-in-the-loop (HIL) configuration.
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6

Ramsey, Glenn. "Hardware/software optimizations for elliptic curve scalar multiplication on hybrid FPGAs /." Online version of thesis, 2008. http://hdl.handle.net/1850/7765.

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Zarate, Orozco Ismael. "Software and Hardware-In-The-Loop Modeling of an Audio Watermarking Algorithm." Thesis, University of North Texas, 2010. https://digital.library.unt.edu/ark:/67531/metadc33221/.

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Due to the accelerated growth in digital music distribution, it becomes easy to modify, intercept, and distribute material illegally. To overcome the urgent need for copyright protection against piracy, several audio watermarking schemes have been proposed and implemented. These digital audio watermarking schemes have the purpose of embedding inaudible information within the host file to cover copyright and authentication issues. This thesis proposes an audio watermarking model using MATLAB® and Simulink® software for 1K and 2K fast Fourier transform (FFT) lengths. The watermark insertion process is performed in the frequency domain to guarantee the imperceptibility of the watermark to the human auditory system. Additionally, the proposed audio watermarking model was implemented in a Cyclone® II FPGA device from Altera® using the Altera® DSP Builder tool and MATLAB/Simulink® software. To evaluate the performance of the proposed audio watermarking scheme, effectiveness and fidelity performance tests were conducted for the proposed software and hardware-in-the-loop based audio watermarking model.
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8

Zaiets, Tetiana. "Diebold Nixdorf - global leader in providing innovative self-service technology, security systems and related services." Thesis, Київський національний університет технологій та дизайну, 2017. https://er.knutd.edu.ua/handle/123456789/6690.

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Farag, Mohammed Morsy Naeem. "Architectural Enhancements to Increase Trust in Cyber-Physical Systems Containing Untrusted Software and Hardware." Diss., Virginia Tech, 2012. http://hdl.handle.net/10919/29084.

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Embedded electronics are widely employed in cyber-physical systems (CPSes), which tightly integrate and coordinate computational and physical elements. CPSes are extensively deployed in security-critical applications and nationwide infrastructure. Perimeter security approaches to preventing malware infiltration of CPSes are challenged by the complexity of modern embedded systems incorporating numerous heterogeneous and updatable components. Global supply chains and third-party hardware components, tools, and software limit the reach of design verification techniques and introduce security concerns about deliberate Trojan inclusions. As a consequence, skilled attacks against CPSes have demonstrated that these systems can be surreptitiously compromised. Existing run-time security approaches are not adequate to counter such threats because of either the impact on performance and cost, lack of scalability and generality, trust needed in global third parties, or significant changes required to the design flow. We present a protection scheme called Run-time Enhancement of Trusted Computing (RETC) to enhance trust in CPSes containing untrusted software and hardware. RETC is complementary to design-time verification approaches and serves as a last line of defense against the rising number of inexorable threats against CPSes. We target systems built using reconfigurable hardware to meet the flexibility and high-performance requirements of modern security protections. Security policies are derived from the system physical characteristics and component operational specifications and translated into synthesizable hardware integrated into specific interfaces on a per-module or per-function basis. The policy-based approach addresses many security challenges by decoupling policies from system-specific implementations and optimizations, and minimizes changes required to the design flow. Interface guards enable in-line monitoring and enforcement of critical system computations at run-time. Trust is only required in a small set of simple, self-contained, and verifiable guard components. Hardware trust anchors simultaneously addresses the performance, flexibility, developer productivity, and security requirements of contemporary CPSes. We apply RETC to several CPSes having common security challenges including: secure reconfiguration control in reconfigurable cognitive radio platforms, tolerating hardware Trojan threats in third-party IP cores, and preserving stability in process control systems. High-level architectures demonstrated with prototypes are presented for the selected applications. Implementation results illustrate the RETC efficiency in terms of the performance and overheads of the hardware trust anchors. Testbenches associated with the addressed threat models are generated and experimentally validated on reconfigurable platform to establish the protection scheme efficacy in thwarting the selected threats. This new approach significantly enhances trust in CPSes containing untrusted components without sacrificing cost and performance.
Ph. D.
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10

Kalibjian, Jeff. "Virtualization Security Issues in Telemetry Post-Processing Environments." International Foundation for Telemetering, 2009. http://hdl.handle.net/10150/606000.

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ITC/USA 2009 Conference Proceedings / The Forty-Fifth Annual International Telemetering Conference and Technical Exhibition / October 26-29, 2009 / Riviera Hotel & Convention Center, Las Vegas, Nevada
Virtualization technologies have the potential to transform the telemetry post-processing environment. Significant efficiencies can be gained by migrating telemetry post processing activities to virtual computing platforms. However, while facilitating better server utilization, virtualization also presents several challenges; one of the most difficult of those challenges being security. In virtualization, server environments are replicated in software; unfortunately, the security individual servers provide is not replicated in a software stack implementation of a server environment. After reviewing virtualization fundamentals, security issues and their impact on telemetry post processing will be discussed.
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Книги з теми "Software and hardware security"

1

Raj, Balwinder, and Arun Kumar Singh. Nanoelectronic Devices for Hardware and Software Security. Boca Raton: CRC Press, 2021. http://dx.doi.org/10.1201/9781003126645.

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2

L, Antonakos James, ed. Computer networking from LANs to WANs: Hardware, software and security. Boston, MA: Course Technology, Cengage Learning, 2010.

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3

Inc, ebrary, ed. Zabbix 1.8 network monitoring: Monitor your network's hardware, servers, and Web performance effectively and efficiently. Birmingham, U.K: Packt Pub., 2010.

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4

Madden, Wayne. Implementing AS/400 security. Loveland, Colo: Duke Press, 1992.

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5

Madden, Wayne. Implementing AS/400 security. 2nd ed. Loveland, Colo: Duke Press, 1995.

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6

Carol, Woodbury, ed. Implementing AS/400 security. 3rd ed. Loveland Colo: Duke Press, 1998.

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7

Pascal, Paillier, and Verbauwhede Ingrid, eds. Cryptographic hardware and embedded systems - CHES 2007: 9th international workshop, Vienna, Austria, September 10-13, 2007 ; proceedings. Berlin: Springer, 2007.

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8

Danseglio, Mike. Microsoft Windows server 2003 security administrator's companion. Redmond, Wash: Microsoft Press, 2003.

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9

Patrick, Schaumont, and SpringerLink (Online service), eds. Cryptographic Hardware and Embedded Systems – CHES 2012: 14th International Workshop, Leuven, Belgium, September 9-12, 2012. Proceedings. Berlin, Heidelberg: Springer Berlin Heidelberg, 2012.

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10

Christophe, Clavier, and Gaj Kris, eds. Cryptographic hardware and embedded systems - CHES 2009: 11th international workshop, Lausanne, Switzerland, September 6-9, 2009 ; proceedings. Berlin: Springer, 2009.

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Частини книг з теми "Software and hardware security"

1

Liu, Leibo, Shaojun Wei, Jianfeng Zhu, and Chenchen Deng. "Hardware Security and Reliability." In Software Defined Chips, 73–134. Singapore: Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-19-7636-0_2.

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2

Hossain, Muhammad Monir, Fahim Rahman, Farimah Farahmandi, and Mark Tehranipoor. "Software Security with Hardware in Mind." In Emerging Topics in Hardware Security, 309–33. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-64448-2_12.

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Androulidakis, Iosif I. "Software and Hardware Mobile Phone Tricks." In Mobile Phone Security and Forensics, 47–69. Cham: Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-29742-2_4.

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4

Goryachev, Alex. "Special Session on Security Verification." In Hardware and Software: Verification and Testing, 5. Berlin, Heidelberg: Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-39611-3_5.

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5

Bansal, Shonak, Krishna Parkash, Prince Jain, Sanjeev Kumar, Neena Gupta, and Arun K. Singh. "Photodetectors for Security Application." In Nanoelectronic Devices for Hardware and Software Security, 279–300. Boca Raton: CRC Press, 2021. http://dx.doi.org/10.1201/9781003126645-14.

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6

Mazzawi, Jamil, and Ziyad Hanna. "Formal Analysis of Security Data Paths in RTL Design." In Hardware and Software: Verification and Testing, 7. Berlin, Heidelberg: Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-39611-3_7.

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Ye, Mengmei, Myra B. Cohen, Witawas Srisa-an, and Sheng Wei. "EvoIsolator: Evolving Program Slices for Hardware Isolation Based Security." In Search-Based Software Engineering, 377–82. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-99241-9_24.

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Mao, Wenbo, Fei Yan, Chuanjiang Yi, and Haibo Chen. "Daonity: Protocol Solutions to Grid Security Using Hardware Strengthened Software Environment." In Security Protocols, 204–21. Berlin, Heidelberg: Springer Berlin Heidelberg, 2010. http://dx.doi.org/10.1007/978-3-642-17773-6_27.

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Fukase, Masa-aki, Hiroki Takeda, and Tomoaki Sato. "Hardware/Software Co-design of a Secure Ubiquitous System." In Computational Intelligence and Security, 385–95. Berlin, Heidelberg: Springer Berlin Heidelberg, 2007. http://dx.doi.org/10.1007/978-3-540-74377-4_41.

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Sachidananda, Saraswathi, Srividya Gopalan, and Sridhar Varadarajan. "Hardware-Software Hybrid Packet Processing for Intrusion Detection Systems." In Computational Intelligence and Security, 236–43. Berlin, Heidelberg: Springer Berlin Heidelberg, 2005. http://dx.doi.org/10.1007/11596981_35.

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Тези доповідей конференцій з теми "Software and hardware security"

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Reina, Alessandro, Aristide Fattori, Fabio Pagani, Lorenzo Cavallaro, and Danilo Bruschi. "When hardware meets software." In the 28th Annual Computer Security Applications Conference. New York, New York, USA: ACM Press, 2012. http://dx.doi.org/10.1145/2420950.2420962.

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Lee, Robert P., Konstantinos Markantonakis, and Raja Naeem Akram. "Provisioning Software with Hardware-Software Binding." In ARES '17: International Conference on Availability, Reliability and Security. New York, NY, USA: ACM, 2017. http://dx.doi.org/10.1145/3098954.3103158.

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Singh, Ashwini Kumar, and Nagendra Kushwaha. "Software and Hardware Security of IoT." In 2021 IEEE International IOT, Electronics and Mechatronics Conference (IEMTRONICS). IEEE, 2021. http://dx.doi.org/10.1109/iemtronics52119.2021.9422651.

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Mosier, Nicholas, Hanna Lachnitt, Hamed Nemati, and Caroline Trippel. "Axiomatic hardware-software contracts for security." In ISCA '22: The 49th Annual International Symposium on Computer Architecture. New York, NY, USA: ACM, 2022. http://dx.doi.org/10.1145/3470496.3527412.

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Ferraz, André, and Carlos Ferraz. "Digital Identity Challenge: The Security and Convenience Dilemma." In Seminário Integrado de Software e Hardware. Sociedade Brasileira de Computação - SBC, 2021. http://dx.doi.org/10.5753/semish.2021.15829.

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Анотація:
This paper argues that the essential pieces of an enduring digital identity should be privacy, security, and convenience. Authentication should be frictionless. In this sense, the core of the digital identity of the future will be created around location sensing techniques. Incognia proposes a solution to secure and frictionless authentication for mobile apps that is composed of five steps. Its proprietary technology called environment fingerprinting can identify location spoofing and precisely determine the devices actual location. Incognia has found that most mobile logins, sensitive transactions, and purchases occur at trusted locations. To date, 90% of mobile logins and 89% of mobile banking sessions happen at a trusted location. Experimental results show false-negative rates below 0.004% and a decrease of over 85% of account takeover attacks.
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Lo, Dan Chia-Tien, Kai Qian, and Wei Chen. "Hardware Attacks and Security Education." In 2016 IEEE 40th Annual Computer Software and Applications Conference (COMPSAC). IEEE, 2016. http://dx.doi.org/10.1109/compsac.2016.128.

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"Computing & Processing (Hardware/Software). Information Security." In 2021 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (ElConRus). IEEE, 2021. http://dx.doi.org/10.1109/elconrus51938.2021.9396290.

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Evans, David, and David Eyers. "Melding security metadata between software and hardware." In the Posters and Demo Track. New York, New York, USA: ACM Press, 2012. http://dx.doi.org/10.1145/2405153.2405166.

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"Special sessions: HSS: Hardware and software security." In 2018 IEEE International Conference on Automation, Quality and Testing, Robotics (AQTR). IEEE, 2018. http://dx.doi.org/10.1109/aqtr.2018.8402791.

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"Computing & Processing(Hardware/Software). Information Security." In 2020 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (EIConRus). IEEE, 2020. http://dx.doi.org/10.1109/eiconrus49466.2020.9039073.

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Звіти організацій з теми "Software and hardware security"

1

Souppaya, Murugiah. Hardware-Enabled Security:. Gaithersburg, MD: National Institute of Standards and Technology, 2022. http://dx.doi.org/10.6028/nist.ir.8320b.

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Souppaya, Murugiah. Hardware-Enabled Security:. Gaithersburg, MD: National Institute of Standards and Technology, 2022. http://dx.doi.org/10.6028/nist.ir.8320.

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Bartock, Michael. Hardware Enabled Security:. Gaithersburg, MD: National Institute of Standards and Technology, 2022. http://dx.doi.org/10.6028/nist.ir.8320c.ipd.

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Bartock, Michael, Murugiah Souppaya, Jerry Wheeler, Tim Knoll, Uttam Shetty, Ryan Savino, Joseprabu Inbaraj, Stefano Righi, and Karen Scarfone. Hardware-Enabled Security: Container Platform Security Prototype. National Institute of Standards and Technology, June 2021. http://dx.doi.org/10.6028/nist.ir.8320a.

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Leson, Joel L. Microcomputer Hardware and Software Management Program. Fort Belvoir, VA: Defense Technical Information Center, February 2001. http://dx.doi.org/10.21236/ada402387.

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Sprinkle, Jonathan, and Brandon Eames. Multicore Hardware Experiments in Software Producibility. Fort Belvoir, VA: Defense Technical Information Center, June 2009. http://dx.doi.org/10.21236/ada502782.

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Aggarwal, Aneesh. Low Overhead Software/Hardware Mechanisms for Software Assurance and Producibility. Fort Belvoir, VA: Defense Technical Information Center, February 2007. http://dx.doi.org/10.21236/ada464355.

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Nguyen, Thuy D., Timothy E. Levin, Cynthia E. Irvin, Terry V. Benzel, and Ganesha Bhaskara. Preliminary Security Requirements for SecureCore Hardware. Fort Belvoir, VA: Defense Technical Information Center, September 2006. http://dx.doi.org/10.21236/ada457517.

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Lei, Li. Hardware/Software Interface Assurance with Conformance Checking. Portland State University Library, January 2000. http://dx.doi.org/10.15760/etd.2320.

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Hopper, G. Future possibilities: Data, hardware, software and people. Office of Scientific and Technical Information (OSTI), January 1985. http://dx.doi.org/10.2172/6566336.

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