Добірка наукової літератури з теми "Power Electronics Reliability"

With the development of China’s electric power, power electronics devices such as insulated-gate bipolar transistors (IGBTs) have been widely used in the field of high voltages and large currents. However, the currents in these power electronic devices are transient. For example, the uneven currents and internal chip currents overshoot, which may occur when turning on and off, and could have a great impact on the device. In order to study the reliability of these power electronics devices, this paper proposes a miniature printed circuit board (PCB) Rogowski coil that measures the current of these power electronics devices without changing their internal structures, which provides a reference for the subsequent reliability of their designs.

With the development of power electronics, DC distribution network has advantages in power supplying for DC loads, saving transmission loss of reactive power and improving power quality, when compared with traditional AC distribution network. Since DC distribution network has several multiple topologies, lots of power electronic components and DGs, the traditional reliability evaluation methods aren’t applicable any more. Hence, the reliability models of power electronics and DGs are built in this paper, and a hybrid method combining minimum-cut with non-sequential Monte Carlo is presented. Moreover, three topologies of mid-voltage DC distribution network are designed based on IEEE RBTS bus6, by which the feasibility of the method is validated. Results show that two-terminal network is more reliable than radial and looped network.

Magnetic components are characterized by high robustness and reliability. Controllable magnetic components, which used to dominate, have been out of fashion for about 50 years. However, they have great advantages in terms of longevity, radiation resistance and overload capacity and become smaller and smaller with increasing operating frequency. This makes them interesting in modern power electronics applications with the increasing use of WGB semiconductors. The article shows how the performance of power electronic converters can be improved with modern power electronics and with field-controlled magnetic components using modern magnetic materials. Keywords: Magnetic components; Passive components; Modelling; Magnetic amplifiers; Controllable filters;

Abstract For applications using Wide Band Gap (WBG) semiconductors, and for electronics for down-hole drilling, oil exploration, geothermal energy generation and power electronics, there is a growing need for capacitors that have robust reliability at temperatures of 125°C, 150°C or above. The development of more energy efficient power converters and inverters based on WBG semiconductors is driving the adoption of higher temperatures in a growing number of power electronics and automotive circuits since these operate at higher junction temperatures than traditional silicon. This has led to a growing need for high temperature capacitors with robust reliability. A Class-I C0G dielectric has been developed using Nickel electrodes for high temperature application up to 200°C and beyond. Since it is a paraelectric linear dielectric, these capacitors exhibit highly stable capacitance as a function of temperature and voltage, possess low loss (DF) and can conduct high RMS currents with a low temperature rise compared to other capacitor solutions. To maximize the capacitance density and achieve a high degree of mechanical robustness, stacks and leaded form factors are commonly needed. Materials for assembly of stacks are of interest due to the challenge of higher cost of attachment materials based on gold-solders or nano-silver pastes, as well as due to the presence of lead (Pb) in common high melting point (HMP) solders. This paper will report electrical properties and reliability test data on these Class-I C0G ceramic capacitors and stacks at high temperatures. It will also review thermal robustness and electrical characteristics of stacks assembled using Pb-free transient liquid phase sintering (TLPS) materials based on Sn-Cu and In-Ag.

Silicon Carbide (SiC) is a wide-bandgap (WBG) semiconductor materialwhich has several advantages such as higher maximum electric field, lowerON-state resistance, higher switching speeds, and higher maximum allowablejunction operation temperature compared to Silicon (Si). In the 1.2 kV - 1.7kV voltage range, power devices in SiC are foreseen to replace Si Insulatedgatebipolar transistors (IGBTs) for applications targeting high efficiency,high operation temperatures and/or volume reductions. In particular, theSiC Metal-oxide semiconductor field-effect transistor (MOSFET) – which isvoltage controlled and normally-OFF – is the device of choice due to the easeof its implementation in designs using Si IGBTs.In this work the reliability of SiC devices, in particular that of the SiCMOSFET, has been investigated. First, the possibility of paralleling two discreteSiC MOSFETs is investigated and validated through static and dynamictests. Parallel-connection was found to be unproblematic. Secondly, drifts ofthe threshold voltage and forward voltage of the body diode of the SiC MOSFETare investigated through long-term tests. Also these reliability aspectswere found to be unproblematic. Thirdly, the impact of the package on thechip reliability is discussed through a modeling of the parasitic inductancesof a standard module and the impact of those inductances on the gate oxide.The model shows imbalances in stray inductances and parasitic elementsthat are problematic for high-speed switching. A long-term test on the impactof humidity on junction terminations of SiC MOSFETs dies and SiCSchottky dies encapsulated in the same standard package reveals early degradationfor some modules situated outdoors. Then, the short-circuit behaviorof three different types (bipolar junction transistor, junction field-effect transistor,and MOSFET) of 1.2 kV SiC switching devices is investigated throughexperiments and simulations. The necessity to turn OFF the device quicklyduring a fault is supported with a detailed electro-thermal analysis for eachdevice. Design guidelines towards a rugged and fast short-circuit protectionare derived. For each device, a short-circuit protection driver was designed,built and validated experimentally. The possibility of designing diode-lessconverters with SiC MOSFETs is investigated with focus on surge currenttests through the body diode. The discovered fault mechanism is the triggeringof the npn parasitic bipolar transistor. Finally, a life-cycle cost analysis(LCCA) has been performed revealing that the introduction of SiC MOSFETsin already existing IGBT designs is economically interesting. In fact,the initial investment is saved later on due to a higher efficiency. Moreover,the reliability is improved, which is beneficial from a risk-management pointof-view. The total investment over 20 years is approximately 30 % lower fora converter with SiC MOSFETs although the initial converter cost is 30 %higher.
Kiselkarbid (SiC) är ett bredbandgapsmaterial (WBG) som har flera fördelar,såsom högre maximal elektrisk fältstyrka, lägre ON-state resitans, högreswitch-hastighet och högre maximalt tillåten arbetstemperatur jämförtmed kisel (Si). I spänningsområdet 1,2-1,7 kV förutses att effekthalvledarkomponenteri SiC kommer att ersätta Si Insulated-gate bipolar transistorer(IGBT:er) i tillämpningar där hög verkningsgrad, hög arbetstemperatur ellervolymreduktioner eftersträvas. Förstahandsvalet är en SiC Metal-oxidesemiconductor field-effect transistor (MOSFET) som är spänningsstyrd ochnormally-OFF, egenskaper som möjliggör enkel implementering i konstruktionersom använder Si IGBTer.I detta arbete undersöks tillförlitligheten av SiC komponenter, specielltSiC MOSFET:en. Först undersöks möjligheten att parallellkoppla tvådiskretaSiC MOSFET:ar genom statiska och dynamiska prov. Parallellkopplingbefanns vara oproblematisk. Sedan undersöks drift av tröskelspänning ochbody-diodens framspänning genom långtidsprov. Ocksådessa tillförlitlighetsaspekterbefanns vara oproblematiska. Därefter undersöks kapslingens inverkanpåchip:et genom modellering av parasitiska induktanser hos en standardmoduloch inverkan av dessa induktanser pågate-oxiden. Modellen påvisaren obalans mellan de parasitiska induktanserna, något som kan varaproblematiskt för snabb switchning. Ett långtidstest av inverkan från fuktpåkant-termineringar för SiC-MOSFET:ar och SiC-Schottky-dioder i sammastandardmodul avslöjar tidiga tecken pådegradering för vissa moduler somvarit utomhus. Därefter undersöks kortslutningsbeteende för tre typer (bipolärtransistor,junction-field-effect transistor och MOSFET) av 1.2 kV effekthalvledarswitchargenom experiment och simuleringar. Behovet att stänga avkomponenten snabbt stöds av detaljerade elektrotermiska simuleringar för allatre komponenter. Konstruktionsriktlinjer för ett robust och snabbt kortslutningsskyddtas fram. För var och en av komponenterna byggs en drivkrets medkortslutningsskydd som valideras experimentellt. Möjligheten att konstrueradiodlösa omvandlare med SiC MOSFET:ar undersöks med fokus påstötströmmargenom body-dioden. Den upptäckta felmekanismen är ett oönskat tillslagav den parasitiska npn-transistorn. Slutligen utförs en livscykelanalys(LCCA) som avslöjar att introduktionen av SiC MOSFET:ar i existerandeIGBT-konstruktioner är ekonomiskt intressant. Den initiala investeringensparas in senare pågrund av en högre verkningsgrad. Dessutom förbättrastillförlitligheten, vilket är fördelaktigt ur ett riskhanteringsperspektiv. Dentotala investeringen över 20 år är ungefär 30 % lägre för en omvandlare medSiC MOSFET:ar även om initialkostnaden är 30 % högre.

QC 20170524

Nowadays, numerous power electronics application requires operation at high temperatures. In order to address increasing change of reliability problems in power die attachments for high temperature and high reliability applications, sintering Ag nanoparticles has been used as bonding material for this work. Firstly, quantitative microstructure characterization of as-sintered Ag joints has been carried out. The resulting normalized thickness, pore size and porosity decreased, and grain size increased with increasing the sintering time. A time dependence of the form t1/n with n close to 2 or 3 can be further derived for the kinetics of the thinning, densification and grain growth within the sintered Ag joints. From the results can be seen, sintering kinetics is still in the intermediate stage, the densification had not been completed, and Ag grain would continue growing afterwards, which could further explain degradation behaviours of sintered joints during isothermal ageing tests and thermal cycling tests. Secondly, sintered Ag joints with four kinds of substrate metallization have been subjected to isothermal ageing tests at temperatures of 150°C, 200°C and 250°C for up to 32 days. The different microstructure patterns of sintered joints with four substrate finishes during isothermal ageing tests have been presented and compared, which could use the results to explain part of the degradation behaviours of the sintered Ag joints during thermal cycling tests and guide selection of suitable substrate finish for the die attachments in high temperature power electronic system. Furthermore, thermal cycling tests have been carried out to investigate the reliability of two sizes of sintered Ag joints and solder joints during temperature cycling between -55°C to 125°C and -55°C to 150°C. Microstructure evolution of sintered Ag joints was investigated by non-destructive and destructive characterization methods, which revealed the factors which could effect on the degradation during thermal cycling tests. With microstructure features of sintered joints observed from X-ray tomography and SAM, because a specific specimen can be evaluated over its lifetime, a true image of microstructure evolution of damage during operation can be obtained, and crack and degradation can be observed three-dimensionally.

Circuit assembly and packaging technologies for power electronics have not kept pace with those for digital electronics. Inside those packaged power devices as well as the state-of-the-art power modules, interconnection of power chips is accomplished with wirebonds. Wirebonds in power devices and modules are prone to resistance, noise, parasitic oscillations, fatigue and eventual failure. Furthermore, there has been an increase demand for higher power density and better efficiency for power converters. Power semiconductor suppliers have been concentrating on improving device structure, density, and process technology to lower the on-resistance of MOSFETs and voltage drop of IGBTs. Recent advances made in power semiconductor technology are pushing packaging technology to the limits for performance of these power systems since the resistance and parasitics contribution by the package and the wirebonds are roughly the same as that on the silicon. In recent years, an integrated systems approach to standardizing power electronics components and packaging techniques in the form of power electronics building blocks has emerged as a new concept in the area of power electronics. As a result, it has been envisioned that the packaging of three-dimensional high-density multichip modules (MCMs) can meet the requirement for future power electronics systems. However, the conventional wirebond interconnected power devices are excluded from three-dimensional MCMs because of their large size, limited thermal management, and incompatible processing techniques. On the other hand, advanced solder joint area-array technologies, such as flip-chip technology, has emerged in microelectronics industry due to increased speed, higher packaging density, and performance, improved reliability and low cost these technologies offer. With all these benefits to offer, solder joint area-array technology has yet to be implemented for power electronics packaging. Therefore, the first objective of this study is to design and develop a solder joint area-array interconnection technique for power chips. Solder joint reliability is a major concern for area array technologies and power chip interconnection, thus the second objective of this study is to evaluate solder joint reliability, investigate the fatigue failure behavior of solder joint and improve solder joint reliability by developing a new solder bumping process for improved solder joint geometry, underfilling solder joint with encapsulant and applying flexible substrate in the assembly. The third objective is the implementation of solder joint interconnection technique in developing chip-scale power packages and a three-dimensional integrated power electronics module structure. Solder joint area array interconnection for power chips has been designed with the considerations of parasitic resistance and inductance reduction, current handling capability, thermal management, reliability improvement and manufacturability. A new solder joint fabrication process, which is able to produce high standoff hourglass-shaped solder joint that consists of an inner cap, middle ball and outer cap, as well as the conventional solder bumping process have been successfully developed for power chips by using stencil printing. This solder bumping technology is compatible with the existing surface-mount assembly operations and potentially low cost. The fabricated solder joints have been characterized for their structure integrity, mechanical strength and electrical performances. Solder joint reliability has been improved by optimizing solder joint geometry, underfilling flipped power chip and utilizing compliant substrate. Solder joint reliability was evaluated using accelerated temperate cycling and adhesion tests. The interfaces of the triple-stacked solder joints were examined using scanning electron microscopy (SEM) and energy dispersive X-ray analysis (EDX) for the integrity of the joint. Acoustic microscopy imaging (nondestructive evaluation) was utilized to examine the quality of the bonded interfaces and to detect cracks and other defects before and during accelerated fatigue tests. Adhesion strength of both single bump barrel-shaped and stacked hourglass-shaped solder joints to bonding pads was characterized and analyzed. It was found that stacked hourglass-shaped solder joint have higher fracture stress than barrel-shaped solder joint. This verifies that hourglass-shaped solder joint has lower stress singularity at the interface between the solder bump and the silicon die as well as at the interface between the solder bump and substrate than barrel-shaped solder joint, especially around the corners of the interfaces. Furthermore, the adhesion strength of barrel-shaped solder joint decreases much faster than that of high standoff hourglass-shaped solder joint under temperature cycling, which indicates that the latter has high reliability than the former. Our accelerated temperature cycling test clearly shows that solder joint fatigue failure process consists of three phases: crack initiation, crack propagation and catastrophic failure. Solder joint geometry, underfilling and substrate flexibility were proved to affect solder joint reliability. The effects of solder joint shape and standoff height on reliability have been systematically studied experimentally for the first time. Our experimental results indicated that both hourglass shape and great standoff height could improve solder joint fatigue lifetime, with standoff height being the more effective factor. The fatigue lifetime of high standoff hourglass-shaped solder joint is improved mainly by prolonged crack propagation time, with slight improvement in crack initiation time. Experimental data suggested that shape is the dominant factor affecting crack initiation time while standoff height is the major factor influencing crack propagation time. Underfilling and flexible substrate improved the lifetime of both barrel and hourglass-shaped solder joints. The effect of underfill on solder joint reliability is well known in microelectronics packaging field. However, for the first time, it is reported in this study that flex substrate could improve solder joint reliability. It has been found that flex substrate bucks during temperature cycling and thus reduces thermal strain in solder joints, which in turn improves solder joint fatigue lifetime. Chip scale packaging can enable a few very important concepts and advantages in power electronics packaging. It offers high silicon to package footprint ratio, provides a known good die solution to power chips, improves electrical as well as thermal performance and creates an opportunity for power component standardization. Two kinds of chip-scale power packages have been developed in this research. One is called cavity down flip chip on flex; the other is termed Die Dimensional Ball Grid Array (D2BGA). Both utilize solder joint as chip-level interconnection. Electrical tests show that the VCE(sat) of the high speed IGBT chip-scale packages is improved by 20% to 30% by eliminating the device¡¯s wirebonds and other external interconnections, such as leadframe. Double-sided cooling is realized in these CSPs. Temperature cycling test shows that the CSPs are reliable. Integrated power electronics modules (IPEMs) are envisioned as integrated power modules consisting of power semiconductor devices, power integrated circuits, sensors, and protection circuits for a wide range of power electronics applications, such as inverters for motor drives and converters for power processing equipment. We have developed a three-dimensional approach, termed flip chip on flex (FCOF), for packaging high-performance IPEMs. The new concept is based on the use of solder joint (D2BGA chip scale package), not bonding wires, to interconnect power devices. This packaging approach has the potential to produce modules having superior electrical and thermal performance and improved reliability. We have demonstrated the feasibility of this approach by constructing half-bridge converters (consisting of two IGBTs, two power diodes, and a simple gate driver circuitry) which have been successfully tested at power levels over 30 kW. Switching tests have shown that parasitic inductance of the FCOF module has been reduced by 40% to 50% over conventional wire bond power modules. Better thermal management can be achieved in this three-dimensional power module structure. Compared with the state-of-the-art half-bridge power modules, the volume of the half-bridge FCOF power module is reduced by at least 65%. Reliability test shows that this flip chip on flex power module structure is potentially more reliable than wire bond power module.
Ph. D.

The emergence of the hybrid electric vehicle and electric vehicles (HEV and EV) requires the reliability assessment of power electronic devices used in the inverters. This includes the electro-thermal reliability of bipolar devices such as IGBTs and PiN diodes and more recently, the SiC MOSFETs since the SiC technology is not as mature as their bipolar counterparts. This research, in its own capacity, through the use of accurate compact models, investigates the switching performance and characteristics of silicon IGBTs, PiN diodes and SiC MOSFETs. The need for higher power densities and fast device switching causes certain concerns in the performance and terminal characteristics of the converter. SiC MOSFET is a potential power device for implementing EV drivetrain inverters. One of the major advantages of SiC MOSFET is the possibility of using their body diodes for reverse current conduction, thereby obviating the need for lossy silicon PiN diodes. The primary goal of using SiC MOSFETs is to enable high frequency switching since the significantly lower switching losses coupled with the high dI/dt and dV/dt can increase the power density. This research has investigated and modelled the use of the SiC body diode for current commutation under high dV/dt conditions. Since the body diode is not designed to operate under such conditions, the electrothermal robustness of SiC body diode is investigated by simulating parasitic BJT latch-up that results from hard current commutation under high dV/dt. In a power MOSFET, high switching rates coupled with the drain-body capacitance brings about a displacement current passing through the resistive path of the P-body in the MOSFET structure which creates a voltage at the base of the parasitic BJT within the device. This BJT latch-up under certain thermal conditions is capable of destruction of the device. Another problem induced by high switching speed is that of the electrical coupling between complementing devices in the same leg of the inverter which is known as cross-talk or parasitic gate turn-on. In this research, the unintentional switching of IGBTs and the resulting short circuit current surge passing through the devices as a consequence of reducing the dead-time as well as increasing the switching rate is investigated and modelled. This is due to the discharge of the Miller capacitance which feeds back a current into the gate of the transistor. The result is that both transistors are switching on in the same phase leg. The other problem which is addressed in this research is modelling the switching transients of parallel connected IGBTs for the purpose of delivering high current conduction capability. The electrothermal energy balancing between the parallel connected IGBTs is important as the electrothermal variation between the parallel connected devices can cause temperature imbalance, thereby, accelerating the degradation of the power module. This research investigates the variations in the electrical time constants and the thermal time constants between the parallel connected devices and models the switching behaviours. Lastly, this research has focused on designing and fabricating power modules suitable for EV application and has tried to address methods to improve the electrothermal performance of the device and has investigated the impact of parasitic inductance of the layout on the electrothermal performance of the power module.

Wide-bandgap (WBG) semiconductor materials such as silicon carbide (SiC) and gallium-nitride (GaN) allow higher voltage ratings, lower on-state voltage drops, higher switching frequencies, and higher maximum temperatures. All these advantages make them an attractive choice when high-power density and high-efficiency converters are targeted. Two different gate-driver designs for SiC power devices are presented. First, a dual-function gate-driver for a power module populated with SiC junction field-effect transistors that finds a trade-off between fast switching speeds and a low oscillative performance has been presented and experimentally verified. Second, a gate-driver for SiC metal-oxide semiconductor field-effect transistors with a short-circuit protection scheme that is able to protect the converter against short-circuit conditions without compromising the switching performance during normal operation is presented and experimentally validated. The benefits and issues of using parallel-connection as the design strategy for high-efficiency and high-power converters have been presented. In order to evaluate parallel connection, a 312 kVA three-phase SiC inverter with an efficiency of 99.3 % has been designed, built, and experimentally verified. If parallel connection is chosen as design direction, an undesired trade-off between reliability and efficiency is introduced. A reliability analysis has been performed, which has shown that the gate-source voltage stress determines the reliability of the entire system. Decreasing the positive gate-source voltage could increase the reliability without significantly affecting the efficiency. If high-temperature applications are considered, relatively little attention has been paid to passive components for harsh environments. This thesis also addresses high-temperature operation. The high-temperature performance of two different designs of inductors have been tested up to 600_C. Finally, a GaN power field-effect transistor was characterized down to cryogenic temperatures. An 85 % reduction of the on-state resistance was measured at −195_C. Finally, an experimental evaluation of a 1 kW singlephase inverter at low temperatures was performed. A 33 % reduction in losses compared to room temperature was achieved at rated power.

QC 20160922

This thesis mainly focuses on improving the conventional DC-DC converter topology by utilizing the redundancy concept (N+1) and fault-tolerant design to maintain an uninterrupted output operation even on primary switch failure. The proposed fault-tolerant converter (FTC) involves merging three configurations namely buck, boost and buck-boost to derive a new converter structure along with bidirectional capabilities. The proposed FTC is equipped with a single redundant switch and shared with one coupled inductor and one capacitor (1L-1C) to be capable of achieving the step-up and step-down operation. The major faults of the converter system are highly related to the power switching devices, which can be categorized as open circuit fault (OCF), and short circuit fault (SCF). The proposed fault diagnosis scheme is able to detect the OCF and SCF in less than half of the switching period by sampling the rising and failing edge of the pulsating signal to identify the switch fault behavior. Therefore, remedial action of the proposed FTC can be associated with the fault detection unit to anticipate the moment when the converter requires the activation of the redundant switches by providing a back-up operation. However, any reconfigurable decision is necessary to electrically isolate the faulty component in order to avoid the subsequent fault current within the circuit loop. The proposed method of isolation design adopts the joule-integral principle for selecting an appropriate rating between fuse and MOSFET pair. It provides the satisfactory result for protecting the proposed FTC. Finally, a converter reliability model is carried out based on Markov chain theory to formulate the mean time to failure (MTTF) profile for the proposed FTC. The reliability analysis shows that the proposed FTC can surpass the reliability performance of the conventional DC-DC converter through optimization of the circuit topology.

As our electric power distribution infrastructure has aged, considerable investment has been applied to modernizing the electrical power grid through weatherization and in deployment of real-time monitoring systems. A key question is whether or not these investments are reducing the number and duration of power outages, leading to improved reliability. Statistical methods are applied to analyze electrical disturbance data (from the Department of Energy, DOE) and reliability index data (from state utility public service commission regulators) to detect signs of improvement. The number of installed smart meters provided by several utilities is used to determine whether the number of smart meters correlate with a reduction in outage frequency. Indication emerged that the number of power outages may be decreasing over time. The magnitude of power loss has decreased from 2003 to 2007, and behaves cyclically from 2008 to 2014, with a few outlier points in both groups. The duration also appears to be decreasing between 2003-2014. Large blackout events exceeding 5 GW continue to be rare, and certain power outage events are seasonally dependent. There was a linear relationship between the number of customers and the magnitude of a power outage event. However, no relationship was found between the magnitude of power outages and time to restore power. The frequency of outages maybe decreasing as the number of installed smart meters has increased. Recommendations for inclusion of additional metrics, changes to formatting and semantics of datasets currently provided by federal and state regulators are made to help aid researchers in performing more effective analysis. Confounding variables and lack of information that has made the analysis diffcult is also discussed.

Battery storage devices have been widely utilized for different applications. However, for high power applications, battery storage systems come with several challenges, such as the thermal issue, low power density, low life span and high cost. Compared with batteries, supercapacitors have a lower energy density but their power density is very high, and they offer higher cyclic life and efficiency even during fast charge and discharge processes. In this dissertation, new techniques for the control and energy management of the hybrid battery-supercapacitor storage system are developed to improve the performance of the system in terms of efficiency, power quality and reliability. To evaluate the findings of this dissertation, a laboratory-scale DC microgrid system is designed and implemented. The developed microgrid utilizes a hybrid lead-acid battery and supercapacitor energy storage system and is loaded under various grid conditions. The developed microgrid has also real-time monitoring, control and energy management capabilities. A new control scheme and real-time energy management algorithm for an actively controlled hybrid DC microgrid is developed to reduce the adverse impacts of pulsed power loads. The developed control scheme is an adaptive current-voltage controller that is based on the moving average measurement technique and an adaptive proportional compensator. Unlike conventional energy control methods, the developed controller has the advantages of controlling both current and voltage of the system. This development is experimentally tested and verified. The results show significant improvements achieved in terms of enhancing the system efficiency, reducing the AC grid voltage drop and mitigating frequency fluctuation. Moreover, a novel event-based protection scheme for a multi-terminal DC power system has been developed and evaluated. In this technique, fault identification and classifications are performed based on the current derivative method and employing an artificial inductive line impedance. The developed scheme does not require high speed communication and synchronization and it transfers much less data when compared with the traditional method such as the differential protection approach. Moreover, this scheme utilizes less measurement equipment since only the DC bus data is required.

Gallium Nitride is rapidly emerging as a promising material for electronic devices in various fields. Since it is a direct bandgap semiconductor it can be used for highly efficient light emitting devices (Light Emitting Diodes and Laser Diodes) and the possibility of growing alloys containing Aluminum and Indium allow for the selection of the peak wavelength along the whole UV-green part of the radiation spectrum. Moreover, the high electron mobility, the ability of withstand high electric fields and the good thermal dissipation make GaN-based diodes and transistors devices with a good potential for high frequency and power applications. Before final products containing Gallium Nitride devices can permeate the international market, it is required to guarantee that they are reliable enough to have long lifetimes to appeal potential customers, and that their performance/cost relationship is superior compared to other competitors, at least in some specific fields of application. Aim of this thesis is to investigate the strong points of Gallium Nitrides by means of characterization and reliability tests on various different structures (LEDs, laser diodes, blocking diodes, HEMTs, GITs, MISs), in order to analyze the behavior of the material from different points of view. Within this work is reported a detailed study of the gradual degradation of InGaN-based laser diodes and Light-Emitting Diodes submitted to electro-thermal stress. The purpose is to compare the behavior of the two devices by means of electro-optical measurements, electroluminescence characterization, near field emission measurements and Deep-Level Transient Spectroscopy (DLTS) investigation in order to give a deeper understanding of the mechanisms involved in LD degradation. Particular attention is given to the role of injection efficiency decrease and non-radiative recombination. The comparison of the degradation kinetics and an analysis of the degradation modes of the two device structures allowed a complete study of the physical mechanisms responsible for the degradation. It was found that the degradation of the devices can be ascribed to an increase of the defect density, which has a strong impact on non radiative recombination kinetics. The activation energy of the detected deep level is 0.35 - 0.45 eV. As an effect of combined electrical and thermal stress tests on commercially-available InGaN-based blue laser diodes, it has been found that sometimes there is an initial decrease of the threshold current, which is ascribed to the increase of the activation of p-type dopant, promoted by the temperature and the flow of minority carriers. In order to investigate the effects of the creation of defects, two different commercial blue InGaN-based LEDs were submitted to 3 MeV proton irradiation at various fluencies (10^11, 10^12 and 10^13 p/cm2). The degradation process was characterized by combined current-voltage (I - V), optical power-current (L - I) and capacitance-voltage (C - V) measurements, in order to investigate the changes induced by the irradiation and the recovery after annealing time at high temperature (150 °C‰). The experimental data suggest the creation of non-radiative recombination centers near or into the active region of the LEDs, due to atomic displacement. This hypothesis is confirmed by the results of the recovery tests: the increase of the optical power and its correlation with the recovery of the forward current is consistent with the annealing of those defects. Part of the activity on high electron mobility transistors was devoted to the realization of measurement setups in order to carry out novel characterization techniques. Were analyzed the advantages and limitations of the current-transient method used for the study of the deep levels in GaN-based high electron mobility transistors (HEMTs), by evaluating how the procedures adopted for measurement and data analysis can influence the results of the investigation. The choice of the measurement parameters (such as the voltage levels used to induce the trapping phenomena and monitor the current transients and the duration of the filling pulses) and of the analysis procedure (the method used for the extrapolation of the time constants of the processes) can influence the results of the drain current transient investigation and can provide information on the location of the trap levels responsible for current collapse. Moreover, was collected a database of defects described in more than 60 papers on GaN and its compounds, which can be used to extract information on the nature and origin of the traps in AlGaN/GaN HEMTs. Using this newly developed technique and other more common tests, several reliability and lifetime test were carried out on various structures, in order to gain a better understanding of their problematic aspects and possible improvements. One potential variation is the composition of the gate stack. Degradation tests were performed at Vgs = -5 V and increasing Vds levels on GaN HEMTs with different gate materials: Ni/Au/Ni, ITO and Ni/ITO. At each step of the stress experiment, the electrical and optical characteristics of the transistors were measured in order to analyze the degradation process. It was found that stress induces a permanent degradation of the gate diode, consisting in an increase in the leakage current. This change is due to the generation of parasitic conductive paths, as suggested by electroluminescence (EL) mapping, and devices based on ITO showed higher reliability. These data strongly support the hypothesis that the robustness is influenced by processing parameters and/or by the gate material, since all analyzed devices come from the same epitaxial wafer. Other than varying the gate material, it is possible to add a p-type layer under the gate in order to achieve normally-off operation. This change produces a benefit in terms of performances, but can give birth to unusual trapping phenomena. It was carried out an extensive analysis of the time and field-dependent trapping processes that occur in GaN-based gate injection transistors exposed to high drain voltage levels. Results indicate that, even if the devices do not suffer from current collapse, continuous exposure to high drain voltages can induce a remarkable increase in the on-resistance (Ron). The increase in Ron can be recovered by leaving the device in rest conditions. Temperature-dependent analysis indicates that the activation energy of the detrapping process is equal to 0.47 eV. By time-resolved electroluminescence characterization, it is shown that this effect is related to the capture of electrons in the gate - drain access region. This is further confirmed by the fact that charge emission can be significantly accelerated through the injection of holes from the gate. A first-order model was developed to explain the time dependence of the trapping process. Using other deep levels characterization techniques, such as drain current transients, gate frequency sweeps and backgating, several other trap states were identified in these devices. Their activation energies are 0.13, 0.14, 0.25, 0.47 and 0.51 eV. During the accelerated lifetime tests of these devices, it was found a variation of the relative amplitude of the transconductance peaks, well correlated with the increase of the electroluminescence. This effect can be explained by the activation of the p-type dopant, a phenomenon which was detected also in laser diodes. It is possible to develop diodes able to withstand very high reverse voltages using a similar structure, deprived of the gate region and with an additional Schottky diode (Natural superjunction). In this case, the activation energies of the detected deep levels were 0.35, 0.36, 0.44 and 0.47 eV. These values are very similar to the ones found in GITs, and this fact, along with the presence of the p-dopant activation in very different devices, confirms that it is useful to study different structures based on the same material in order to gain more knowledge on its performances, possibilities and reliability aspects.
Il Nitruro di Gallio si sta rapidamente proponendo come un materiale promettente per dispositivi elettronici in vari campi applicativi. Dato che si tratta di un semiconduttore a bandgap diretto, può essere utilizzato per realizzare emettitori di radiazione luminosa altamente efficienti (LED e diodi laser), e la possibilità di realizzare leghe contenenti Alluminio e Indio permette di selezionare la lunghezza d’onda di picco all’interno dell’intervallo UV - verde dello spettro elettromagnetico. Prima che i prodotti finali basati su Nitruro di Gallio possano permeare il mercato internazionale, è necessario garantire che siano abbastanza affidabili da possedere lunghi tempi di vita ai fini di essere considerati da potenziali acquirenti, e che il loro rapporto prestazioni/costi sia superiore rispetto a quello dei dispositivi attualmente presenti nel mercato, almeno per alcune specifiche applicazioni. Lo scopo di questa tesi è analizzare i punti di forza dei materiali composti basati su Nitruro di Gallio tramite caratterizzazione e test affidabilistici su varie strutture differenti (LED, diodi laser, diodi bloccanti, HEMT, GIT, MIS), per comprendere il comportamento del materiale da diversi punti di vista. In questo lavoro viene effettuato uno studio dettagliato del degrado graduale di LED e diodi laser in InGaN sottoposti a stress elettrotermici. lo scopo è di paragonare il comportamento delle due tipologie di dispositivi tramite caratterizzazione elettrica e ottica, elettroluminescenza, mappe di emissione in campo vicino e Deep-Level Transient Spectroscopy (DLTS), in modo da ottenere una comprensione profonda dei meccanismi di degrado che causano il calo di performance dei diodi laser. Un’attenzione particolare è rivolta al ruolo del calo dell’efficienza di iniezione e alla ricombinazione non-radiativa. Il confronto delle cinetiche di degrado e l’analisi del tipo di danno nelle due diverse strutture ha permesso uno studio completo dei meccanismi fisici responsabili del calo delle prestazioni. Il degrado dei dispositivi è stato attribuito ad un aumento della concentrazione di difetti, che ha un forte impatto sulle cinetiche di ricombinazione non-radiativa. L’energia di attivazione del livello profondo rilevato è 0.35 - 0.45 eV. Come effetto dei test di vita accelerata elettrici e termici compiuti su diodi laser blu commerciali basati su InGaN, si è notato che a volte si ha un iniziale calo della corrente di soglia, dovuto all’aumento dell’attivazione del drogante di tipo p, promossa dalla temperatura e dal flusso di portatori minoritari. Per comprendere gli effetti della creazione di difetti, due differenti tipologie di LED blu commerciali basati su InGaN sono stati sottoposti a irraggiamento tramite protoni con un’energia di 3 MeV a varie fluenze (10^11, 10^12 and 10^13 p/cm2). Il processo di degrado è stato caratterizzato tramite misure corrente - tensione (I - V), potenza ottica - corrente (L - I) e capacità - tensione (C - V) combinate, per cercare di comprendere le modifiche indotte dall’irraggiamento e il recupero conseguente all’annealing ad alte temperature (150 ‰). I dati sperimentali suggeriscono la creazione di centri di ricombinazione non-radiativa vicino o all’interno della regione attiva dei LED, causati dallo spostamento di atomi. Questa ipotesi viene confermata dai risultati dei test di recupero: l’aumento della potenza ottica e la sua correlazione con il recupero della corrente diretta è consistente con l’annealing dei difetti. Parte dell’attività sui transistor ad elevata mobilità elettronica è stata dedicata alla realizzazione di setup di misura che permettessero di utilizzare tecniche di caratterizzazione avanzata. Si sono analizzati i vantaggi e i limiti della metodologia dei transienti di corrente utilizzata per lo studio dei livelli profondi in HEMT basati su GaN, verificando in che modo diverse procedure adottate per la misurazione e l’analisi dei dati possano influenzare i risultati. La scelta dei parametri di misura (come i livelli di tensione utilizzati per indurre l’intrappolamento di carica e monitorare il transiente di corrente e la durata degli impulsi di filling) e della procedura di analisi (il metodo usato per l’estrapolazione delle costanti di tempo dei processi) può influenzare i risultati e può fornire informazioni sulla posizione degli stati trappola responsabili per il calo della corrente. Inoltre, è stato raccolto un database di difetti descritti in più di 60 articoli scientifici sul Nitruro di Gallio e i suoi composti, che può essere utilizzato per ottenere informazioni sulla natura e sull’origine delle trappole negli HEMT in AlGaN/GaN. Utilizzando questa tecnica innovativa e altri test più comuni, sono stati condotti test affidabilistici e di tempo di vita su varie strutture, per ottenere una miglior comprensione delle loro problematiche e dei possibili miglioramenti. Una possibile variazione riguarda la composizione dello stack di gate. Sono stati condotti test di degrado a Vgs = -5 V e valori di Vds crescenti su HEMT in GaN con differenti materiali di gate: Ni/Au/Ni, ITO e Ni/ITO. Ad ogni passo dello stress sono state misurate le caratteristiche elettriche e ottiche dei transistor, per analizzare il processo di degrado. Si è trovato che lo stress causa un degrado permanente del diodo di gate, che consiste in un aumento della corrente di leakage. Questo cambiamento è dovuto alla generazione di cammini conduttivi parassiti, come suggerito dalle misure di elettroluminescenza (EL), e dispositivi basati su ITO hanno mostrato un’affidabilità maggiore. Questi dati sostengono fortemente l’ipotesi che la robustezza è influenzata dai parametri di processo e/o dal materiale di gate, dato che tutti i dispositivi analizzati provengono dallo stesso wafer epitassiale. Oltre a variare il materiale di gate, è possibile aggiungere uno strato di tipo p sotto il gate per ottenere un funzionamento normally-off. Questo cambiamento fornisce un incremento delle performance, ma può dar nascita a fenomeni di trapping particolari. Si è condotta un’accurata analisi dei processi di trapping dipendenti dal tempo e dal campo elettrico che si verificano nei transistor ad iniezione di corrente di gate (GIT) quando vengono sottoposti ad elevate tensioni di drain. I risultati indicano che, anche se i dispositivi non soffrono di cali di corrente per tempi brevi, l’esposizione continua a tensioni di drain elevate può indurre un aumento significativo della resistività in zona lineare (Ron). Il valore originario di Ron può essere recuperato lasciano il dispositivo a riposo. L’analisi della dipendenza dalla temperatura indica che l’energia di attivazione del processo di detrappolamento è pari a 0.47 eV. Tramite una caratterizzazione dell’elettroluminescenza risolta temporalmente, viene mostrato che questo effetto è correlato alla cattura di elettroni nella regione di accesso gate - drain. Questa interpretazione è inoltre confermata dal fatto che l’emissione della carica può essere significativamente accelerata attraverso l’iniezione di lacune dal gate. Un modello del primo ordine è stato sviluppato per spiegare la dipendenza dal tempo del processo di trapping. Utilizzando altre tecniche di caratterizzazione dei livelli profondi, come i transienti di corrente di drain, gli sweep di frequenza di gate e il backgating, in questi dispositivi si sono identificati vari altri stati trappola. Le loro energie di attivazione sono 0.13, 0.14, 0.25, 0.47 e 0.51 eV. Durante i test di vita accelerata di questi dispositivi, si è trovata una variazione dell’ampiezza relativa dei picchi di transconduttanza ben correlata con l’aumento dell’elettroluminescenza. Questo effetto può essere spiegato tramite l’attivazione del drogante p, un fenomeno che si è osservato anche nei diodi laser. Utilizzando una struttura simile, è possibile realizzare diodi capaci di sopportare tensioni inverse molto elevate, rimuovendo la regione di gate e aggiungendo un diodo Schottky (Natural Superjunction). In questo caso, si sono rilevati livelli profondi di energia di attivazione 0.35, 0.36, 0.44 e 0.47 eV. Questi valori sono molto simili a quelli trovati nei GIT, e questo fatto, insieme alla presenza dell’ativazione del drogante p in dispositivi molto differenti tra loro, conferma l’utilità dello studio di differenti strutture basate sullo stesso materiale per ottenere una maggior conoscenza delle sue performance, possibilità e aspetti affidabilistici.

This study focuses on development a planar power module with low thermal impedance and thermo-mechanical stress for high density integration of power electronics systems. With the development semiconductor technology, the heat flux generated in power device keeps increasing. As a result, more and more stringent requirements were imposed on the thermal and reliability design of power electronics packaging. In this dissertation, a boundary-dependent RC transient thermal model was developed to predict the peak transient temperature of semiconductor device in the power module. Compared to conventional RC thermal models, the RC values in the proposed model are functions of boundary conditions, geometries, and the material properties of the power module. Thus, the proposed model can provide more accurate prediction for the junction temperature of power devices under variable conditions. In addition, the transient thermal model can be extracted based on only steady-state thermal simulation, which significantly reduced the computing time. To detect the peak transient temperature in a fully packaged power module, a method for thermal impedance measurement was proposed. In the proposed method, the gate-emitter voltage of an IGBT which is much more sensitive to the temperature change than the widely used forward voltage drop of a pn junction was monitored and used as temperature sensitive parameter. A completed test circuit was designed to measure the thermal impedance of the power module using the gate-emitter voltage. With the designed test set-up, in spite of the temperature dependency of the IGBT electrical characteristics, the power dissipation in the IGBT can be regulated to be constant by adjusting the gate voltage via feedback control during the heating phase. The developed measurement system was used to evaluate thermal performance and reliability of three different die-attach materials. From the prediction of the proposed thermal model, it was found that the conventional single-sided power module with wirebond connection cannot achieve both good steady-state and transient thermal performance under high heat transfer coefficient conditions. As a result, a plate-bonded planar power module was designed to resolve the issue. The comparison of thermal performance for conventional power module and the plate-bonded power module shows that the plate-bonded power module has both better steady-state and transient thermal performance than the wirebonded power module. However, due to CTE mismatch between the copper plate and the silicon device, large thermo-mechanical stress is induced in the bonding layer of the power module. To reduce the stress in the plate-bonded power module, an improved structure called trenched copper plate structure was proposed. In the proposed structure, the large copper plate on top of the semiconductor can be partitioned into several smaller pieces that are connected together using a thin layer copper foil. The FEM simulation shows that, with the improved structure, the maximum von Mises stress and plastic strain in the solder layer were reduced by 18.7% and 67.8%, respectively. However, the thermal impedance of the power module increases with reduction of the stress. Therefore, the trade-off between these two factors was discussed. To verify better reliability brought by the trenched copper plate structure, twenty-four samples with three different copper plate structures were fabricated and thermally cycled from -40°C to 105°C. To detect the failure at the bonding layer, the curvature of these samples were measured using laser scanning before and after cycling. By monitoring the change of curvature, the degradation of bonding layer can be detected. Experimental results showed that the samples with different copper plate structure had similar curvature before thermal cycle. The curvatures of the samples with single copper plate decreased more than 80% after only 100 cycles. For the samples with 2 × 2 copper plate and the samples with 3 × 3 copper plate, the curvatures became 75.8% and 77.5% of the original values, respectively, indicating better reliability than the samples with single copper plate. The x-ray pictures of cross-sectioned samples confirmed that after 300 cycles, the bonding layer for the sample with single copper plate has many cracks and delaminations starting from the edge.
Ph. D.

Power Electronics uses semiconductor technology to convert and control electrical power. Demands for efficient energy management, conversion and conservation, and the increasing take up of electronics in transport systems (i.e. all electric car) there has been tremendous growth in the use of power electronics semiconductor devices such as Insulated Gate Bipolar Transistors (IGBT’s). The packaging of the power electronics devices involves a number of challenges for design engineers in terms of reliability and thermal management. For example IGBT modules will contain a number of semiconductor dies within a small footprint bonded to substrates with aluminium wires and wide area solder joints. The reliability of the package will depend on thermo-mechanical behavior of these materials. This paper details the results from a major UK project involving academics and industrial partners to investigate the reliability of IGBT modules. The focus of the presentation will be on the modelling tools developed to predict reliability and also the development of prognostics techniques to predict the remaining life of the package.

Power electronics are used in wind turbines to convert variable voltages and frequencies produced by the generator to fixed voltages and frequencies compliant with an electrical grid with minimal losses. The power electronic system is based on a series of three-phase pulse width modulated (PWM) power modules consisting of insulated-gate bipolar transistor (IGBT) power switches and associated diodes that are soldered to a ceramic substrate and interconnected with wirebonds. Power electronics can generate thermal loads in the hundreds of watts/cm2, therefore the design of the packaging and cooling of the electronics is crucial for enhancing their energy efficiency and reliability. Without adequate heat removal, the increase in device temperature will reduce the efficiency of power electronic devices, leading to thermal runaway and eventual failure of the entire power electronic system. Furthermore, the increased temperatures can lead to failure of the packaging elements. Turbines utilizing these power electronics are often placed in harsh and inaccessible offshore environments; power electronic failures causing unscheduled maintenance lead to costly repairs. This paper will provide an overview of the fundamental package level mechanisms that can cause failures in the power electronic system. These include wirebond and lead fatigue, die attach fatigue, substrate cracking, and lead micro-voids. Attention will then be given to the reliability of a plastic-insert liquid cold plate used to manage the thermal loads from the power electronics.

The electric car, the all electric aircraft and requirements for renewable energy are examples of potential technologies needed to address the world problem of global warming/carbon emission etc. Power electronics and packaged modules are fundamental for the underpinning of these technologies and with the diverse requirements for electrical configurations and the range of environmental conditions, time to market is paramount for module manufacturers and systems designers alike. This paper details some of the results from a major UK project into the reliability of power electronic modules using physics of failure techniques. This paper presents a design methodology together with results that demonstrate enhanced product design with improved reliability, performance and value within acceptable time scales.