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Добірка наукової літератури з теми "PCM memory"

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Опубліковано: 7 липня 2024
Оновлено: 7 липня 2024

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Статті в журналах з теми "PCM memory":

1

Arjomand, Mohammad, Amin Jadidi, Mahmut T. Kandemir, Anand Sivasubramaniam, and Chita R. Das. "HL-PCM: MLC PCM Main Memory with Accelerated Read." IEEE Transactions on Parallel and Distributed Systems 28, no. 11 (November 1, 2017): 3188–200. http://dx.doi.org/10.1109/tpds.2017.2705125.

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2

Priya, Bhukya Krishna, and N. Ramasubramanian. "Improving the Lifetime of Phase Change Memory by Shadow Dynamic Random Access Memory." International Journal of Service Science, Management, Engineering, and Technology 12, no. 2 (March 2021): 154–68. http://dx.doi.org/10.4018/ijssmet.2021030109.

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Emerging NVM are replacing the conventional memory technologies due to their huge cell density and low energy consumption. Restricted writes is one of the major drawbacks to adopt PCM memories in real-time environments. The non-uniform writes and process variations can damage the memory cell with intensive writes, as PCM memory cells are having restricted write endurance. To prolong the lifetime of a PCM, an extra DRAM shadow memory has been added to store the writes that comes to the PCM and to level out the wearing that occurs on the PCM. An extra address directory will store the address of data written to the DRAM and a counter is used to count the number of times the blocks are written into. Based upon the counter values, the data will be written from DRAM to the PCM. The data is written to the DRAM from the PCM, based on the data requirement. Experimental results show the reduction in overall writes in a PCM, which in turn improves the lifetime of a PCM by 5% with less hardware and power overhead.
3

Macyna, Wojciech, and Michal Kukowski. "Adaptive Merging on Phase Change Memory." Fundamenta Informaticae 188, no. 2 (March 15, 2023): 103–26. http://dx.doi.org/10.3233/fi-222144.

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Indexing is a well-known database technique used to facilitate data access and speed up query processing. Nevertheless, the construction and modification of indexes are very expensive. In traditional approaches, all records in the database table are equally covered by the index. It is not effective, since some records may be queried very often and some never. To avoid this problem, adaptive merging has been introduced. The key idea is to create an index adaptively and incrementally as a side-product of query processing. As a result, the database table is indexed partially depending on the query workload. This paper faces the problem of adaptive merging for phase change memory (PCM). The most important features of this memory type are limited write endurance and high write latency. As a consequence, adaptive merging should be investigated from the scratch. We solve this problem in two steps. First, we apply several PCM optimization techniques to the traditional adaptive merging approach. We prove that the proposed method (eAM) outperforms a traditional approach by 60%. After that, we invent the framework for adaptive merging (PAM) and propose a new variant of the PCM-optimized index. It further improves the system performance by 20% for databases where search queries interleave with data modifications.
4

Jabarov, Elkhan, Byung-Won On, Gyu Choi, and Myong-Soon Park. "R-Tree for phase change memory." Computer Science and Information Systems 14, no. 2 (2017): 347–67. http://dx.doi.org/10.2298/csis160620008j.

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Nowadays, many applications use spatial data for instance-location information, so storing spatial data is important.We suggest using R -Tree over PCM. Our objective is to design a PCM-sensitive R -Tree that can store spatial data as well as improve the endurance problem. Initially, we examine how R -Tree causes endurance problems in PCM, and we then optimize it for PCM. We propose doubling the leaf node size, writing a split node to a blank node, updating parent nodes only once and not merging the nodes after deletion when the minimum fill factor requirement does not meet. Based on our experimental results while using benchmark dataset, the number of write operations to PCM in average decreased by 56 times by using the proposed R -Tree. Moreover, the proposed R -Tree scheme improves the performance in terms of processing time in average 23% compared to R -Tree.
5

Hong, Jeong Beom, Young Sik Lee, Yong Wook Kim, and Tae Hee Han. "Error-Vulnerable Pattern-Aware Binary-to-Ternary Data Mapping for Improving Storage Density of 3LC Phase Change Memory." Electronics 9, no. 4 (April 9, 2020): 626. http://dx.doi.org/10.3390/electronics9040626.

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Multi-level cell (MLC) phase-change memory (PCM) is an attractive solution for next-generation memory that is composed of resistance-based nonvolatile devices. MLC PCM is superior to dynamic random-access memory (DRAM) with regard to scalability and leakage power. Therefore, various studies have focused on the feasibility of MLC PCM-based main memory. The key challenges in replacing DRAM with MLC PCM are low reliability, limited lifetime, and long write latency, which are predominantly affected by the most error-vulnerable data pattern. Based on the physical characteristics of the PCM, where the reliability depends on the data pattern, a tri-level-cell (3LC) PCM has significantly higher performance and lifetime than a four-level-cell (4LC) PCM. However, a storage density is limited by binary-to-ternary data mapping. This paper introduces error-vulnerable pattern-aware binary-to-ternary data mapping utilizing 3LC PCM without an error-correction code (ECC) to enhance the storage density. To mitigate the storage density loss caused by the 3LC PCM, a two-way encoding is applied. The performance degradation is minimized through parallel encoding. The experimental results demonstrate that the proposed method improves the storage density by 17.9%. Additionally, the lifetime and performance are enhanced by 36.1% and 38.8%, respectively, compared with those of a 4LC PCM with an ECC.
6

Ding, Feilong, Baokang Peng, Xi Li, Lining Zhang, Runsheng Wang, Zhitang Song, and Ru Huang. "A review of compact modeling for phase change memory." Journal of Semiconductors 43, no. 2 (February 1, 2022): 023101. http://dx.doi.org/10.1088/1674-4926/43/2/023101.

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Abstract Phase change memory (PCM) attracts wide attention for the memory-centric computing and neuromorphic computing. For circuit and system designs, PCM compact models are mandatory and their status are reviewed in this work. Macro models and physics-based models have been proposed in different stages of the PCM technology developments. Compact modeling of PCM is indeed more complex than the transistor modeling due to their multi-physics nature including electrical, thermal and phase transition dynamics as well as their interactions. Realizations of the PCM operations including threshold switching, set and reset programming in these models are diverse, which also differs from the perspective of circuit simulations. For the purpose of efficient and reliable designs of the PCM technology, open issues and challenges of the compact modeling are also discussed.
7

Tang, Pu, Jing Xiao, and Ming Tao. "Thermal Crosstalk Analysis of Phase Change Memory Considering Thermoelectric Effect and Thermal Boundary Resistance." Journal of Physics: Conference Series 2624, no. 1 (October 1, 2023): 012020. http://dx.doi.org/10.1088/1742-6596/2624/1/012020.

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Abstract Phase change memory (PCM) has emerged as a promising memory for next-generation applications due to its high-speed read and write capabilities as well as non-volatility. However, as PCM scales down to smaller feature sizes, it faces the challenge of thermal crosstalk. During the reset operation, a large amount of heat is generated and dissipated in the PCM array, potentially affecting adjacent memory cells, compromising device stability, and limiting high-density integration. To accurately investigate the thermal crosstalk in the PCM array, the conventional finite element model of the PCM array is improved by incorporating the thermoelectric effect and thermal boundary resistance. Under the 65, 45, 32, and 22-nm process nodes, the improved model reveals the occurrence of thermal crosstalk within the PCM array, whereas the conventional model is unable to detect this phenomenon at the 65-nm node. The improved model proposed in this paper incorporates more comprehensive considerations, providing a more precise analysis of the thermal crosstalk phenomenon in the PCM array, and thereby offering theoretical reference for high-density integration of the PCM.
8

Stern, Keren, Yair Keller, Christopher M. Neumann, Eric Pop, and Eilam Yalon. "Temperature-dependent thermal resistance of phase change memory." Applied Physics Letters 120, no. 11 (March 14, 2022): 113501. http://dx.doi.org/10.1063/5.0081016.

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One of the key challenges of phase change memory (PCM) is its high power consumption during the reset operation, when the phase change material (typically Ge2Sb2Te5, i.e., GST) heats up to ∼900 K or more in order to melt. Here, we study the temperature-dependent behavior of PCM devices by probing the reset power at ambient temperatures from 80 to 400 K. We find that different device structures exhibit contrasting temperature-dependent behavior. The reset power in our confined-type PCM is nearly unchanged with ambient temperature, corresponding to a temperature-dependent thermal resistance, whereas results for mushroom-type PCM from the literature show a linear relation between power and temperature, suggesting a more constant thermal resistance. This discrepancy is ascribed to different temperature distributions and thermal properties of the dominant components of the PCM cell thermal resistance, as shown by electro-thermal modeling. In the confined cell, the thermal boundary resistance of the GST and the thermal conductivity of the bottom electrode dominate the thermal resistance, while for the mushroom cell, the GST thermal conductivity plays a greater role. These findings can help to design more power- and energy-efficient PCM devices by better focusing thermal management efforts on the key components of the device.
9

Sun, Hao, Lan Chen, Xiaoran Hao, Chenji Liu, and Mao Ni. "An Energy-Efficient and Fast Scheme for Hybrid Storage Class Memory in an AIoT Terminal System." Electronics 9, no. 6 (June 17, 2020): 1013. http://dx.doi.org/10.3390/electronics9061013.

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Conventional main memory can no longer meet the requirements of low energy consumption and massive data storage in an artificial intelligence Internet of Things (AIoT) system. Moreover, the efficiency is decreased due to the swapping of data between the main memory and storage. This paper presents a hybrid storage class memory system to reduce the energy consumption and optimize IO performance. Phase change memory (PCM) brings the advantages of low static power and a large capacity to a hybrid memory system. In order to avoid the impact of poor write performance in PCM, a migration scheme implemented in the memory controller is proposed. By counting the write times and row buffer miss times in PCM simultaneously, the write-intensive data can be selected and migrated from PCM to dynamic random-access memory (DRAM) efficiently, which improves the performance of hybrid storage class memory. In addition, a fast mode with a tmpfs-based, in-memory file system is applied to hybrid storage class memory to reduce the number of data movements between memory and external storage. Experimental results show that the proposed system can reduce energy consumption by 46.2% on average compared with the traditional DRAM-only system. The fast mode increases the IO performance of the system by more than 30 times compared with the common ext3 file system.
10

Shin, Dongsuk, Hakbeom Jang, Kiseok Oh, and Jae W. Lee. "An Energy-Efficient DRAM Cache Architecture for Mobile Platforms With PCM-Based Main Memory." ACM Transactions on Embedded Computing Systems 21, no. 1 (January 31, 2022): 1–22. http://dx.doi.org/10.1145/3451995.

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A long battery life is a first-class design objective for mobile devices, and main memory accounts for a major portion of total energy consumption. Moreover, the energy consumption from memory is expected to increase further with ever-growing demands for bandwidth and capacity. A hybrid memory system with both DRAM and PCM can be an attractive solution to provide additional capacity and reduce standby energy. Although providing much greater density than DRAM, PCM has longer access latency and limited write endurance to make it challenging to architect it for main memory. To address this challenge, this article introduces CAMP, a novel DRAM c ache a rchitecture for m obile platforms with P CM-based main memory. A DRAM cache in this environment is required to filter most of the writes to PCM to increase its lifetime, and deliver highest efficiency even for a relatively small-sized DRAM cache that mobile platforms can afford. To address this CAMP divides DRAM space into two regions: a page cache for exploiting spatial locality in a bandwidth-efficient manner and a dirty block buffer for maximally filtering writes. CAMP improves the performance and energy-delay-product by 29.2% and 45.2%, respectively, over the baseline PCM-oblivious DRAM cache, while increasing PCM lifetime by 2.7×. And CAMP also improves the performance and energy-delay-product by 29.3% and 41.5%, respectively, over the state-of-the-art design with dirty block buffer, while increasing PCM lifetime by 2.5×.
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Статті в журналах Дисертації Книги

Дисертації з теми "PCM memory":

1

Grönberg, Axel. "Emerging Non-Volatile Memory and Initial Experiences with PCM Main Memory." Thesis, Uppsala universitet, Institutionen för informationsteknologi, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-407070.

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A group of new non-volatile memory technologies with characteristics making them worthy of consideration for different parts of the memory hierarchy, including the main memory, are emerging. In this thesis I discuss the state of STT-RAM, ReRAM and PCM technologies which are three of the front runners in this group of new technologies. I also simulate the performance of PCM used as main memory using Intel’s binary instrumentation framework Pin and compare it to DRAM to explore three research questions. Firstly, in the case of horizontally integrated PCM and DRAM I test a data mapping policy where an application’s stack is mapped to DRAM and the heap is mapped to PCM. I find that in the case of my simulation this mapping have no benefits since most of the stack is continually kept in the cache which causes the DRAM to end up unutilized. Secondly, I compare the read latency between PCM and DRAM and find an average increase 48 %for PCM. Thirdly, I compare the energy costs of two write policiesfor PCM. The first being write-through of dirty bytes at byte granularity and the second being full row buffer write-back. I find that the first method has on average less than a third of the energy cost compared to the second method.T
2

Seong, Nak Hee. "A reliable, secure phase-change memory as a main memory." Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/50123.

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The main objective of this research is to provide an efficient and reliable method for using multi-level cell (MLC) phase-change memory (PCM) as a main memory. As DRAM scaling approaches the physical limit, alternative memory technologies are being explored for future computing systems. Among them, PCM is the most mature with announced commercial products for NOR flash replacement. Its fast access latency and scalability have led researchers to investigate PCM as a feasible candidate for DRAM replacement. Moreover, the multi-level potential of PCM cells can enhance the scalability by increasing the number of bits stored in a cell. However, the two major challenges for adopting MLC PCM are the limited write endurance cycle and the resistance drift issue. To alleviate the negative impact of the limited write endurance cycle, this thesis first introduces a secure wear-leveling scheme called Security Refresh. In the study, this thesis argues that a PCM design not only has to consider normal wear-out under normal application behavior, most importantly, it must take the worst-case scenario into account with the presence of malicious exploits and a compromised OS to address the durability and security issues simultaneously. Security Refresh can avoid information leak by constantly migrating their physical locations inside the PCM, obfuscating the actual data placement from users and system software. In addition to the secure wear-leveling scheme, this thesis also proposes SAFER, a hardware-efficient multi-bit stuck-at-fault error recovery scheme which can function in conjunction with existing wear-leveling techniques. The limited write endurance leads to wear-out related permanent failures, and furthermore, technology scaling increases the variation in cell lifetime resulting in early failures of many cells. SAFER exploits the key attribute that a failed cell with a stuck-at value is still readable, making it possible to continue to use the failed cell to store data; thereby reducing the hardware overhead for error recovery. Another approach that this thesis proposes to address the lower write endurance is a hybrid phase-change memory architecture that can dynamically classify, detect, and isolate frequent writes from accessing the phase-change memory. This proposed architecture employs a small SRAM-based Isolation Cache with a detection mechanism based on a multi-dimensional Bloom filter and a binary classifier. The techniques are orthogonal to and can be combined with other wear-out management schemes to obtain a synergistic result. Lastly, this thesis quantitatively studies the current art for MLC PCM in dealing with the resistance drift problem and shows that the previous techniques such as scrubbing or error correction schemes are incapable of providing sufficient level of reliability. Then, this thesis proposes tri-level-cell (3LC) PCM and demonstrates that 3LC PCM can be a viable solution to achieve the soft error rate of DRAM and the performance of single-level-cell PCM.
3

SELMO, SIMONE. "Functional analysis of In-based nanowires for low power phase change memory applications." Doctoral thesis, Università degli Studi di Milano-Bicocca, 2017. http://hdl.handle.net/10281/153247.

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Phase change memories (PCMs), based on chalcogenide alloys (mainly Ge2Sb2Te5), are the most promising candidate for the realization of “Storage Class Memories”, which would fill the gap between ‘‘operation’’ and ‘‘storage’’ memories. PCMs are also one of the few currently available technologies for the implementation of nanoeletronic synapses in high density neuromorphic systems. The main improvements needed in order to exploit the full potential of PCMs in these innovative applications are the reduction of the programming currents and power consumption, and further cell downscaling. Thanks to their nano-sized active volume to be programmed and self-heating behavior, phase change nanowires (NWs) are expected to exhibit improved memory performances with respected to commonly used thin-film/heater-based structures. The Ph. D. Thesis of the candidate reports the study of the phase change properties of ultra-thin In-based NWs for low power consuming PCMs, exploring the more promising features of this class of materials with respect to the commonly considered Ge-Sb-Te alloys. In particular, the self-assembly of In-Sb-Te, In-doped Sb and In-Ge-Te NWs was successfully achieved by Metal Organic Chemical Vapour Deposition (MOCVD), coupled to vapour-liquid-solid mechanism, catalysed by catalyst nanoparticles. The parameters influencing the NW self-assembly were studied and the compositional, morphological and structural analysis of the grown structures was performed. In all cases, NWs of several μm in length and with diameters as small as 15 nm were obtained. The experimental contribution of the Ph. D. candidate to the NWs growth study was mainly related to the substrates preparation, catalyst deposition and, morphological and elemental analysis of the grown samples. Moreover, the Ph. D. candidate has performed the functional analysis of In3Sb1Te2 and In-doped Sb NW-based PCM devices. To conduct that analysis, a suitable fabrication procedure of the devices and an appropriate electrical measuring set-up have been identified. Reversible and well reproducible phase change memory switching was demonstrated for In3Sb1Te2 and In-doped Sb NW devices, showing low working parameters, such as “RESET” voltage, current and power. The obtained results support the conclusion that In-based ultra-thin NWs are potential building blocks for the realization of ultra-scaled, high performance PCM devices.
Phase change memories (PCMs), based on chalcogenide alloys (mainly Ge2Sb2Te5), are the most promising candidate for the realization of “Storage Class Memories”, which would fill the gap between ‘‘operation’’ and ‘‘storage’’ memories. PCMs are also one of the few currently available technologies for the implementation of nanoeletronic synapses in high density neuromorphic systems. The main improvements needed in order to exploit the full potential of PCMs in these innovative applications are the reduction of the programming currents and power consumption, and further cell downscaling. Thanks to their nano-sized active volume to be programmed and self-heating behavior, phase change nanowires (NWs) are expected to exhibit improved memory performances with respected to commonly used thin-film/heater-based structures. The Ph. D. Thesis of the candidate reports the study of the phase change properties of ultra-thin In-based NWs for low power consuming PCMs, exploring the more promising features of this class of materials with respect to the commonly considered Ge-Sb-Te alloys. In particular, the self-assembly of In-Sb-Te, In-doped Sb and In-Ge-Te NWs was successfully achieved by Metal Organic Chemical Vapour Deposition (MOCVD), coupled to vapour-liquid-solid mechanism, catalysed by catalyst nanoparticles. The parameters influencing the NW self-assembly were studied and the compositional, morphological and structural analysis of the grown structures was performed. In all cases, NWs of several μm in length and with diameters as small as 15 nm were obtained. The experimental contribution of the Ph. D. candidate to the NWs growth study was mainly related to the substrates preparation, catalyst deposition and, morphological and elemental analysis of the grown samples. Moreover, the Ph. D. candidate has performed the functional analysis of In3Sb1Te2 and In-doped Sb NW-based PCM devices. To conduct that analysis, a suitable fabrication procedure of the devices and an appropriate electrical measuring set-up have been identified. Reversible and well reproducible phase change memory switching was demonstrated for In3Sb1Te2 and In-doped Sb NW devices, showing low working parameters, such as “RESET” voltage, current and power. The obtained results support the conclusion that In-based ultra-thin NWs are potential building blocks for the realization of ultra-scaled, high performance PCM devices.
4

Garbin, Daniele. "Etude de la variabilité des technologies PCM et OxRAM pour leur utilisation en tant que synapses dans les systèmes neuromorphiques." Thesis, Université Grenoble Alpes (ComUE), 2015. http://www.theses.fr/2015GREAT133/document.

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Le cerveau humain est composé d’un grand nombre de réseaux neuraux interconnectés, dont les neurones et les synapses en sont les briques constitutives. Caractérisé par une faible consommation de puissance, de quelques Watts seulement, le cerveau humain est capable d’accomplir des tâches qui sont inaccessibles aux systèmes de calcul actuels, basés sur une architecture de type Von Neumann. La conception de systèmes neuromorphiques vise à réaliser une nouvelle génération de systèmes de calcul qui ne soit pas de type Von Neumann. L’utilisation de mémoire non-volatile innovantes en tant que synapses artificielles, pour application aux systèmes neuromorphiques, est donc étudiée dans cette thèse. Deux types de technologies de mémoires sont examinés : les mémoires à changement de phase (Phase-Change Memory, PCM) et les mémoires résistives à base d’oxyde (Oxide-based resistive Random Access Memory, OxRAM). L’utilisation des dispositifs PCM en tant que synapses de type binaire et probabiliste est étudiée pour l’extraction de motifs visuels complexes, en évaluant l’impact des conditions de programmation sur la consommation de puissance au niveau du système. Une nouvelle stratégie de programmation, qui permet de réduire l’impact du problème de la dérive de la résistance des dispositifs PCM est ensuite proposée. Il est démontré qu’en utilisant des dispositifs de tailles réduites, il est possible de diminuer la consommation énergétique du système. La variabilité des dispositifs OxRAM est ensuite évaluée expérimentalement par caractérisation électrique, en utilisant des méthodes statistiques, à la fois sur des dispositifs isolés et dans une matrice complète de mémoire. Un modèle qui permets de reproduire la variabilité depuis le niveau faiblement résistif jusqu’au niveau hautement résistif est ainsi développé. Une architecture de réseau de neurones de type convolutionnel est ensuite proposée sur la base de ces travaux éxperimentaux. La tolérance du circuit neuromorphique à la variabilité des OxRAM est enfin démontrée grâce à des tâches de reconnaissance de motifs visuels complexes, comme par exemple des caractères manuscrits ou des panneaux de signalisations routières
The human brain is made of a large number of interconnected neural networks which are composed of neurons and synapses. With a low power consumption of only few Watts, the human brain is able to perform computational tasks that are out of reach for today’s computers, which are based on the Von Neumann architecture. Neuromorphic hardware design, taking inspiration from the human brain, aims to implement the next generation, non-Von Neumann computing systems. In this thesis, emerging non-volatile memory devices, specifically Phase-Change Memory (PCM) and Oxide-based resistive memory (OxRAM) devices, are studied as artificial synapses in neuromorphic systems. The use of PCM devices as binary probabilistic synapses is studied for complex visual pattern extraction applications, evaluating the impact of the PCM programming conditions on the system-level power consumption.A programming strategy is proposed to mitigate the impact of PCM resistance drift. It is shown that, using scaled devices, it is possible to reduce the synaptic power consumption. The OxRAM resistance variability is evaluated experimentally through electrical characterization, gathering statistics on both single memory cells and at array level. A model that allows to reproduce OxRAM variability from low to high resistance state is developed. An OxRAM-based convolutional neural network architecture is then proposed on the basis of this experimental work. By implementing the computation of convolution directly in memory, the Von Neumann bottleneck is avoided. Robustness to OxRAM variability is demonstrated with complex visual pattern recognition tasks such as handwritten characters and traffic signs recognition
5

Balasubramanian, Sanchayeni. "Improving Hard Disk Drive Write IO Performance with Phase Change Memory as a Buffer Cache." University of Cincinnati / OhioLINK, 2017. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1511881125562903.

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6

Baek, Seungcheol. "High-performance memory system architectures using data compression." Diss., Georgia Institute of Technology, 2014. http://hdl.handle.net/1853/51863.

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The Chip Multi-Processor (CMP) paradigm has cemented itself as the archetypal philosophy of future microprocessor design. Rapidly diminishing technology feature sizes have enabled the integration of ever-increasing numbers of processing cores on a single chip die. This abundance of processing power has magnified the venerable processor-memory performance gap, which is known as the ”memory wall”. To bridge this performance gap, a high-performing memory structure is needed. An attractive solution to overcoming this processor-memory performance gap is using compression in the memory hierarchy. In this thesis, to use compression techniques more efficiently, compressed cacheline size information is studied, and size-aware cache management techniques and hot-cacheline prediction for dynamic early decompression technique are proposed. Also, the proposed works in this thesis attempt to mitigate the limitations of phase change memory (PCM) such as low write performance and limited long-term endurance. One promising solution is the deployment of hybridized memory architectures that fuse dynamic random access memory (DRAM) and PCM, to combine the best attributes of each technology by using the DRAM as an off-chip cache. A dual-phase compression technique is proposed for high-performing DRAM/PCM hybrid environments and a multi-faceted wear-leveling technique is proposed for the long-term endurance of compressed PCM. This thesis also includes a new compression-based hybrid multi-level cell (MLC)/single-level cell (SLC) PCM management technique that aims to combine the performance edge of SLCs with the higher capacity of MLCs in a hybrid environment.
7

Trabelsi, Ahmed. "Modulation des niveaux de résistance dans une mémoire PCM pour des applications neuromorphiques." Electronic Thesis or Diss., Université Grenoble Alpes, 2024. http://www.theses.fr/2024GRALT027.

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La croissance exponentielle des données au cours des dernières années a entraîné une augmentation significative de la consommation d'énergie, créant ainsi un besoin urgent de technologies de mémoire innovantes pour surmonter les limitations des solutions conventionnelles. Cette inondation de données a entraîné une augmentation prévue de la consommation dans les centres de données, avec une multiplication par quatre des données d'ici 2025 par rapport au volume actuel. Pour relever ce défi, des technologies de mémoire émergentes telles que la RRAM (RAM résistive), la PCM (mémoire à changement de phase) et la MRAM (RAM magnéto-résistive) sont en cours de développement pour offrir une haute densité, des temps d'accès rapides et une non-volatilité, révolutionnant ainsi les solutions de stockage et de mémoire (Molas & Nowak, 2021).Une technique prometteuse pour répondre au besoin de technologies de mémoire innovantes est l'utilisation de la modulation de fréquence pour moduler la résistance dans la PCM, qui est un aspect crucial de son utilisation en informatique neuromorphique. La PCM est une technologie de mémoire non volatile basée sur la transition de phase réversible entre les phases amorphe et cristalline de certains matériaux. La capacité de modifier les niveaux de conductance rend la PCM bien adaptée aux réalisations synaptiques en informatique neuromorphique. La cristallisation progressive du matériau à changement de phase et l'augmentation subséquente de la conductance du dispositif permettent à la PCM d'être utilisée dans des applications neuromorphiques. De plus, des réseaux neuronaux basés sur la mémoire PCM ont été développés, et l'effet de dérive de la résistance dans la PCM a été quantifié, ouvrant de nouvelles voies pour le développement d'accélérateurs neuromorphiques à base de memristors PCM. De plus, la modulation de fréquence a été identifiée comme une technique prometteuse pour moduler la résistance dans la PCM. Cette approche peut être appliquée à la PCM ainsi qu'à la RRAM, et on s'attend à ce qu'elle produise des effets d'apprentissage améliorés dans des réseaux plus complexes utilisant des cellules multi-niveaux (Wang et al., 2011). L'objectif principal de cette thèse est d'explorer des méthodes innovantes pour contrôler les niveaux de résistance dans les dispositifs PCM en mettant l'accent sur leur application dans les systèmes neuromorphiques. La recherche implique une compréhension approfondie des mécanismes sous-jacents aux dispositifs PCM et une identification des paramètres susceptibles d'influencer la fiabilité de ces dispositifs. De plus, la thèse vise à proposer une nouvelle approche pour moduler efficacement les niveaux de résistance dans les dispositifs PCM, contribuant ainsi aux avancées dans ce domaine
The exponential growth of data in recent years has led to a significant increase in energy consumption, creating a pressing need for innovative memory technologies to overcome the limitations of conventional solutions. This data deluge has resulted in a forecasted consumption surge in data centers, with an expected fourfold increase in data by 2025 compared to the present volume. To address this challenge, emerging memory technologies such as RRAM (Resistive RAM), PCM (Phase-Change Memory), and MRAM (Magnetoresistive RAM) are being developed to offer high density, fast access times, and non-volatility, thereby revolutionizing storage and memory solutions (Molas & Nowak, 2021).One promising technique to address the need for innovative memory technologies is the use of frequency modulation to modulate resistance in PCM which is a crucial aspect of its use in neuromorphic computing. PCM is a non-volatile memory technology based on the reversible phase transition between amorphous and crystalline phases of certain materials. The ability to alter conductance levels makes PCM well-suited for synaptic realizations in neuromorphic computing. The progressive crystallization of the phase-change material and the subsequent increase in device conductance enable PCM to be used in neuromorphic applications. Additionally, PCM-based memristor neural networks have been developed, and the resistance drift effect in PCM has been quantified, opening up new paths for the development of PCM-based memristor neuromorphic accelerators. Furthermore, frequency modulation has been identified as a promising technique to modulate resistance in PCM. This approach can be applied to PCM as well as RRAM, and it is expected to yield improved learning effects in more complex networks using multi-level cells (Wang et al., 2011). The primary aim of this thesis is to explore innovative methods for controlling resistance levels in PCM devices with a focus on their application in neuromorphic systems. The research involves a comprehensive understanding of the mechanisms underlying PCM devices and an identification of parameters that may influence the reliability of these devices. Additionally, the thesis aims to propose a novel approach to effectively modulate resistance levels in PCM devices, contributing to advancements in this field
8

Jensen, Peter, and Christopher Thacker. "A NEW GENERATION OF RECORDING TECHNOLOGY THE SOLID STATE RECORDER." International Foundation for Telemetering, 1998. http://hdl.handle.net/10150/607372.

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International Telemetering Conference Proceedings / October 26-29, 1998 / Town & Country Resort Hotel and Convention Center, San Diego, California
The Test & Evaluation community is starting to migrate toward solid state recording. This paper outlines some of the important areas that are new to solid state recording as well as examining some of the issues involved in moving to a direct recording methodology. Some of the parameters used to choose a solid state memory architecture are included. A matrix to compare various methods of data recording, such as solid state and magnetic tape recording, will be discussed. These various methods will be evaluated using the following parameters: Ruggedness (Shock, Vibration, Temperature), Capacity, and Reliability (Error Correction). A short discussion of data formats with an emphasis on efficiency and usability is included.
9

Kiouseloglou, Athanasios. "Caractérisation et conception d' architectures basées sur des mémoires à changement de phase." Thesis, Université Grenoble Alpes (ComUE), 2015. http://www.theses.fr/2015GREAT128/document.

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Les mémoires à base de semi-conducteur sont indispensables pour les dispositifs électroniques actuels. La demande croissante pour des dispositifs mémoires fortement miniaturisées a entraîné le développement de mémoires non volatiles fiables qui sont utilisées dans des systèmes informatiques pour le stockage de données et qui sont capables d'atteindre des débits de données élevés, avec des niveaux de dissipation d'énergie équivalents voire moindres que ceux des technologies mémoires actuelles.Parmi les technologies de mémoires non-volatiles émergentes, les mémoires à changement de phase (PCM) sont le candidat le plus prometteur pour remplacer la technologie de mémoire Flash conventionnelle. Les PCM offrent une grande variété de fonctions, comme une lecture et une écriture rapide, un excellent potentiel de miniaturisation, une compatibilité CMOS et des performances élevées de rétention de données à haute température et d'endurance, et peuvent donc ouvrir la voie à des applications non seulement pour les dispositifs mémoires, mais également pour les systèmes informatiques à hautes performances. Cependant, certains problèmes de fiabilité doivent encore être résolus pour que les PCM se positionnent comme un remplacement concurrentiel de la mémoire Flash.Ce travail se concentre sur l'étude de mémoires à changement de phase intégrées afin d'optimiser leurs performances et de proposer des solutions pour surmonter les principaux points critiques de la technologie, ciblant des applications à hautes températures. Afin d'améliorer la fiabilité de la technologie, la stœchiométrie du matériau à changement de phase a été conçue de façon appropriée et des dopants ont été ajoutés, optimisant ainsi la stabilité thermique. Une diminution de la vitesse de programmation est également rapportée, ainsi qu'un drift résiduel de la résistance de l'état de faiblement résistif vers des valeurs de résistance plus élevées au cours du temps.Une nouvelle technique de programmation est introduite, permettant d'améliorer la vitesse de programmation des dispositifs et, dans le même temps, de réduire avec succès le phénomène de drift en résistance. Par ailleurs, un algorithme de programmation des PCM multi-bits est présenté. Un générateur d'impulsions fournissant des impulsions avec la tension souhaitée en sortie a été conçu et testé expérimentalement, répondant aux demandes de programmation d'une grande variété de matériaux innovants et en permettant la programmation précise et l’optimisation des performances des PCM
Semiconductor memory has always been an indispensable component of modern electronic systems. The increasing demand for highly scaled memory devices has led to the development of reliable non-volatile memories that are used in computing systems for permanent data storage and are capable of achieving high data rates, with the same or lower power dissipation levels as those of current advanced memory solutions.Among the emerging non-volatile memory technologies, Phase Change Memory (PCM) is the most promising candidate to replace conventional Flash memory technology. PCM offers a wide variety of features, such as fast read and write access, excellent scalability potential, baseline CMOS compatibility and exceptional high-temperature data retention and endurance performances, and can therefore pave the way for applications not only in memory devices, but also in energy demanding, high-performance computer systems. However, some reliability issues still need to be addressed in order for PCM to establish itself as a competitive Flash memory replacement.This work focuses on the study of embedded Phase Change Memory in order to optimize device performance and propose solutions to overcome the key bottlenecks of the technology, targeting high-temperature applications. In order to enhance the reliability of the technology, the stoichiometry of the phase change material was appropriately engineered and dopants were added, resulting in an optimized thermal stability of the device. A decrease in the programming speed of the memory technology was also reported, along with a residual resistivity drift of the low resistance state towards higher resistance values over time.A novel programming technique was introduced, thanks to which the programming speed of the devices was improved and, at the same time, the resistance drift phenomenon could be successfully addressed. Moreover, an algorithm for programming PCM devices to multiple bits per cell using a single-pulse procedure was also presented. A pulse generator dedicated to provide the desired voltage pulses at its output was designed and experimentally tested, fitting the programming demands of a wide variety of materials under study and enabling accurate programming targeting the performance optimization of the technology
10

Navarro, Gabriele. "Analyse de la fiabilité de mémoires à changement de phase embarquées basées sur des matériaux innovants." Phd thesis, Université de Grenoble, 2013. http://tel.archives-ouvertes.fr/tel-01061792.

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Les Mémoires ont de plus en plus importance à l'époque actuelle, et sont fondamentales pour la définition de tous les systèmes électroniques avec lesquels nous entrons en contact dans notre vie quotidienne. Les mémoires non-volatiles (NVM), représentées par la technologie Flash, ont pu suivre jusqu'à présent l'effort à la miniaturisation pour satisfaire la demande croissante de densité de mémoire exigée par le marché. Cependant, la réduction de la taille du dispositif de mémoire est de plus en plus difficile et la complexité technologique demandé a augmenté le coût par octet. Dans ce contexte, les technologies de mémoire innovantes deviennent non seulement une alternative, mais la seule solution possible pour fournir une densité plus élevée à moindre coût, une meilleure fonctionnalité et une faible consommation d'énergie. Les Mémoires à Changement de Phase (PCM) sont considérées comme la solution de pointe pour la future génération de mémoires non-volatiles, grâce à leur non-volatilité , scalabilité, "bit-alterability", grande vitesse de lecture et d'écriture, et cyclabilité élevée. Néanmoins, certains problèmes de fiabilité restent à surmonter afin de rendre cette technologie un remplacement valable de la technologie Flash dans toutes les applications. Plus en détail, la conservation des données à haute température, est l'une des principales exigences des applications embarquées industrielles et automobiles. Cette thèse se concentre sur l'étude des mémoires à changement de phase pour des applications embarquées, dans le but d'optimiser le dispositif de mémoire et enfin de proposer des solutions pour surmonter les principaux obstacles de cette technologie, en abordant notamment les applications automobiles. Nous avons conçu, fabriqué et testé des dispositifs PCM basés sur des structures reconnues et innovantes, en analysant leurs avantages et inconvénients, et en évaluant l'impact de la réduction de la taille. Notre analyse de fiabilité a conduit au développement d'un système de caractérisation dédié à caractériser nos cellules PCM avec des impulsions de l'ordre de la nanoseconde, et à la mise en oeuvre d'un outil de simulation basé sur un solveur thermoélectrique et sur l'approche numérique "Level Set", pour comprendre les différentes mécanismes qui ont lieu dans nos cellules pendant les opérations de programmation. Afin de répondre aux spécifications du marché des mémoires non-volatiles embarquées, nous avons conçu le matériau à changement de phase intégré dans le dispositif PCM avec deux principales approches: la variation de la stoechiométrie et l'ajout de dopants. Nous avons démontré et expliqué comment la rétention des données dans les dispositifs PCM à base de GeTe peut être améliorée avec l'augmentation de la concentration de Te, et comment les inclusions de SiO2 peuvent réduire les défauts causés par la tension de lecture à températures de fonctionnement élevées. En outre, nous avons présenté les avantages sur la réduction de la puissance de programmation du dopage de carbone dans les dispositifs à base de GST. Enfin, nous avons étudié les effets de l'enrichissement en Ge dans le GST, combiné avec le dopage N et C, intégré dans des cellules PCM à l'état de l'art. Grâce à l'introduction d'une nouvelle technique de programmation, nous avons démontré la possibilité d'augmenter la vitesse de programmation de ces dispositifs, caractérisés par des performances de rétention des données parmi les meilleurs rapportés dans la littérature, et de réduire le phénomène de la dérive de la résistance qui affecte la stabilité de l'état programmé des cellules PCM. Nous avons donc prouvé, avec ces derniers résultats, la validité de la technologie PCM pour les applications embarquées.
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Книги з теми "PCM memory":

1

Wadlow, Thomas A. Memory resident programming on the IBM PC. Reading, Mass: Addison-Wesley, 1987.

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2

Prosise, Jeff. PCmagazine DOS 6 memory management with utilities. Emeryville, Calif: Ziff-Davis Press, 1993.

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3

Mueller, Scott. Upgrading and repairing PCs. Indianapolis, IN: Que, 1998.

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4

Mueller, Scott. Upgrading and repairing PCs. Indianapolis, Ind: Que, 2000.

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5

Mueller, Scott. Upgrading and repairing PCs. Indianapolis, Ind: Que, 2001.

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6

Hyman, Michael I. Memory resident utilities, interrupts, and disk management with MS and PC DOS. Portland, Or: Management Information Source, 1986.

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7

Prosise, Jeff. PC magazine DOS 6 memory management with utilities. Emeryville, Calif: Ziff-Davis Press, 1993.

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8

Scott, Mueller. Upgrading and repairing PCs. Indianapolis, IN: Que Pub., 2008.

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9

Scott, Mueller. Upgrading and repairing PCs. Indianapolis, IN: Que, 2004.

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10

Scott, Mueller. Upgrading and repairing PCs. 2nd ed. Indianapolis, IN: Que, 2013.

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Частини книг з теми "PCM memory":

1

Gleixner, Robert. "PCM Main Reliability Features." In Phase Change Memory, 89–124. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-69053-7_5.

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2

Villa, Corrado. "PCM Array Architecture and Management." In Phase Change Memory, 285–311. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-69053-7_10.

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3

Sousa, Véronique, and Gabriele Navarro. "Material Engineering for PCM Device Optimization." In Phase Change Memory, 181–222. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-69053-7_7.

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4

Atwood, Gregory. "PCM Applications and an Outlook to the Future." In Phase Change Memory, 313–24. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-69053-7_11.

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5

Noé, Pierre, and Françoise Hippert. "Structure and Properties of Chalcogenide Materials for PCM." In Phase Change Memory, 125–79. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-69053-7_6.

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6

Kong, Dejiang, and Fei Wu. "Visual Dialog with Multi-turn Attentional Memory Network." In Advances in Multimedia Information Processing – PCM 2018, 611–21. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-030-00776-8_56.

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7

Rahiman, Amir Rizaan Abdul, and Putra Sumari. "Probability Based Page Data Allocation Scheme in Flash Memory." In Advances in Multimedia Information Processing - PCM 2009, 300–310. Berlin, Heidelberg: Springer Berlin Heidelberg, 2009. http://dx.doi.org/10.1007/978-3-642-10467-1_26.

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8

Noh, Tae Hoon, and Se Jin Kwon. "Memory Management Strategy for PCM-Based IoT Cloud Server." In Lecture Notes in Electrical Engineering, 69–77. Singapore: Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-13-1059-1_7.

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9

Chen, Kaimeng, Peiquan Jin, and Lihua Yue. "Efficient Buffer Management for PCM-Enhanced Hybrid Memory Architecture." In Web Technologies and Applications, 29–40. Cham: Springer International Publishing, 2015. http://dx.doi.org/10.1007/978-3-319-25255-1_3.

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10

Li, Fu, Shaowu Yang, Xiaodong Yi, and Xuejun Yang. "Towards Visual SLAM with Memory Management for Large-Scale Environments." In Advances in Multimedia Information Processing – PCM 2017, 776–86. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-77383-4_76.

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Тези доповідей конференцій з теми "PCM memory":

1

Ferreira, Alexandre P., Miao Zhou, Santiago Bock, Bruce Childers, Rami Melhem, and Daniel Mosse. "Increasing PCM main memory lifetime." In 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010). IEEE, 2010. http://dx.doi.org/10.1109/date.2010.5456923.

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2

Liu, Yining, Chuangshi Zhou, and Xiaohua Cheng. "Hybrid SSD with PCM." In 2011 11th Annual Non-Volatile Memory Technology Symposium (NVMTS). IEEE, 2011. http://dx.doi.org/10.1109/nvmts.2011.6137103.

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3

Chang, Yu-Ming, Yuan-Hao Chang, Hsiu-Chang Chen, and Tei-Wei Kuo. "Enabling Hybrid PCM Memory System with Inherent Memory Management." In RACS '16: International Conference on Research in Adaptive and Convergent Systems. New York, NY, USA: ACM, 2016. http://dx.doi.org/10.1145/2987386.2987398.

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4

Arjomand, Mohammad, Amin Jadidi, Mahmut T. Kandemir, Anand Sivasubramaniam, and Chita Das. "MLC PCM main memory with accelerated read." In 2016 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS). IEEE, 2016. http://dx.doi.org/10.1109/ispass.2016.7482082.

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5

Jeong, Hongsik. "High density PCM(phase change memory) technology." In 2016 International SoC Design Conference (ISOCC). IEEE, 2016. http://dx.doi.org/10.1109/isocc.2016.7799850.

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6

Boybat, I., S. R. Nandakumar, M. Le Gallo, B. Rajendran, Y. Leblebici, A. Sebastian, and E. Eleftheriou. "Impact of conductance drift on multi-PCM synaptic architectures." In 2018 Non-Volatile Memory Technology Symposium (NVMTS). IEEE, 2018. http://dx.doi.org/10.1109/nvmts.2018.8603100.

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7

Calderoni, A., M. Ferro, D. Ventrice, P. Fantini, and D. Ielmini. "Physical Modeling and Control of Switching Statistics in PCM Arrays." In 2011 3rd IEEE International Memory Workshop (IMW). IEEE, 2011. http://dx.doi.org/10.1109/imw.2011.5873230.

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8

Bez, Roberto. "Chalcogenide PCM: a memory technology for next decade." In 2009 IEEE International Electron Devices Meeting (IEDM). IEEE, 2009. http://dx.doi.org/10.1109/iedm.2009.5424415.

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9

Shafiee, Amin, Benoit Charbonnier, Sudeep Pasricha, and Mahdi Nikdast. "Design Space Exploration for PCM-based Photonic Memory." In GLSVLSI '23: Great Lakes Symposium on VLSI 2023. New York, NY, USA: ACM, 2023. http://dx.doi.org/10.1145/3583781.3590228.

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10

Jin, Peiquan, Xiaoliang Wang, Dezhi Zhang, and Lihua Yue. "Effective simulation of DRAM/PCM-based hybrid memory." In the Thirteenth ACM International Conference. New York, New York, USA: ACM Press, 2017. http://dx.doi.org/10.1145/3125503.3125564.

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Звіти організацій з теми "PCM memory":

1

Murphy, Richard C. Building more powerful less expensive supercomputers using Processing-In-Memory (PIM) LDRD final report. Office of Scientific and Technical Information (OSTI), September 2009. http://dx.doi.org/10.2172/993898.

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2

Mott, Joanna, Heather Brown, Di Kilsby, Emily Eller, and Tshering Choden. Ferramenta de auto-avaliação de Igualdade de Género e Inclusão Social. The Sanitation Learning Hub, Institute of Development Studies, November 2022. http://dx.doi.org/10.19088/slh.2022.021.

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Анотація:
Este guia foi criado para o pessoal de implementação, projectos de investigação e organizações de WASH, que está empenhado em melhorar a prática de IGIS nos seus projectos e organizações. Destina-se a gestores de programas, assessores IGIS e investigadores de IGIS e qualquer membro do pessoal da sua organização interessado em melhorar a prática de IGIS. O guia detalha as funções e responsabilidades específicas do Ponto de Contacto (PC), do facilitador, dos participantes e auxiliares do processo de auto-avaliação.

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