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Готові списки джерел за темами / Memory and power applications

Добірка наукової літератури з теми "Memory and power applications"

Автор: Grafiati

Опубліковано: 7 липня 2024

Оновлено: 7 липня 2024

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Статті в журналах з теми "Memory and power applications":

1

Zhang, Kaiqiang, Dongyang Ou, Congfeng Jiang, Yeliang Qiu, and Longchuan Yan. "Power and Performance Evaluation of Memory-Intensive Applications." Energies 14, no. 14 (July 6, 2021): 4089. http://dx.doi.org/10.3390/en14144089.

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In terms of power and energy consumption, DRAMs play a key role in a modern server system as well as processors. Although power-aware scheduling is based on the proportion of energy between DRAM and other components, when running memory-intensive applications, the energy consumption of the whole server system will be significantly affected by the non-energy proportion of DRAM. Furthermore, modern servers usually use NUMA architecture to replace the original SMP architecture to increase its memory bandwidth. It is of great significance to study the energy efficiency of these two different memory architectures. Therefore, in order to explore the power consumption characteristics of servers under memory-intensive workload, this paper evaluates the power consumption and performance of memory-intensive applications in different generations of real rack servers. Through analysis, we find that: (1) Workload intensity and concurrent execution threads affects server power consumption, but a fully utilized memory system may not necessarily bring good energy efficiency indicators. (2) Even if the memory system is not fully utilized, the memory capacity of each processor core has a significant impact on application performance and server power consumption. (3) When running memory-intensive applications, memory utilization is not always a good indicator of server power consumption. (4) The reasonable use of the NUMA architecture will improve the memory energy efficiency significantly. The experimental results show that reasonable use of NUMA architecture can improve memory efficiency by 16% compared with SMP architecture, while unreasonable use of NUMA architecture reduces memory efficiency by 13%. The findings we present in this paper provide useful insights and guidance for system designers and data center operators to help them in energy-efficiency-aware job scheduling and energy conservation.

2

Kumar, S., M. Santhanalakshmi, and R. Navaneethakrishnan. "Content addressable memory for energy efficient computing applications." Scientific Temper 14, no. 02 (June 6, 2023): 430–36. http://dx.doi.org/10.58414/scientifictemper.2023.14.2.30.

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Content Addressable Memory (CAM) also known as associate memory isa special kind of semiconductor memory device that works differently from conventional Random Access Memory (RAM). A Content Addressable Memory is a memory unit that matches content over a single clock rather than using addresses. Its inherent parallel search mechanism makes it more advantageous than RAM in terms of speed of search operation. Designers aim to reduce two design characteristics: increasing silicon size and power consumption. As the need for CAM increases, the problem of power consumption also increases. Recent research on CAM is concentrated around diminishing power utilization without forfeiting speed or area. The main reason for the high-power consumption in conventional CAM architecture is devoid of control over the voltage on the Match Line recharge and Search Line precharge. A novel CAM architecture is proposed by removing the necessity of the search line recharge and also by introducing a transistor with gate connected to ML_Eval input that act as a control over the search operation. An Extra transistor with gate connected to Mask_Bar decides whether the circuit can be operated as Ternary Content Addressable Memory (TCAM) or Binary Content Addressable Memory (Bi-CAM). This CAM Architecture is found to be power efficient up to 50% due to the control over recharged voltage on ML. It is also inferred that the delay associated with the search operation can be reduced to a certain extent. The proposed CAM architecture is simulated using Cadence Virtuoso IC 6.1.6 in General Process Design Kit (GPDK) with90nm technology.

3

Tyler, Neil. "Tempo Targets Low-Power Chips for AI Applications." New Electronics 52, no. 13 (July 9, 2019): 7. http://dx.doi.org/10.12968/s0047-9624(22)61557-8.

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4

Kumar Lamba, Anil, and Anuradha Konidena. "IoT Applications: Analysis of MTCMOS Cache Memory Architecture in a Processor." Journal of Futuristic Sciences and Applications 2, no. 1 (2019): 24–33. http://dx.doi.org/10.51976/jfsa.211905.

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The main goals of the suggested inquiry are to measure how much power an amplifier uses, determine how much leaks through SRAM, and use the data. The main issue with the cache memory's design was leakage power. The charge transfer sense amplifier had the lowest value compared to other sense amplifiers' power consumption figures, even though we used MTCMOS and Footer Stack to reduce leaky power. The design included MTCMOS-CTSA and MTCMOS-SRAM memory to reduce power consumption. Fusing CTSA and SRAM with MTCMOS technology can produce low-power cache memory. This cache memory uses a lot less power than CTSA and SRAM devices

5

Zuo, Ze Yu, Wei Hu, Rui Xin Hu, Heng Xiong, Wen Bin Du, and Xiu Cai. "Efficient Scratchpad Memory Management for Mobile Multimedia Application." Advanced Materials Research 748 (August 2013): 932–35. http://dx.doi.org/10.4028/www.scientific.net/amr.748.932.

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Mobile devices have been popular in recent years and the proliferation of mobile devices inspires the interest in mobile multimedia applications. However, memory is always the bottleneck in the traditional memory hierarchy. Scratchpad memory (SPM) is a promising on-chip SRAM to solve such problem. It has faster access time and less power-consumption compared to cache and off-chip memory. In this paper, we propose the efficient scratchpad memory management approach for mobile multimedia applications. SPM is partitioned for the assignment of the slices of the applications based on the profiling and the recorded history. Through the use of SPM, the memory footprint of mobile multimedia applications will be reduced for better performance and less power-consumption. The experimental results show that our approach is able to significantly reduce the power consumption and improve the performance of mobile multimedia applications.

6

Birla, Shilpi. "Variability aware FinFET SRAM cell with improved stability and power for low power applications." Circuit World 45, no. 4 (November 4, 2019): 196–207. http://dx.doi.org/10.1108/cw-12-2018-0098.

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Purpose Major area of a die is consumed in memory components. Almost 60-70% of chip area is being consumed by “Memory Circuits”. The dominant memory in this market is SRAM, even though the SRAM size is larger than embedded DRAM, as SRAM does not have yield issues and the cost is not high as compared to DRAM. At the same time, the other attractive feature for the SRAM is speed, and it can be used for low power applications. CMOS SRAM is the crucial component in microprocessor chips and applications, and as the said major portion of the area is dedicated to SRAM arrays, CMOS SRAM is considered to be the stack holders in the memory market. Because of the scaling feature of CMOS, SRAM had its hold in the market over the past few decades. In recent years, the limitations of the CMOS scaling have raised so many issues like short channel effects, threshold voltage variations. The increased thrust for alternative devices leads to FinFET. FinFET is emerging as one of the suitable alternatives for CMOS and in the region of memory circuits. Design/methodology/approach In this paper, a new 11 T SRAM cell using FinFET technology has been proposed, the basic component of the cell is the 6 T SRAM cell with 4 NMOS access transistors to improve the stability and also makes it a dual port memory cell. The proposed cell uses a header scheme in which one extra PMOS transistor is used which is biased at different voltages to improve the read and write stability thus, helps in reducing the leakage power and active power. Findings The cell shows improvement in RSNM (read static noise margin) with LP8T by 2.39× at sub-threshold voltage 2.68× with D6T SRAM cell, 5.5× with TG8T. The WSNM (write static noise margin) and HM (hold margin) of the SRAM cell at 0.9 V is 306 mV and 384 mV. It shows improvement at sub-threshold operation also. The leakage power is reduced by 0.125× with LP8T, 0.022× with D6T SRAM cell, TG8T and SE8T. The impact of process variation on cell stability is also discussed. Research limitations/implications The FinFet has been used in place of CMOS even though the FinFet has been not been a matured technology; therefore, pdk files have been used. Practical implications SRAM cell has been designed which has good stability and reduced leakage by which we can make an array and which can be used as SRAM array. Social implications The cell can be used for SRAM memory for low power consumptions. Originality/value The work has been done by implementing various leakage techniques to design a stable and improved SRAM cell. The advantage of this work is that the cell has been working for low voltage without degrading the stability factor.

7

Marchal, P., J. I. Gomez, D. Atienza, S. Mamagkakis, and F. Catthoor. "Power aware data and memory management for dynamic applications." IEE Proceedings - Computers and Digital Techniques 152, no. 2 (2005): 224. http://dx.doi.org/10.1049/ip-cdt:20045077.

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8

K, Bharathi, and Vijayakumar S. "QCA Design of Encoder for Low Power Memory Applications." International Journal of Electronics and Communication Engineering 3, no. 11 (November 25, 2016): 13–15. http://dx.doi.org/10.14445/23488549/ijece-v3i11p114.

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9

Fang, Juan, Jiajia Lu, Mengxuan Wang, and Hui Zhao. "A Performance Conserving Approach for Reducing Memory Power Consumption in Multi-Core Systems." Journal of Circuits, Systems and Computers 28, no. 07 (June 27, 2019): 1950113. http://dx.doi.org/10.1142/s0218126619501135.

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With more cores integrated into a single chip and the fast growth of main memory capacity, the DRAM memory design faces ever increasing challenges. Previous studies have shown that DRAM can consume up to 40% of the system power, which makes DRAM a major factor constraining the whole system’s growth in performance. Moreover, memory accesses from different applications are usually interleaved and interfere with each other, which further exacerbates the situation in memory system management. Therefore, reducing memory power consumption has become an urgent problem to be solved in both academia and industry. In this paper, we first proposed a novel strategy called Dynamic Bank Partitioning (DBP), which allocates banks to different applications based on their memory access characteristics. DBP not only effectively eliminates the interference among applications, but also fully takes advantage of bank level parallelism. Secondly, to further reduce power consumption, we propose an adaptive method to dynamically select an optimal page policy for each bank according to the characteristics of memory accesses that each bank receives. Our experimental results show that our strategy not only improves the system performance but also reduces the memory power consumption at the same time. Our proposed scheme can reduce memory power consumption up to 21.2% (10% on average across all workloads) and improve the performance to some extent. In the case that workloads are built with mixed applications, our scheme reduces the power consumption by 14% on average and improves the performance up to 12.5% (3% on average).

10

Yadav, Pradeep Singh, and Harsha Jain. "Review of 6T SRAM for Embedded Memory Applications." Indian Journal of VLSI Design 3, no. 1 (March 30, 2023): 24–30. http://dx.doi.org/10.54105/ijvlsid.a1217.033123.

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Due to the substantial impact embedded Static Random Access Memory (SRAM)s have on the overall system and their relatively limited design, it is essential to manage embedded SRAM trade-offs strategically. SRAMs have power, performance and density trade-offs in general. In all applications, all three dimensions are necessary to some extent; accordingly, embedded SRAM design must incorporate the most crucial system-specific requirements when developing embedded SRAM. This paper discusses many SRAM factors, including Static Noise Margin (SNM), Read Access Time (RAT),Write Access Time (WAT), Read Stability and Write Ability, Power, Data Retention Voltage (DRV), and Process Control. All these factors are crucial when designing SRAM for embedded memory applications. There has also been a discussion of the parameter comparisons and the literature review of the current papers.

Більше джерел

Дисертації з теми "Memory and power applications":

1

Wang, Xin. "Power Efficient Embedded Memory Design for Mobile Video Applications." Thesis, North Dakota State University, 2015. https://hdl.handle.net/10365/27621.

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This thesis mainly addresses the issue of low-power technology for streaming media applications. In order to ensure high output video quality under low-voltage supply, the proposed 8-bit pixel memory is sized by different bit positions. A novel MSEpixel estimation method is then developed according to bit failure rates to directly evaluate the video quality for every 8-bit sizing combination. Based on this estimation, one area-priory and one quality-priority mobile video applications are proposed by SPIDER algorithms. The results show that both luma and chroma data should be considered. More than 70% power is saved in memory units by using sizing-priority SPIDER algorithms. And the proposed SPIDER design methodology for low-voltage application is a feasible and efficient trade-off between the memory reliability and area overhead. Besides, a sample SRAM chip is designed for tape-out for further verification of the proposed SPIDER methodology.

2

SELMO, SIMONE. "Functional analysis of In-based nanowires for low power phase change memory applications." Doctoral thesis, Università degli Studi di Milano-Bicocca, 2017. http://hdl.handle.net/10281/153247.

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Phase change memories (PCMs), based on chalcogenide alloys (mainly Ge2Sb2Te5), are the most promising candidate for the realization of “Storage Class Memories”, which would fill the gap between ‘‘operation’’ and ‘‘storage’’ memories. PCMs are also one of the few currently available technologies for the implementation of nanoeletronic synapses in high density neuromorphic systems. The main improvements needed in order to exploit the full potential of PCMs in these innovative applications are the reduction of the programming currents and power consumption, and further cell downscaling. Thanks to their nano-sized active volume to be programmed and self-heating behavior, phase change nanowires (NWs) are expected to exhibit improved memory performances with respected to commonly used thin-film/heater-based structures. The Ph. D. Thesis of the candidate reports the study of the phase change properties of ultra-thin In-based NWs for low power consuming PCMs, exploring the more promising features of this class of materials with respect to the commonly considered Ge-Sb-Te alloys. In particular, the self-assembly of In-Sb-Te, In-doped Sb and In-Ge-Te NWs was successfully achieved by Metal Organic Chemical Vapour Deposition (MOCVD), coupled to vapour-liquid-solid mechanism, catalysed by catalyst nanoparticles. The parameters influencing the NW self-assembly were studied and the compositional, morphological and structural analysis of the grown structures was performed. In all cases, NWs of several μm in length and with diameters as small as 15 nm were obtained. The experimental contribution of the Ph. D. candidate to the NWs growth study was mainly related to the substrates preparation, catalyst deposition and, morphological and elemental analysis of the grown samples. Moreover, the Ph. D. candidate has performed the functional analysis of In3Sb1Te2 and In-doped Sb NW-based PCM devices. To conduct that analysis, a suitable fabrication procedure of the devices and an appropriate electrical measuring set-up have been identified. Reversible and well reproducible phase change memory switching was demonstrated for In3Sb1Te2 and In-doped Sb NW devices, showing low working parameters, such as “RESET” voltage, current and power. The obtained results support the conclusion that In-based ultra-thin NWs are potential building blocks for the realization of ultra-scaled, high performance PCM devices.
Phase change memories (PCMs), based on chalcogenide alloys (mainly Ge2Sb2Te5), are the most promising candidate for the realization of “Storage Class Memories”, which would fill the gap between ‘‘operation’’ and ‘‘storage’’ memories. PCMs are also one of the few currently available technologies for the implementation of nanoeletronic synapses in high density neuromorphic systems. The main improvements needed in order to exploit the full potential of PCMs in these innovative applications are the reduction of the programming currents and power consumption, and further cell downscaling. Thanks to their nano-sized active volume to be programmed and self-heating behavior, phase change nanowires (NWs) are expected to exhibit improved memory performances with respected to commonly used thin-film/heater-based structures. The Ph. D. Thesis of the candidate reports the study of the phase change properties of ultra-thin In-based NWs for low power consuming PCMs, exploring the more promising features of this class of materials with respect to the commonly considered Ge-Sb-Te alloys. In particular, the self-assembly of In-Sb-Te, In-doped Sb and In-Ge-Te NWs was successfully achieved by Metal Organic Chemical Vapour Deposition (MOCVD), coupled to vapour-liquid-solid mechanism, catalysed by catalyst nanoparticles. The parameters influencing the NW self-assembly were studied and the compositional, morphological and structural analysis of the grown structures was performed. In all cases, NWs of several μm in length and with diameters as small as 15 nm were obtained. The experimental contribution of the Ph. D. candidate to the NWs growth study was mainly related to the substrates preparation, catalyst deposition and, morphological and elemental analysis of the grown samples. Moreover, the Ph. D. candidate has performed the functional analysis of In3Sb1Te2 and In-doped Sb NW-based PCM devices. To conduct that analysis, a suitable fabrication procedure of the devices and an appropriate electrical measuring set-up have been identified. Reversible and well reproducible phase change memory switching was demonstrated for In3Sb1Te2 and In-doped Sb NW devices, showing low working parameters, such as “RESET” voltage, current and power. The obtained results support the conclusion that In-based ultra-thin NWs are potential building blocks for the realization of ultra-scaled, high performance PCM devices.

3

Morrison, Matthew Arthur. "Theory, Synthesis, and Application of Adiabatic and Reversible Logic Circuits For Security Applications." Scholar Commons, 2013. https://scholarcommons.usf.edu/etd/5082.

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Programmable reversible logic is emerging as a prospective logic design style for implementation in modern nanotechnology and quantum computing with minimal impact on circuit heat generation. Adiabatic logic is a design methodology for reversible logic in CMOS where the current flow through the circuit is controlled such that the energy dissipation due to switching and capacitor dissipation is minimized. Recent advances in reversible logic using and quantum computer algorithms allow for improved computer architectures. Production of cost-effective Secure Integrated Chips, such as Smart Cards, requires hardware designers to consider tradeoffs in size, security, and power consumption. In order to design successful security-centric designs, the low-level hardware must contain built-in protection mechanisms to supplement cryptographic algorithms such as AES and Triple DES by preventing side channel attacks, such as Differential Power Analysis (DPA). Dynamic logic obfuscates the output waveforms and the circuit operation, reducing the effectiveness of the DPA attack. Significant research exists in the design and analysis of locally optimal adiabatic elements towards mitigation of side channel attacks. However, none of these works have addressed the use of adiabatic logic in implementation of flexible and programmable hardware security policies. Nor has adiabatic logic been employed in hardware security applications such as trustworthy voting systems and data encryption standards. In this dissertation, I address theory, synthesis, and application of adiabatic and reversible logic circuits for security applications. First, two major debates in reversible computing are addressed. These debates must be addressed in order to devise computational logic primitives in any emerging quantum computing technology. First, we address whether charged based computing is limited due to the use of charge as a state variable. We propose the use of body biasing in CMOS adiabatic systems as a design methodology for reducing the need for gradually changing the energy barriers. Simulation results in HSPICE at 22nm are presented which show behavior of a source-memory device operating at sub-Landauer operation. Second, we address whether reversible logic can be used to design sequential computing structures, such as memory devices. we present an analysis of Quantum Turing Machines with sequential reversible logic structures, to show that the entropy gain is substantially less than the Landauer Barrier of kTln(2), which is the limiting factor for irreversible computing. A mathematical proof is presented showing bit erasure does not occur in sequential reversible logic structures, and that these devices are physically reversible as long as appropriate delay elements are inserted in the feedback paths to prevent race conditions. This proof validates implementation of sequential reversible logic towards ultra-low power computing. Next, a novel algorithm for synthesis of adiabatic circuits in CMOS is proposed. This approach is unique because it correlates the offsets in the permutation matrix to the transistors required for synthesis, instead of determining an equivalent circuit and substituting a previously synthesized circuit from a library. Parallelism is used, and the bijective properties of the device to achieve synthesis of the logic structure in O(n) time. Then, using the ESPRESSO heuristic for minimization of Boolean functions method on each output node in parallel, we optimize the synthesized circuit. It is demonstrated that the algorithm produces a 32.86% improvement over previously synthesized circuit benchmarks. For stronger mitigation of DPA attacks, we propose the implementation of Adiabatic Dynamic Differential Logic for applications in secure IC design. Such an approach is effective in reducing power consumption, demonstrated using HSPICE simulations with 22nm predictive technology. The benefits of our design are demonstrated by comparing instantaneous power waveforms and observing the magnitude of differential power spikes during switching events. First, simulation results for body-biasing on sub-threshold adiabatic inverters show an improvement in differential power up to 43.28% for similar inverters without body biasing. Then, a High Performance Adiabatic Dynamic Differential Logic (PADDL) is presented for an implementation in high frequency secure ICs. This method improves the differential power over previous dynamic and differential logic methods by up to 89.65%. Finally, we propose a Body-Biased Adiabatic Dynamic Differential Logic (BADDL) for ultra-low power applications. Simulation results show that the differential power was improved upon by a factor of 199.16. Then, we present an adiabatic S-box which significantly reduces energy imbalance compared to previous benchmarks. The design is capable of forward encryption and reverse decryption with minimal overhead, allowing for efficient hardware reuse.

4

Ramclam, Kenneth M. "Low-Power and Robust Level-Shifter with Contention Mitigation for Memory and Standalone Applications." Scholar Commons, 2015. https://scholarcommons.usf.edu/etd/5555.

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The scaling down of transistor sizes has imposed significant challenges in today's technology. Memories such as eDRAM, are experiencing poor retention time because of challenges such as reference voltage variation, high transistor leakage, and low cell capacitance. It can be seen that we must consider not only the first order effects, but also the second order effects to ensure we keep up with current technology trends such as Moore's law. In this thesis we explore various circuit level techniques on level shifters in order to achieve better retention time. With our research, we have addressed important design challenges and propose techniques that can be utilized in current and emerging technologies. Level shifters (LS) are crucial components in low-power design where the die is segregated in multiple voltage domains. LS are used at the voltage domain interfaces to mitigate sneak path current. A less-known but very important application of LS is in high voltage drivers for designs where voltage boosting is needed for performance and functionality. We first study LS in eDRAM where LS is employed in the wordline path. Our investigation reveals that leakage power of LS can pose a serious threat by lowering the wordline voltage and subsequently affecting the speed and retention time of the eDRAM. It can also be noted that the delay of the LS under worse case process corners can cause significant functional discrepancies. We propose low-power pulsed-LS with supply gating to circumvent these issues. Our analysis indicate that pulsed-LS design can improve the worst case speed from 2.7%-43%. We extended this concept to design generic self-collapsible LSs that can be used for other applications such as voltage interfaces. The self-collapsed design in both applications improved the worst case speed from 6%-24% and 89% in some cases.

5

Lai, Farley. "Stream processing optimizations for mobile sensing applications." Diss., University of Iowa, 2017. https://ir.uiowa.edu/etd/5797.

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Mobile sensing applications (MSAs) are an emerging class of applications that process continuous sensor data streams to make time-sensitive inferences. Representative application domains range from environmental monitoring, context-aware services to recognition of physical activities and social interactions. Example applications involve city air quality assessment, indoor localization, pedometer and speaker identification. The common application workflow is to read data streams from the sensors (e.g, accelerometers, microphone, GPS), extract statistical features, and then present the inferred high-level events to the user. MSAs in the healthcare domain especially draw a significant amount of attention in recent years because sensor-based data collection and assessment offer finer-granularity, timeliness, and higher accuracy in greater quantity than traditional, labor-intensive, data gathering mechanisms in use today, e.g., surveys methods. The higher fidelity and accuracy of the collected data expose new research opportunities, improve the reliability and accuracy of medical decisions, and empower users to manage personal health more effectively. Nonetheless, a critical challenge to practical deployment of MSAs in real-world is to effectively manage limited resources of mobile platforms to meet stringent quality of service (QoS) requirements in terms of processing throughput and delay while ensuring long term robustness. To address the challenge, we model MSAs in dataflows as a graph of processing elements that are connected by communication channels. The processing elements may execute in parallel as long as they have sufficient data to process. A key feature of the dataflow model is that it explicitly capture parallelism and data dependencies between processing elements. Based on the graph composition, we first proposed CSense, a stream-processing toolkit for robust and high-rate MSAs. In this work, CSense provide a simple language for developers to describe their sensing flow without the need to deal with system intricacy, such as memory allocation, concurrency control and power management. The results show up to 19X performance difference may be achieved automatically compared with a baseline using the default runtime concurrency and memory management. Following this direction, we saw the opportunities that MSAs can be significantly improved from the perspective of memory performance and energy efficiency in view of the iterative execution. Therefore, we next focus on optimizing the runtime memory management through compile time analysis. The contribution is a stream compiler that captures the whole program memory behavior to generate an efficient memory layout for runtime access. Experiments show that our memory optimizations reduce memory footprint by as much as 96% while matching or improving the performance of the StreamIt compiler with cache optimizations enabled. On the other hand, while there is a significant body of work that has focused on optimizing the throughput or latency of processing sensor streams, little to no attention has been given to energy efficiency. We proposed an accurate offline energy prediction model for MSAs that leverages the pipeline structure and iterative execution nature to search for the most energy saving batching configuration w.r.t. a deadline constraint. The developers are expected to visualize the energy delay trade-off in the parameter space without runtime profiling. The evaluation shows the worst-case prediction errors are about 7% and 15% for energy and latency respectively despite variable application workloads.

6

Mandlekar, Anup Shrikant. "An Application Framework for a Power-Aware Processor Architecture." Thesis, Virginia Tech, 2012. http://hdl.handle.net/10919/34484.

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The instruction-set based general purpose processors are not energy-efficient for event-driven applications. The E-textiles group at Virginia Tech proposed a novel data-flow processor architecture design to bridge the gap between event-driven applications and the target architecture. The architecture, although promising in terms of performance and energy-efficiency, was explored for limited number of applications. This thesis presents a model-driven approach for the design of an application framework, facilitating rapid development of software applications to test the architecture performance. The application framework is integrated with the prior automation framework bringing software applications at the right level of abstraction. The processor architecture design is made flexible and scalable, making it suitable for a wide range of applications. Additionally, an embedded flash memory based architecture design for reduction in the static power consumption is proposed. This thesis estimates significant reduction in overall power consumption with the incorporation of flash memory.
Master of Science

7

Cortes, Christoffer, and Adam Krauser. "Android : Resource Consumption in Native and Web Applications." Thesis, Blekinge Tekniska Högskola, Sektionen för datavetenskap och kommunikation, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:bth-4681.

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There is an ongoing debate by people in the industry whether to make native or web applications. These discussions mostly surround issues about development costs, user experience and capabilities. Another aspect of this debate is the fact that mobile devices have varying hardware specifications which is another factor to consider when making this decision. What we want to shed some light on is how performance is affected on the device when using these two different approaches of application development. The use of CPU/RAM and Energy is our primary concern and in our experiment we measure these values on two similar applications where one uses Nested Layouts and the other a WebView. The experiment was made on three different devices with varying specifications. What we found was that Web applications have a bigger impact on overall performance and because of this use more battery. While the debate certainly won't come to a close with results they are conclusive when it comes to the topic of performance and will be of value to developers who are concerned about it.

8

Mugisha, Dieudonne Manzi. "Exploiting Application Behaviors for Resilient Static Random Access Memory Arrays in the Near-Threshold Computing Regime." DigitalCommons@USU, 2015. https://digitalcommons.usu.edu/etd/4550.

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Near-Threshold Computing embodies an intriguing choice for mobile processors due to the promise of superior energy efficiency, extending the battery life of these devices while reducing the peak power draw. However, process, voltage, and temperature variations cause a significantly high failure rate of Level One cache cells in the near-threshold regime a stark contrast to designs in the super-threshold regime, where fault sites are rare. This thesis work shows that faulty cells in the near-threshold regime are highly clustered in certain regions of the cache. In addition, popular mobile benchmarks are studied to investigate the impact of run-time workloads on timing faults manifestation. A technique to mitigate the run-time faults is proposed. This scheme maps frequently used data to healthy cache regions by exploiting the application cache behaviors. The results show up to 78% gain in performance over two other state-of-the-art techniques.

9

Mahato, Prabir. "Study and development of resistive memories for flexible electronic applications." Thesis, Lyon, 2020. http://www.theses.fr/2020LYSEI134.

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L’avènement de l’électronique flexible a entraîné des recherches rapides sur des capteurs, des dispositifs bio-implantables et portables pour l’évaluation de maladies telles que l’épilepsie, la maladie de Parkinson et les crises cardiaques. Les dispositifs de mémoire sont des composants majeurs dans tous les circuits électroniques, uniquement secondaires aux transistors, par conséquent de nombreux efforts de recherche sont consacrés au développement de dispositifs de mémoire flexibles. Les mémoires à accès aléatoire à pont conducteur (CBRAM) basées sur la création / dissolution d'un filament métallique dans un électrolyte solide sont d'un grand intérêt pour la recherche en raison de leur architecture métallique isolante métallique simple, de leurs capacités basse tension et de leur compatibilité avec les substrats flexibles. Dans ce travail, au lieu d'un oxyde métallique conventionnel ou d'une couche de chalcogénure, un polymère biocompatible - l'oxyde de polyéthylène (PEO) - est utilisé comme couche d'électrolyte solide en utilisant l'eau comme solvant. Des dispositifs de mémoire, constitués d'empilements tri-couches Ag / PEO / Pt, ont été fabriqués à la fois sur du silicium et des substrats flexibles en utilisant un processus hétérogène combinant un dépôt physique en phase vapeur et un revêtement par rotation. Pour cela, une étude systématique de l'effet de la concentration de la solution et de la vitesse de dépôt sur l'épaisseur du PEO est présentée. Des mesures SEM / EDX et AFM ont ensuite été effectuées sur des structures planes dédiées à «nano-gap» et ont révélé la formation de précipités métalliques d'Ag ainsi que des changements morphologiques de la couche de polymère après commutation de résistance. Les performances des dispositifs de mémoire résistive sont ensuite évaluées sur silicium et substrats flexibles. En particulier, la programmation des statistiques de tension, le rapport de résistance OFF / ON, les cycles d'endurance et les tests de rétention sont effectués et l'effet de la conformité du courant est analysé. Le mécanisme de conduction dans le HRS / LRS est étudié sur les appareils de référence Ag / PEO / Pt et Pt / PEO / Pt. Enfin, la caractérisation électrique des dispositifs sur substrat souple est réalisée sous contrainte mécanique, donnant des résultats prometteurs. Les dispositifs CBRAM à base de polymères sont donc proposés comme candidats potentiels pour le développement durable de dispositifs de mémoire flexibles
The advent of flexible electronics has brought about rapid research towards sensors, bio implantable and wearable devices for assessment of diseases such as epilepsy, Parkinson’s and heart attacks. Memory devices are major component in any electronic circuits, only secondary to transistors, therefore many research efforts are devoted to the development of flexible memory devices. Conductive Bridge Random Access Memories (CBRAMs) based on creation/dissolution of a metallic filament within a solid electrolyte are of great research interest because of their simple Metal Insulator Metal architecture, low-voltage capabilities, and compatibility with flexible substrates. In this work, instead of a conventional metallic oxide or a chalcogenide layer, a biocompatible polymer - Polyethylene Oxide (PEO) – is employed as the solid electrolyte layer using water as solvent. Memory devices, consisting in Ag/PEO/Pt tri-layer stacks, were fabricated on both silicon and flexible substrates using a heterogeneous process combining physical vapour deposition and spin coating. To aim this, a systematic study on the effect of solution concentration and deposition speed on the PEO thickness is presented. SEM/EDX and AFM measurements were then conducted on devoted “nano-gap” planar structures and have revealed the formation of metallic Ag precipitates together with morphological changes of the polymer layer after resistance switching. The performance of the resistive memory devices is then assessed on silicon and flexible substrates. In particular programming voltage statistics, OFF/ON resistance ratio, endurance cycles and retention tests are performed and the effect of current compliance is analysed. The conduction mechanism in the HRS/LRS is studied on the Ag/PEO/Pt and Pt/PEO/Pt reference devices. Finally, the electrical characterization of devices on flexible substrate is performed under mechanical stress, showing promising results. Polymer-based CBRAM devices are therefore suggested as potential candidates for sustainable development of flexible memory devices

10

Ly, Aliou. "Développement d’un oscillateur paramétrique optique continu intense et à faible bruit pour des applications aux communications quantiques." Thesis, Université Paris-Saclay (ComUE), 2017. http://www.theses.fr/2017SACLS528/document.

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La portée des communications quantiques est limitée à quelques dizaines de km en raison de l’atténuation dans les fibres. Les répéteurs quantiques (relais quantiques synchronisés par des mémoires quantiques photoniques) furent introduits afin d’accroître ces distances. Or, pour le moment, les mémoires les plus performantes fonctionnent à des longueurs d’onde n’appartenant pas à la bande C télécom. Afin de profiter de ces mémoires, l’utilisation d’interfaces quantiques (milieu non linéaire quadratique) fut proposée comme alternative. En ajoutant ainsi par somme de fréquences un photon de pompe de longueur d’onde appropriée au photon télécom portant l’information, on transfère l’information à une longueur d’onde compatible avec les mémoires, et ceci sans dégradation de l’information portée initialement par le photon télécom. Notre but est ainsi de construire un oscillateur paramétrique optique continu simplement résonant (SRO) qui fournira un faisceau à 1648 nm qui sera sommé en fréquence aux photons télécom à 1536 nm pour transférer l’information vers un photon stockable dans une mémoire à base d’atomes alcalins. Pour transférer efficacement l’information, le SRO doit satisfaire quelques critères : une haute finesse spectrale (largeur de raie ~kHz), une forte puissance (~1W) et une longueur d’onde plus grande que celle du photon télécom à convertir. Pour ce faire, nous utilisons le faisceau non-résonant d’un SRO continu. Le premier travail réalisé dans cette thèse a été de faire la démonstration de la possibilité d’avoir un faisceau à la fois intense et pur spectralement en sortie d’un SRO continu. En réutilisant un SRO déjà développé durant nos travaux antérieurs, nous avons pu stabiliser au niveau du kHz la fréquence du faisceau non résonant à 947 nm (onde signal) de ce SRO, tout en émettant une puissance de plus d’un watt. Ensuite, nous avons conçu le SRO dont le faisceau non résonant à 1648 nm (onde complémentaire) a été stabilisé à court terme en-dessous du kHz avec une puissance de l’ordre du watt. Nous avons ensuite étudié la stabilité à long terme de la longueur d’onde du complémentaire à 1648 nm. Nous avons mesuré des dérives de fréquences de l’ordre de 10 MHz/mn. Ces dérives, venant essentiellement de la cavité de référence sur laquelle le SRO est asservi, peuvent être réduites en contrôlant activement la cavité d’une part, et en utilisant des techniques de stabilisation en fréquence robustes, d’autre part
Long distance quantum communications are limited to few tens of km due to the attenuation of light in telecom fibres. Quantum repeaters (quantum relays synchronized by photonic quantum memories) were introduced in order to increase distances. Or, currently, the most efficient memories do not operate at wavelengths in the telecom C band. In order to take advantage of these memories, the use of quantum interfaces (second order nonlinear medium) was proposed as an alternative. Thus, by adding by sum frequency generation a pump photon at an appropriate wavelength to the telecom photon carrying the information, one transfers the information to a wavelength compatible with these memories, and this with a preservation of the information initially carried by the telecom photon. Our aim is thus to build a continuous-wave singly resonant optical parametric oscillator (cw SRO) which will provide a wave at 1648 nm that will be frequency summed to telecom photons at 1536 nm to transfer the information to a photon storable into alkali atoms based memory. To efficiently transfer the information, the cw SRO has to fulfill some requirements: a high spectral purity (linewidth ~kHz), a high output power (~1 W) and a wavelength longer than that of the telecom photon to be converted. To this aim, we use the non-resonant wave of a cw SRO. The first work done during this thesis was to experimentally prove the possibility to have both high output power and high spectral purity from a cw SRO. By reusing a cw SRO already built during our previous works, we were able to stabilize at the kHz level the frequency of the non-resonant wave at 947 nm (signal wave) of this SRO, with an output power of more than one watt. Then, we built the cw SRO of which non-resonant wave at 1648 nm (idler wave) has been frequency stabilized below the kHz level along with an output power of the order of one watt. We next studied the long term stability of the idler wavelength at 1648 nm. We have measured frequency drifts of the order of 10 MHz/mn. These drifts originating mainly from the reference cavity to which the SRO is locked, can be reduced by, firstly, an active control of the cavity and by, secondly, the use of robust frequency stabilization techniques

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Книги з теми "Memory and power applications":

1

Chernow, Fred B. Memory power plus! Paramas, N.J: Prentice Hall, 1997.

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2

Lapp, Danielle C. Maximizing your memory power. Hauppauge, N.Y: Barron's, 1992.

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3

Kellett, Michael Cliff. High-intensity memory power. New York: Sterling, 1986.

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4

Os, H. W. van. The power of memory. Baarn, the Netherlands: De Prom, 1999.

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5

Weiss, Donald H. Increasing your memory power. New York, NY: American Management Association, 1986.

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6

Lapp, Danielle C. Maximizing your memory power. 2nd ed. Hauppauge, NY: Barron's Educational Series, 1998.

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7

Semiconductor, National. Memory applications handbook. Santa Clara: National Semiconductor, 1993.

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8

Esposito, Anthony. Fluid power with applications. 6th ed. Upper Saddle River, N.J: Prentice Hall, 2003.

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9

Klemin, V. Wayne. PC power: Microcomputer applications. New York, N.Y: Glencoe/McGraw-Hill, 1991.

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10

Esposito, Anthony. Fluid power with applications. 4th ed. Upper Saddle River, N.J: Prentice Hall, 1997.

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Частини книг з теми "Memory and power applications":

1

Tarasov, Vasily E. "Economic models with power-law memory." In Applications in Engineering, Life and Social Sciences, Part B, edited by Dumitru Bǎleanu and António Mendes Lopes, 1–32. Berlin, Boston: De Gruyter, 2019. http://dx.doi.org/10.1515/9783110571929-001.

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2

Edelman, Mark. "Dynamics of nonlinear systems with power-law memory." In Applications in Physics, Part A, edited by Vasily E. Tarasov, 103–32. Berlin, Boston: De Gruyter, 2019. http://dx.doi.org/10.1515/9783110571707-005.

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3

Corcuera, José Manuel. "Power Variation Analysis of Some Integral Long-Memory Processes." In Stochastic Analysis and Applications, 219–34. Berlin, Heidelberg: Springer Berlin Heidelberg, 2007. http://dx.doi.org/10.1007/978-3-540-70847-6_9.

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4

Prodromakis, Themis. "Harnessing the Power of the Brain with Memory-resitors." In Circuits and Systems for Biomedical Applications, 49–69. New York: River Publishers, 2022. http://dx.doi.org/10.1201/9781003337546-3.

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5

Qiu, Yeliang, Congfeng Jiang, Tiantian Fan, Yumei Wang, Liangbin Zhang, Jian Wan, and Weisong Shi. "Power Characterization of Memory Intensive Applications: Analysis and Implications." In Benchmarking, Measuring, and Optimizing, 189–201. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-32813-9_16.

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6

Choi, Hong Jun, Dong Oh Son, and Cheol Hong Kim. "Memory Contention Aware Power Management for High Performance GPUs." In Parallel and Distributed Computing, Applications and Technologies, 220–29. Singapore: Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-13-5907-1_23.

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7

Cheng, Yao, Chang Xu, Daisuke Mashima, Vrizlynn L. L. Thing, and Yongdong Wu. "PowerLSTM: Power Demand Forecasting Using Long Short-Term Memory Neural Network." In Advanced Data Mining and Applications, 727–40. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-69179-4_51.

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8

Yoo, Hoi Jun, and Donghyun Kim. "Embedded Memory Architecture for Low-Power Application Processor." In Integrated Circuits and Systems, 7–38. Boston, MA: Springer US, 2009. http://dx.doi.org/10.1007/978-0-387-88497-4_2.

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9

Song, Yong-Ha, and Jun-Bo Yoon. "Micro and Nanoelectromechanical Contact Switches for Logic, Memory, and Power Applications." In Nano Devices and Circuit Techniques for Low-Energy Applications and Energy Harvesting, 65–117. Dordrecht: Springer Netherlands, 2015. http://dx.doi.org/10.1007/978-94-017-9990-4_3.

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10

El-Atab, Nazek, Ali K. Okyay, and Ammar Nayfeh. "Two-nanometer Laser Synthesized Si-Nanoparticles for Low Power Memory Applications." In 3D Stacked Chips, 129–56. Cham: Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-20481-9_7.

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Тези доповідей конференцій з теми "Memory and power applications":

1

Roizin, Yakov, Evgeny Pikhay, Vladislav Dayan, and Alexey Heiman. "High Density MTP Logic NVM for Power Management Applications." In 2009 IEEE International Memory Workshop (IMW). IEEE, 2009. http://dx.doi.org/10.1109/imw.2009.5090593.

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2

Zhu, Zongwei, Xi Li, Chao Wang, and Xuehai Zhou. "Memory power optimization on different memory address mapping schemas." In 2014 IEEE 20th International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA). IEEE, 2014. http://dx.doi.org/10.1109/rtcsa.2014.6910545.

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3

Kouznetsov, Igor, Krishnaswamy Ramkumar, Venkatraman Prabhakar, Long Hinh, H. M. Shih, S. Saha, S. Govindaswamy, et al. "40 nm Ultralow-Power Charge-Trap Embedded NVM Technology for IoT Applications." In 2018 IEEE International Memory Workshop (IMW). IEEE, 2018. http://dx.doi.org/10.1109/imw.2018.8388777.

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4

Yiyan Tang, Yingtao Jiang, and Yuke Wang. "Reduce FFT memory reference for low power applications." In IEEE International Conference on Acoustics Speech and Signal Processing ICASSP-02. IEEE, 2002. http://dx.doi.org/10.1109/icassp.2002.1005369.

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5

Tang, Yiyan, Yingtao Jiang, and Yuke Wang. "Reduce FFT memory reference for low power applications." In Proceedings of ICASSP '02. IEEE, 2002. http://dx.doi.org/10.1109/icassp.2002.5745331.

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6

Golanbari, Mohammad Saber, Saman Kiamehr, Rajendra Bishnoi, and Mehdi B. Tahoori. "Reliable memory PUF design for low-power applications." In 2018 19th International Symposium on Quality Electronic Design (ISQED). IEEE, 2018. http://dx.doi.org/10.1109/isqed.2018.8357289.

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7

Mansilla, Oscar, and Eric Thomson. "Power solution for DDR memory in space applications." In 2014 IEEE Aerospace Conference. IEEE, 2014. http://dx.doi.org/10.1109/aero.2014.6836177.

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8

Sharif, Kazi Fatima, Riazul Islam, Mahbubul Haque, Satyendra N. Biswas, Voicu Groza, and Mansour Assaf. "Low power nMOS based memory cell." In 2017 International Conference on Innovative Mechanisms for Industry Applications (ICIMIA). IEEE, 2017. http://dx.doi.org/10.1109/icimia.2017.7975598.

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9

Nii, Koji. "Ultra-Low Standby Power Embedded SRAM Design Techniques for Smart IoT Applications." In 2019 IEEE 11th International Memory Workshop (IMW). IEEE, 2019. http://dx.doi.org/10.1109/imw.2019.8739660.

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10

Wang, M., Y. L. Song, H. J. Wan, H. B. Lv, P. Zhou, T. A. Tang, Y. Y. Lin, et al. "A CuxO-based resistive memory with low power and high reliability for SOC nonvolatile memory applications." In 2010 IEEE International Memory Workshop. IEEE, 2010. http://dx.doi.org/10.1109/imw.2010.5488318.

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Звіти організацій з теми "Memory and power applications":

1

Musmanno, Joseph F., Joseph W. Manke, and Jon W. Harris. Processor-in-Memory Applications Assessment. Fort Belvoir, VA: Defense Technical Information Center, October 2000. http://dx.doi.org/10.21236/ada386682.

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2

Agarwal, Anant, and Anoop Gupta. Memory-Reference Characteristics of Multiprocessor Applications under MACH. Fort Belvoir, VA: Defense Technical Information Center, January 1988. http://dx.doi.org/10.21236/ada207318.

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3

Schindewolf, M., B. Bihari, J. Gyllenhaal, M. Schulz, A. Wang, and W. Karl. What Scientific Applications can Benefit from Hardware Transactional Memory? Office of Scientific and Technical Information (OSTI), June 2012. http://dx.doi.org/10.2172/1044233.

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4

Bochat, W. M. Atomic Bomb: Memory and its Power on Japanese Pacifism. Fort Belvoir, VA: Defense Technical Information Center, May 2008. http://dx.doi.org/10.21236/ada526120.

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5

Levy, Scott N., Patrick G. Bridges, Kurt Brian Ferreira, Aidan Patrick Thompson, and Christian Robert Trott. An examination of content similarity within the memory of HPC applications. Office of Scientific and Technical Information (OSTI), January 2013. http://dx.doi.org/10.2172/1088105.

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6

Merritt, Alexander M., and Kevin Thomas Tauke Pedretti. LDRD final report : managing shared memory data distribution in hybrid HPC applications. Office of Scientific and Technical Information (OSTI), September 2010. http://dx.doi.org/10.2172/1007320.

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7

Biryukov, A., D. Dinu, D. Khovratovich, and S. Josefsson. Argon2 Memory-Hard Function for Password Hashing and Proof-of-Work Applications. RFC Editor, September 2021. http://dx.doi.org/10.17487/rfc9106.

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8

Lindemuth, I. R., R. E. Reinovsky, and C. M. Fowler. Megagauss technology and pulsed power applications. Office of Scientific and Technical Information (OSTI), September 1996. http://dx.doi.org/10.2172/378770.

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9

Muljadi, E., Y. C. Zhang, A. Allen, M. Singh, V. Gevorgian, and Y. H. Wan. Synchrophasor Applications for Wind Power Generation. Office of Scientific and Technical Information (OSTI), February 2014. http://dx.doi.org/10.2172/1126317.

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10

Zhang, Y. Aluminide Coatings for Power-Generation Applications. Office of Scientific and Technical Information (OSTI), November 2003. http://dx.doi.org/10.2172/885900.

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