Готові списки джерел за темами / Low power high-speed links

Добірка наукової літератури з теми "Low power high-speed links"

Автор: Grafiati
Опубліковано: 6 вересня 2023

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Статті в журналах з теми "Low power high-speed links"

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Statkus, Arūnas, Šarūnas Paulikas, and Audrius Krukonis. "TCP Acknowledgment Optimization in Low Power and Embedded Devices." Electronics 10, no. 6 (March 10, 2021): 639. http://dx.doi.org/10.3390/electronics10060639.

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Paper investigates transport control protocol (TCP) acknowledgment (ACK) optimization in low power or embedded devices to improve their performance on high-speed links by limiting the ACK rate. Today the dominant protocol for interconnecting network devices is the TCP and it has a great influence on the entire network operation if the processing power of network devices is exhausted to the processing data from the TCP stack. Therefore, on high-speed not congested networks the bottleneck is no longer the network link but low-processing power network devices. A new ACK optimization algorithm has been developed and implemented in the Linux kernel. Proposed TCP stack modification minimizes the unneeded technical expenditure from TCP flow by reducing the number of ACKs. The results of performed experiments show that TCP ACK rate limiting leads to the noticeable decrease of CPU utilization on low power devices and an increase of TCP session throughput but does not impact other TCP QoS parameters, such as session stability, flow control, connection management, congestion control or compromises link security. Therefore, more resources of the low-power network devices could be allocated for high-speed data transfer.
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2

Khitrov, Andrei, and Alexander Khitrov. "Electrical subsystem of the low-power cogeneration plant with low-speed vehicle." Environment. Technology. Resources. Proceedings of the International Scientific and Practical Conference 2 (August 8, 2015): 119. http://dx.doi.org/10.17770/etr2013vol2.852.

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Nowadays diesel power plants form the basis of distributed power generation in Russia, but they have disadvantages. The alternative variant is cogeneration plant based on the rotary-vane machine. One of the types of such machines is the rotary-vane external combustion vehicle (engine) developed in Pskov State University. Electrical subsystem of the plant requires its effective work to provide both start and generation modes. Development of such subsystem structure, employment of elements for links with other subsystems in the hierarchic control system is an actual task. The paper considers structures of the electrical part of the plant, simulation and experiment results.
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Ali, Luqman Sufer, and Asmaa Salim Mayoof. "Design of Current Mode MTCMOS Sense Amplifier with Low Power and High Speed." Tikrit Journal of Engineering Sciences 23, no. 2 (May 31, 2016): 96–102. http://dx.doi.org/10.25130/tjes.23.2.11.

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This paper involved the design and analysis of multi-threshold voltage CMOS (MTCMOS) current sense amplifier focusing on optimizing power and time delay. In this work the basic 6T SRAM structure was chosen and the simulation is implemented using ADS programs. The key to low power operation in the SRAM data path is to reduce the signal swings on the bit lines and the data lines. The power dissipation and delay of the sense amplifier circuit can be further reduced by using several low power and high speed techniques like MTCMOS. This technique can be used for solving the leakage power dissipation problem in the higher technology design. Simulated results show the current mode sense amplifier with MTCMOS technology has 0.82ns time delay and 0.395μW power dissipation. The designs and simulations in 0.25μm CMOS technology with supply voltage equal to 1.8 V have been carried out to evaluate the efficiency of the current mode sense amplifier with MTCMOS technique proposed.
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4

Lyashenko, Yu, and A. Prudiy. "RESEARCH INTO THE IMPACT OF ROAD POWER ENERGY SYSTEM MECHANICAL CONVERTER LINKS MOTION ON GENERATOR OPERATION." Bulletin of the South Ural State University series "Power Engineering" 21, no. 3 (2021): 41–48. http://dx.doi.org/10.14529/power210305.

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Currently, alternative energy sources are used to economize. They provide autonomous power supply for the electrical receivers. One of the solutions in the field of alternative generation for lighting and power supply to low-power electrical receivers is to use road power energy systems. It is integrated as speed breakers and has an electromechanical generator converting a car speed energy into electrical energy. The paper considers the developed road power energy system with a rocker rod gear used to convert the forward movement to rota-tional movement. The study concentrates on the influence the acting force converter mechanism links movement have on the operation of road power energy system generator. The paper analyzes the operation of mechanisms with various crank arm lengths with preset speed and size parameters. The influence of the crank arm length on the motion path and speed of rocker arm was determined. The analysis showed that the100 and 150 mm crank arm lengths provide for the site with proportional speed rate of motion rocker arm. The100 mm crank arm was selected for future research. It allows building a system with a minimal size possible.
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Traversi, G., S. Bonacini, F. De Canio, L. Gaioni, K. Kloukinas, M. Manghisoni, L. Ratti, and V. Re. "Design of low-power, low-voltage, differential I/O links for High Energy Physics applications." Journal of Instrumentation 10, no. 01 (January 29, 2015): C01055. http://dx.doi.org/10.1088/1748-0221/10/01/c01055.

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Ayachi, Riadh, Ayoub Mhaouch, and Abdessalem Ben Abdelali. "Lightweight Cryptography for Network-on-Chip Data Encryption." Security and Communication Networks 2021 (May 19, 2021): 1–10. http://dx.doi.org/10.1155/2021/9943713.

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System-on-chip (SoC) is the main processor for most recent applications such as the Internet of things (IoT). SoCs are composed of multiple blocks that communicate with each other through an integrated router. Data routing from a block to another poses many challenges. The network-on-chip (NoC) was used for the transmission of data from a source to a destination with high reliability, high speed, low power consumption, and low hardware occupation. An NoC is composed of a router, network links (NL), and network interface (NI). The main component of the NoC, the NI, is composed of an input/output FIFO, a finite state machine (FSM), pack, and depack modules. Data transmission from a block to another poses a security problem such as secret information extraction. In this paper, we proposed a data encryption framework for NoC based on a light encryption device (LED) algorithm. The main advantages of the proposed algorithm are to reduce the implementation area and to achieve high speed while reducing the power consumption. The proposed encryption framework was simulated Verilog/VHDL on the Xilinx ISE and implemented on the Xilinx Virtex 5 XC5VFX200T. The obtained results have shown that the proposed framework has a smaller area and higher speed compared to existing works. The proposed algorithm has reduced the NI implementation area and enhanced the network performance in terms of speed and security.
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Qu, Zhi Jian, and Li Liu. "Real-Time Database System Implementation of Railway Signal Power Source Remote Monitoring." Applied Mechanics and Materials 128-129 (October 2011): 961–64. http://dx.doi.org/10.4028/www.scientific.net/amm.128-129.961.

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Railway signal is a key technology for high-speed railway，which is the foundation to keep the high-speed train line. Railway signal power is the automatic blocking of railway lines and 10kV lines transform into 380V power through after the power supply for railway signals. Signal power as the railway traffic signal of the power supply, it belongs to the first level of power system load. Its 10kV high voltage side stik up by the major of electric, 380V low voltage side maintenance by the signal major. When the signal power failure, often occur shirk responsibilities between the different majors, in order to define the responsibilities of the accident better, which need automation remote monitoring for main railway lines of the railway signal power and scheduling control as soon as possible[1-3].
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Chrisey, Douglas B., and Arun Inam. "Pulsed Laser Deposition of High Tc Superconducting Thin Films for Electronic Device Applications." MRS Bulletin 17, no. 2 (February 1992): 37–43. http://dx.doi.org/10.1557/s0883769400040604.

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The discovery of high transition temperature, Tc, superconductivity in copperoxide-based ceramics by Bednörz and Miiller, and the subsequent increase in Tc above the boiling point of liquid nitrogen (77 K), renewed interest in employing superconducting thin films in high-speed, low-power electronic device applications (e.g., compact high-quality factor filters, delay lines, and Josephson elements for high-speed, low-power switching). However, realization of these benefits requires well-controlled, reliable superconducting thin film technology which addresses not only the growth of superconducting thin films, but also the development of a multilayer device technology encompassing materials with metallic, semiconducting, and insulating properties.
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Ulusoy, Ahmet Çağrı, Gang Liu, Andreas Trasser, and Hermann Schumacher. "Hardware efficient receiver for low-cost ultra-high rate 60 GHz wireless communications." International Journal of Microwave and Wireless Technologies 3, no. 2 (March 3, 2011): 121–29. http://dx.doi.org/10.1017/s1759078711000110.

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This paper presents a hardware efficient receiver architecture, to be used in low-cost, ultra-high rate 60 GHz wireless communication systems. The receiver utilizes a simple, feed-forward carrier recovery concept, performing phase and frequency synchronization in the analog domain. This enables 1-bit baseband processing without a need of ultra-high speed and high precision analog-to-digital conversion, offering a strong simplification of the system architecture and comparatively low power consumption. In a first prototype implementation, the receiver is realized in a low-cost SiGe technology as two separate ICs: the 60 GHz/5 GHz downconverter, and the intermediate frequency synchronous demodulator. The simple synchronous reception concept is experimentally validated for up to 3.5 Gbit/s data rate, which constituted the limit of the existing experimental setup. Furthermore, the downconverter demonstrates that low-cost technologies (fop/fmax ~ 0.75) can be used to realize short-range data links at 60 GHz, with low-noise amplifiers in a more performant technology as needed.
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Ophir, Noam, Christopher Mineo, David Mountain, and Keren Bergman. "Silicon Photonic Microring Links for High-Bandwidth-Density, Low-Power Chip I/O." IEEE Micro 33, no. 1 (January 2013): 54–67. http://dx.doi.org/10.1109/mm.2013.1.

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Дисертації з теми "Low power high-speed links"

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Fang, Yuan [Verfasser], Klaus [Akademischer Betreuer] Hofmann, Franko [Akademischer Betreuer] Küppers, Marius [Akademischer Betreuer] Pesavento, Christian [Akademischer Betreuer] Hochberger, and Gersem Herbert [Akademischer Betreuer] De. "PHY Link Design and Optimization For High-Speed Low-Power Communication Systems / Yuan Fang. Betreuer: Klaus Hofmann ; Franko Küppers ; Marius Pesavento ; Christian Hochberger ; Herbert De Gersem." Darmstadt : Universitäts- und Landesbibliothek Darmstadt, 2015. http://d-nb.info/1111112444/34.

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Saadallah, Nisrine. "High-speed low-power asynchronous circuits." Thesis, McGill University, 2004. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=80140.

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This thesis presents several design experiments for high-performance power-efficient asynchronous circuits.
In Chapter two we present a new asynchronous pipeline logic family with improved latency and throughput compared to several other asynchronous pipeline circuits. The channels between pipeline stages use data encoding and a small set of minimum-delay timing constraints that permit modular design with few dependencies on technology and layout. We develop circuit blocks that implement linear pipelines as well as forking, joining and data-dependent decisions. An implementation in 0.18mum CMOS exhibits a latency of 56ps per pipeline stage and throughput of 4.8-giga data item per second (GDI/s) in Hspice simulation.
We also present the design of a low-control-overhead asynchronous microprocessor integrated with a high-speed sampling FIFO. This is an experiment in exploring the benefits of asynchronous design in high-speed embedded DSP applications. It reports on the design approach, implementation and performance, including a comparison with the synchronous version of the microprocessor.
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Ibrahim, Sameh Ahmed Assem Mostafa. "High-speed low-power equalizers for high-loss channels." Diss., Restricted to subscribing institutions, 2009. http://proquest.umi.com/pqdweb?did=2026920921&sid=1&Fmt=2&clientId=1564&RQT=309&VName=PQD.

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Jiang, Hao. "High-power, high-speed p-i-n- photodiodes for analog fiber optic links /." Diss., Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2000. http://wwwlib.umi.com/cr/ucsd/fullcit?p9970665.

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Nho, Hyunwoo. "A high-speed, low-power 3D-SRAM architecture /." May be available electronically:, 2008. http://proquest.umi.com/login?COPT=REJTPTU1MTUmSU5UPTAmVkVSPTI=&clientId=12498.

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Zheng, Shijie M. Eng Massachusetts Institute of Technology. "A low cost asynchronous eye diagram reconstruction system for high speed links." Thesis, Massachusetts Institute of Technology, 2013. http://hdl.handle.net/1721.1/85233.

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Анотація:
Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2013.
This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Cataloged from student-submitted PDF version of thesis.
Includes bibliographical references (pages 97-98).
As link communication data rate increases, there is an increasing need for a more cost eective way to test and monitor signal integrity in link communication systems. Specifically, eye diagrams are valuable visual aids to analyze and quantify digital signal quality. This thesis presents a novel low cost eye diagram reconstruction system using asynchronous undersampling technique, which solves a key problem in performance monitoring in systems where synchronous sampling is not available, such as video switches. Existing works are studied and compared to this work in performance and cost. The proposed system is designed as a system-on-chip (SOC) and contains an undersampling ADC, aliased frequency estimator and a simple reconstruction algorithm. Major building blocks are implemented and simulated in 65nm CMOS process. Extensive system level analysis and simulations demonstrate functionality and performance of the system working at 10Gb/s maximum data rate.
by Shijie Zheng.
M. Eng.
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Wolfe, Kurt A. "Radiation tolerant, high speed, low power gallium arsenide logic." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 1993. http://handle.dtic.mil/100.2/ADA277293.

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Zargaran, Yazd Arash. "Design techniques for high-speed low-power wireline receivers." Thesis, University of British Columbia, 2013. http://hdl.handle.net/2429/44660.

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High-speed data transmission through wireline links, either copper or optical based, has become the backbone for modern communication infrastructure. Since at multi-Gb/s data rates the transmitted signal is attenuated and distorted by the channel, sophisticated analog front-end and/or digital signal processing are required at the receiver (RX) to recover data and clock from the received signal. In this thesis, both analog- and digital-based receivers are investigated, and power-reduction techniques are exploited at both system- and circuit levels. A speculative successive-approximation register (speculative/SAR) digitization algorithm is proposed for use at the receiver front-end of digital receivers that combines equalization and data recovery with the digitization step at the front-end analog-to-digital converter (ADC). Furthermore, architecture for quadrature clock generation is proposed which is of use in both analog and digital receivers. Then, an analog clock and data recovery (CDR) architecture suitable for high data rates (e.g., beyond 10 Gb/s) is proposed that utilizes a wideband data phase generation technique to facilitate mixer-based phase detection. The CDR architecture is implemented and experimentally validated for a 12.5 Gb/s system. Finally, a mixed-mode hardware-efficient CDR architecture is proposed that exploits both analog and digital design techniques to reach a robust operation suited for long-haul optical link communications. Proof-of-concept prototypes of the proposed RX architectures are designed and implemented in 65 nm and 90 nm CMOS processes. The prototypes are successfully tested. Note that although individual performance merits of the each prototype may not necessarily outperform that of the state-of-the-art, however, the prototypes confirm the feasibility of the proposed structure. Furthermore, the proposed architectures can be used at higher data rates particularly if more advanced technologies with higher device transit frequency, (fT), is used.
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Safi-Harab, Mouna. "Low-power low-voltage high-speed delta-sigma analog-to-digital converters." Thesis, McGill University, 2003. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=79258.

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The increasingly stringent requirements of today's communication systems and portable devices are imposing two challenges on the design of Analog-to-Digital Converters (ADC) and delta-sigma modulators (DeltaSigmaM) architecture in particular.
The first is the extension of the input frequency range to include applications where the input bandwidth exceeds the 1 MHz range.
This challenge in extending the operational speed of DeltaSigmaM is further rendered more complicated by the ever shrinking transistor dimension. As predicted by the Semiconductor Industry Association (SIA) Roadmap for CMOS technology, the transistor dimension will reach 0.05 mum in 2011. With this dramatic shrink in the transistor length, and as a result in the supply voltage, device modelling becomes ambiguous and circuit non-idealities more pronounced. The design of the main analog building blocks that minimize the time-to-market is therefore becoming very complicated.
These two issues will be addressed in this thesis, namely a new design method that will minimize the design cycle of delta-sigma analog-to-digital converters (DeltaSigma ADCs) intended for high-speed applications. This method will be demonstrated efficient in the implementation of two state-of-the-art modulators in terms of performance using a widely adopted figure of merit.
The validity of the top-down design methodology was verified through the fabrication of two prototype integrated circuits (ICs), both in TSMC 0.18 mum CMOS technology. In the first chip, a single-bit, fourth-order DeltaSigma ADC was implemented achieving more than 12-bit resolution. The second chip further validated the methodology to include higher resolution, in the range of 13 bits, multi-bit DeltaSigma ADCs. The experimental results from both prototype ICs closely mimic the system-level behavior of the designed modulator.
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Avadhanam, Karthik. "A new high speed low power Dynamic Programmable Logic Array /." Available to subscribers only, 2007. http://proquest.umi.com/pqdweb?did=1453188921&sid=5&Fmt=2&clientId=1509&RQT=309&VName=PQD.

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Книги з теми "Low power high-speed links"

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Cao, Zhiheng, and Shouli Yan. Low-Power High-Speed ADCs for Nanometer CMOS Integration. Dordrecht: Springer Netherlands, 2008. http://dx.doi.org/10.1007/978-1-4020-8450-8.

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Cao, Zhiheng. Low-Power High-Speed ADCs for Nanometer CMOS Integration. Dordrecht: Springer Science + Business Media B.V, 2008.

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3

Li, Weitao, Fule Li, and Zhihua Wang. High-Resolution and High-Speed Integrated CMOS AD Converters for Low-Power Applications. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-62012-1.

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Margarit, Josep Maria. Low-Power CMOS Digital Pixel Imagers for High-Speed Uncooled PbSe IR Applications. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-49962-8.

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Armin, Kemna, and Hosticka Bedrich J, eds. Modular low-power, high-speed CMOS analog-to-digital converter of embedded systems. Boston: Kluwer Academic Publishers, 2003.

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6

Shehata, Khaled Ali. Low-power high-speed dynamic logic families for complementary gallium arsenide (CGaAs) fabrication processes. Monterey, Calif: Naval Postgraduate School, 1996.

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7

Roermund, Arthur H. M. van., Casier Herman, and Steyaert Michiel 1959-, eds. Analog circuit design: High-speed A-D converters, automotive electronics, and ultra-low power wireless. Dordrecht, Netherlands: Springer, 2006.

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8

United States. Congress. Senate. Committee on Commerce, Science, and Transportation. Subcommittee on Communications. S. 2454, wireless high speed internet access for rural areas: Hearing before the Subcommittee on Communications of the Committee on Commerce, Science, and Technology, United States Senate, One Hundred Sixth Congress, second session, June 14, 2000. Washington: U.S. G.P.O., 2003.

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9

Raabe, Oliver. Der öffentlich-rechtliche Primärrechtschutz gegen Höchstspannungsfreileitungen am Beispiel der Rechtslage in Schleswig-Holstein, Baden-Württemberg und Bayern. Kiel: [s.n.], 2000.

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10

Virginia. Dept. of Transportation. Report of the Virginia Department of Transportation on a study of the Overhead High Voltage Line Safety Act to the Governor and the General Assembly of Virginia. Richmond: Commonwealth of Virginia, 1995.

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Частини книг з теми "Low power high-speed links"

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Fujishima, Minoru. "Ultimate High-Speed Wireless Link." In Low Power Circuit Design Using Advanced CMOS Technology, 363–444. New York: River Publishers, 2022. http://dx.doi.org/10.1201/9781003338772-5.

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Knudsen, Magne. "Changing Tides: Temporal Dimensions of Low-Cost, High-Skill Fisheries in the Central Visayas, Philippines." In Case Studies in Biocultural Diversity from Southeast Asia, 21–42. Singapore: Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-16-6719-0_2.

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AbstractAt the southern mouth of the Tañon Strait—the body of water that separates the islands of Cebu and Negros in the Visayas region of the Philippines—small-scale fishing has always been challenging. Strong and complex sea currents make it difficult for fishers to utilise certain fishing gears. With a significant decline in the resource base and new regulations of the fisheries in recent decades, only fishers with advanced skills and fine-grained place-specific and calendric knowledge of the marine environment are able to catch enough fish, and the right kind of fish, to secure a decent return. Drawing on insights from cultural ecology, the chapter examines the skills and knowledges that fishers draw on to catch fish in this challenging environment. It gives particular attention to the temporal dimensions of the biocultural knowledge complex, showing how fishers’ knowledge of the links between sea currents, the lunar cycle and monsoon winds play into their decisions about where, when and how to fish. In addition to its direct livelihood significance, calendric knowledge also serves as a resource in the formation of identity as mananagat (fisherman) and authority and status within the fishing community. To further explain why some fishers are able to use their knowledge to make fishing a viable and legitimate livelihood and others are not, the last part of the chapter uses insights from political ecology to address issues of power and dynamics of exclusion in the fisheries.
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Hatai, Indranil, and Indrajit Chakrabarti. "A High-Speed Low-Power Low-Latency Pipelined ROM-Less DDFS." In Communications in Computer and Information Science, 108–19. Berlin, Heidelberg: Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-17881-8_11.

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Beerel, Peter A. "Asynchronous Design for High-Speed and Low-Power Circuits." In Lecture Notes in Computer Science, 669. Berlin, Heidelberg: Springer Berlin Heidelberg, 2006. http://dx.doi.org/10.1007/11847083_66.

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Tigelaar, Howard. "Engineering MOS Transistors for High Speed and Low Power." In How Transistor Area Shrank by 1 Million Fold, 51–66. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-40021-7_4.

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Kabra, Naveen Kumar, and Zuber M. Patel. "Low-Power and High-Speed Configurable Arithmetic and Logic Unit." In Lecture Notes in Networks and Systems, 355–63. Singapore: Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-13-3765-9_37.

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Oudjida, Abdelkrim K., Nicolas Chaillet, Ahmed Liacha, Mustapha Hamerlain, and Mohamed L. Berrandjia. "High-Speed and Low-Power PID Structures for Embedded Applications." In Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 257–66. Berlin, Heidelberg: Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-24154-3_26.

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Dimitrakopoulos, G., P. Kolovos, P. Kalogerakis, and D. Nikolos. "Design of High-Speed Low-Power Parallel-Prefix VLSI Adders." In Lecture Notes in Computer Science, 248–57. Berlin, Heidelberg: Springer Berlin Heidelberg, 2004. http://dx.doi.org/10.1007/978-3-540-30205-6_27.

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Kumar, K. J., and A. Raganna. "Implementation of Low-Power High-Speed Clock and Data Recovery." In Cognitive Informatics and Soft Computing, 333–46. Singapore: Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-16-1056-1_27.

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Gao, Yuan, Jin Yong Xu, Yan Ping Liu, Zhi Yong He, and Zhong Xu. "A New Low Alloy High Speed Power Hack Saw Blades." In Materials Science Forum, 3939–42. Stafa: Trans Tech Publications Ltd., 2005. http://dx.doi.org/10.4028/0-87849-960-1.3939.

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Тези доповідей конференцій з теми "Low power high-speed links"

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Thomson, David J., Kapil Debnath, Weiwei Zhang, Ke Li, Shenghao Liu, Fanfan Meng, Ali Z. Khokhar, et al. "Towards High Speed and Low Power Silicon Photonic Data Links." In 2018 20th International Conference on Transparent Optical Networks (ICTON). IEEE, 2018. http://dx.doi.org/10.1109/icton.2018.8473598.

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Zhang, Hao, Hiroki Matsutani, Michihiro Koibuchi, and Hideharu Amano. "Dynamic power on/off method for 3D NoCs with wireless inductive-coupling links." In IEEE Symposium on Low-Power and High-Speed Chips. 2013 COOL Chips XVI. IEEE, 2013. http://dx.doi.org/10.1109/coolchips.2013.6547924.

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Melikyan, Vazgen, Arthur Sahakyan, Arsen Hekimyan, Davit Trdatyan, Aram Shishmanyan, and Tigran Khazhakyan. "Low power duty cycle adjustment simple method in high speed serial links." In 2015 IEEE East-West Design & Test Symposium (EWDTS). IEEE, 2015. http://dx.doi.org/10.1109/ewdts.2015.7493157.

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Changqing Xu, Yi Liu, and Yintang Yang. "High-speed, low-power transmitter based on charge redistribution for NoC links." In 2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT). IEEE, 2016. http://dx.doi.org/10.1109/icsict.2016.7998881.

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Duquennoy, Simon, Fredrik Österlind, and Adam Dunkels. "Lossy links, low power, high throughput." In the 9th ACM Conference. New York, New York, USA: ACM Press, 2011. http://dx.doi.org/10.1145/2070942.2070945.

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Shekhar, S., J. E. Jaussi, F. O'Mahony, M. Mansuri, and B. Casper. "Design considerations for low-power receiver front-end in high-speed data links." In 2013 IEEE Custom Integrated Circuits Conference - CICC 2013. IEEE, 2013. http://dx.doi.org/10.1109/cicc.2013.6658406.

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Zamarreno-Ramos, Carlos, Teresa Serrano-Gotarredona, Bernabe Linares-Barranco, Raghavendra Kulkarni, and Jose Silva-Martinez. "Voltage mode driver for low power transmission of high speed serial AER Links." In 2011 IEEE International Symposium on Circuits and Systems. IEEE, 2011. http://dx.doi.org/10.1109/iscas.2011.5938095.

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Ayesh, Mostafa M., Sameh A. Ibrahim, Hani F. Ragai, and Mohamed M. Rizk. "A low-power high-speed charge-steering ADC-based equalizer for serial links." In 2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS). IEEE, 2015. http://dx.doi.org/10.1109/icecs.2015.7440360.

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Nagula, Suresh, Patri Sreehari Rao, and Ekta Goel. "Adaptively Biased Low dropout regulator with High Power Supply Rejection for High speed serial Links." In 2022 IEEE International Symposium on Smart Electronic Systems (iSES). IEEE, 2022. http://dx.doi.org/10.1109/ises54909.2022.00070.

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Hou, Zhongyuan, Fan Yang, Junhua Liu, Huailin Liao, and Xing Zhang. "A low power and wide frequency range CMOS signal detector for high speed data links." In 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology (ICSICT). IEEE, 2012. http://dx.doi.org/10.1109/icsict.2012.6466700.

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Звіти організацій з теми "Low power high-speed links"

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Lawrence, William R. Nanomechanical Devices for High Speed and Low-Power Electronics. Fort Belvoir, VA: Defense Technical Information Center, June 2001. http://dx.doi.org/10.21236/ada394851.

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Parhi, Keshab K. High-Speed and Low-Power VLSI Error Control Coders. Fort Belvoir, VA: Defense Technical Information Center, September 2004. http://dx.doi.org/10.21236/ada426960.

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Waks, Edo, Sangbok Lee, Nader Engheta, and Benjamin Shapiro. Metatronics for Ultra-High-Speed Low-Power Nano-Circuits. Fort Belvoir, VA: Defense Technical Information Center, December 2011. http://dx.doi.org/10.21236/ada585948.

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Wang, Wen I. InAs HVT for Extremely Low Power and High Speed Applications. Fort Belvoir, VA: Defense Technical Information Center, July 2005. http://dx.doi.org/10.21236/ada438567.

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Dagenais, M. High Speed, Low Power Non-Linear Optical Signal Processing in Semiconductors. Fort Belvoir, VA: Defense Technical Information Center, June 1985. http://dx.doi.org/10.21236/ada159054.

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Crosbie, R. E., J. J. Zenor, R. Bednar, D. Word, and N. G. Hingorani. Low-Cost High-Speed Techniques for Real-Time Simulation of Power Electronic Systems. Fort Belvoir, VA: Defense Technical Information Center, June 2007. http://dx.doi.org/10.21236/ada485330.

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Brice, Jeremy. Investment, power and protein in sub-Saharan Africa. Edited by Tara Garnett. TABLE, October 2022. http://dx.doi.org/10.56661/d8817170.

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Анотація:
The place of protein in sub-Saharan Africa’s food system is changing rapidly, raising complex international development, global health and environmental sustainability issues. Despite substantial growth in the region’s livestock agriculture sector, protein consumption per capita remains low, and high levels of undernourishment persist. Meanwhile sub-Saharan Africa’s population is growing and urbanising rapidly, creating expectations that demand for protein will increase rapidly over the coming decades and triggering calls for further investment in the expansion and intensification of the region’s meat and dairy sector. However, growing disquiet over the environmental impacts of further expansion in livestock numbers, and growing sales of alternative protein products in the Global North, has raised questions about the future place of plant-based, insect and lab-grown proteins in African diets and food systems. This report examines financial investment in protein production in sub-Saharan Africa. It begins from the position that investors play an important role in shaping the development of diets and food systems because they are able to mobilise the financial resources required to develop new protein products, infrastructures and value chains, or to prevent their development by withholding investment. It therefore investigates which actors are financing the production in sub-Saharan Africa of: a) animal proteins such as meat, fish, eggs and dairy products; b) ‘protein crops’ such as beans, pulses and legumes; and c) processed ‘alternative proteins’ derived from plants, insects, microbes or animal cells grown in a tissue culture. Through analysing investment by state, philanthropic and private sector organisations – as well as multilateral financial institutions such as development banks – it aims to establish which protein sources and stages of the value chain are financed by different groups of investors and to explore the values and goals which shape their investment decisions. To this end, the report examines four questions: 1. Who is currently investing in protein production in sub-Saharan Africa? 2. What goals do these investors aim to achieve (or what sort of future do they seek to bring about) through making these investments? 3. Which protein sources and protein production systems do they finance? 4. What theory of change links their investment strategy to these goals? In addressing these questions, this report explores what sorts of protein production and provisioning systems different investor groups might be helping to bring into being in sub-Saharan Africa. It also considers what alternative possibilities might be marginalised due to a lack of investment. It thus seeks to understand whose priorities, preferences and visions for the future of food might be informing the changing place of protein in the region’s diets, economies and food systems.
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Analysis of Recompression-Regeneration sCO 2 Combined Cycle Utilizing Marine Gas Turbine Exhaust Heat: Effect of Operating Parameters. SAE International, July 2022. http://dx.doi.org/10.4271/2022-01-5059.

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Gas turbines are fast being explored to replace the existing steam or diesel-based power packs to propel marine transportation. Marine gas turbines have already come to power high-speed marine vessels transporting perishable goods as well as high-speed naval fleets. This article investigates the potential of gas turbine to be made hybrid with supercritical recompression-regeneration carbon dioxide (CO2) cycle drawing thermal energy from the exhaust of marine gas turbines. The recompression unit acts as the topping cycle and the regeneration unit acts as the bottoming cycle of the proposed combined supercritical CO2 (sCO2) cycle. The cycle has a maximum temperature of 530°C and supercritical pressure of 20 MPa. The proposed sCO2 powerplant is compact because of the smaller size of the turbomachinery, owing to the low specific volume of working fluid in the supercritical range. The proposed combined cycle is analyzed for different operating conditions including maximum temperature, minimum temperature, and cycle pressure ratio. The thermal efficiency of the proposed sCO2 cycle is 30.77% and efficiency of the hybrid cycle (including marine GT) is 58.17%, i.e., enhancement in thermal efficiency of the marine vessel power pack by 18.6%. Further the power output of the gas turbine-sCO2 hybrid cycle is enhanced by nearly 23.5% to 45.7 megawatts (MW). The second law of thermodynamic efficiency of the proposed combined cycle is close to 52.5%. The proposed hybrid gas turbine-sCO2 cycle has immense potential to replace the aging propulsion systems of existing marine vessels as the proposed power cycle is greener and more compact.
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L52074 Investigation of Mixing and Scavenging in Large Bore (Natural Gas) Engines using Laser Diagnostics. Chantilly, Virginia: Pipeline Research Council International, Inc. (PRCI), January 2003. http://dx.doi.org/10.55274/r0011345.

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Poor in-cylinder mixing processes due to ineffective fuel delivery are problematic in large-bore, slow-speed, natural gas two-stroke cycle engines. High levels of combustion variability and documented engine performance improvements due to mixing enhancements, such as high-pressure fuel injection, support this assertion. The natural gas industry operates over 8000 stationary large bore (bore greater than 35 cm) natural gas engines for natural gas compression on pipelines and power generation. Much of the research in the past 10-20 years on large bore natural gas engines has been aimed at enhancing the mixing process. This includes hardware modifications as well as CFD work. The objectives of this project were to design and build a laboratory for laser diagnostics of in-cylinder processes in large and medium bore engines; to develop and demonstrate a technique to directly characterize fuel and air mixing and the scavenging process in a large bore engine and to characterize mixing and scavenging in a large bore two-stroke cycle natural gas engine with both standard and high pressure fuel injection. Much of the project involved the design, assembly, and testing of original prototype hardware, so the generation of results was only a small part of the overall project. However, significant findings were realized. The performance of the low and high pressure fuel valves helped explain many of the results from on-engine testing of the GMV-4TF during the original high pressure fuel injection development testing. The biggest implication that relates to future work is that the air and fuel mixture at spark is not uniformly mixed, even for the high-pressure injection case that showed significant engine performance improvements.
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