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Статті в журналах з теми "High speed ADC/DAC"
Azarov, O. D., S. V. Bohomolov, and O. Y. Stahov. "MULTICHANNEL SPEED ADC-DAC SYSTEM BASED ON HIGH-LINE CURRENT-CURRENT CONVERTERS." Information technology and computer engineering 50, no. 1 (2021): 69–79. http://dx.doi.org/10.31649/1999-9941-2021-50-1-69-79.
Повний текст джерелаCheng, Li, Jiao Xu, Yi Xin Zhang, and Ning Yang. "Design of High-Speed and Low-Power Two-Channel Pipeline ADC." Advanced Materials Research 328-330 (September 2011): 1820–23. http://dx.doi.org/10.4028/www.scientific.net/amr.328-330.1820.
Повний текст джерелаWang, Li, Wenli Chen, Kai Chen, Renjun He, and Wenjian Zhou. "The Research on the Signal Generation Method and Digital Pre-Processing Based on Time-Interleaved Digital-to-Analog Converter for Analog-to-Digital Converter Testing." Applied Sciences 12, no. 3 (February 7, 2022): 1704. http://dx.doi.org/10.3390/app12031704.
Повний текст джерелаKakarla, Deepti. "An optimized design approach for 8-bit pipelined ADC using high gain amplifier." i-manager’s Journal on Electronics Engineering 12, no. 2 (2022): 23. http://dx.doi.org/10.26634/jele.12.2.18529.
Повний текст джерелаArafa, Kawther I., Dina M. Ellaithy, Abdelhalim Zekry, Mohamed Abouelatta, and Heba Shawkey. "Successive Approximation Register Analog-to-Digital Converter (SAR ADC) for Biomedical Applications." Active and Passive Electronic Components 2023 (January 4, 2023): 1–29. http://dx.doi.org/10.1155/2023/3669255.
Повний текст джерелаYe, Wen Hua, and Huan Li. "Design of Virtex-7 FPGA-Based High-Speed Signal Processor Carrier Board." Applied Mechanics and Materials 719-720 (January 2015): 534–37. http://dx.doi.org/10.4028/www.scientific.net/amm.719-720.534.
Повний текст джерелаChauhan, Sarita. "Implementation of 32-BIT Pipelined ADC Using 90nm Analog CMOS Technology." International Journal for Research in Applied Science and Engineering Technology 9, no. VII (July 31, 2021): 3073–80. http://dx.doi.org/10.22214/ijraset.2021.37002.
Повний текст джерелаShetty, Chaya, M. Nagabushanam, and Venkatesh Nuthan Prasad. "A 14-bit High Speed 125MS/s Low Power SAR ADC using Dual Split Capacitor DAC Architecture in 90nm CMOS Technology." International Journal of Circuits, Systems and Signal Processing 15 (June 29, 2021): 556–68. http://dx.doi.org/10.46300/9106.2021.15.62.
Повний текст джерелаBchir, Mounira, Thouraya Ettaghzouti, and Néjib Hassen. "A Novel High Frequency Low Voltage Low Power Current Mode Analog to Digital Converter Pipeline." Journal of Low Power Electronics 15, no. 4 (December 1, 2019): 368–78. http://dx.doi.org/10.1166/jolpe.2019.1621.
Повний текст джерелаVasudeva, G., and B. V. Uma. "Design and Implementation of High Speed and Low Power 12-bit SAR ADC using 22nm FinFET." WSEAS TRANSACTIONS ON SYSTEMS AND CONTROL 17 (January 3, 2022): 1–15. http://dx.doi.org/10.37394/23203.2022.17.1.
Повний текст джерелаДисертації з теми "High speed ADC/DAC"
Swindlehurst, Eric Lee. "High-Speed and Low-Power Techniques for Successive-Approximation-Register Analog-to-Digital Converters." BYU ScholarsArchive, 2020. https://scholarsarchive.byu.edu/etd/8923.
Повний текст джерелаLu, Dongtian. "High speed CMOS ADC for UWB receiver /." View abstract or full-text, 2007. http://library.ust.hk/cgi/db/thesis.pl?ECED%202007%20LUD.
Повний текст джерелаHiremath, Vinayashree. "DESIGN OF ULTRA HIGH SPEED FLASH ADC, LOW POWER FOLDING AND INTERPOLATING ADC IN CMOS 90nm TECHNOLOGY." Wright State University / OhioLINK, 2010. http://rave.ohiolink.edu/etdc/view?acc_num=wright1291391500.
Повний текст джерелаSivakumar, Balasubramanian. "A 6-Bit Sub-Ranging High Speed Flash Analog To Digital Converter With Digital Speed And Power Control." The Ohio State University, 2008. http://rave.ohiolink.edu/etdc/view?acc_num=osu1229631191.
Повний текст джерелаWang, Mingzhen. "High-speed Low-voltage CMOS Flash Analog-to-Digital Converter for Wideband Communication System-on-a-Chip." Wright State University / OhioLINK, 2007. http://rave.ohiolink.edu/etdc/view?acc_num=wright1189815482.
Повний текст джерелаKaald, Rune. "Modelling, Simulation and Implementation Considerations of High Speed Continuous Time Sigma Delta ADC." Thesis, Norwegian University of Science and Technology, Department of Electronics and Telecommunications, 2008. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-8942.
Повний текст джерелаA found state of the art Continuous Time Sigma Delta ADC is modelled and simulated for the presence of nonidealities. A comparison between two Excess Loop Delay compensation techniques is done, the digital differentiation technique was found to have lower swing at the last integrator, and did not need a gain-bandwidth induced delay sensitive summing amplifier. The detrimental influence of clock jitter is shown. Different DAC linearization techniques are discussed, the DWA algorithm was simulated and found to be the best choice for linearizing the DACs. Through high level modeling in Simulink and verification in the Cadence framework specifications for each building block was determined, a final simulation resulted in a SNDR of 76.3 dB.
Homsi, Mustafa Al. "High speed ADC design targeting the UWB system using TSMC 0.18uM technology process." The Ohio State University, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=osu1399551999.
Повний текст джерелаShar, Ahmad. "Design of a High-Speed CMOS Comparator." Thesis, Linköping University, Department of Electrical Engineering, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-10446.
Повний текст джерелаThis master thesis describes the design of high-speed latched comparator with 6-bit resolution, full scale voltage of 1.6 V and the sampling frequency of 250 MHz. The comparator is designed in a 0.35 9m CMOS process with a supply voltage of 3.3 V.
The comparator is designed for time-interleaved bandpass sigma-delta ADC.
Due to the nature of the target application, it should be possible to turn off the components to avoid the static power consumption. The comparator of this design implements the turn off technique when it is not in use. The settling time of the comparator is less than half the clock cycle which means it does not effect the functionality of the bandpass sigma-delta ADC in terms of speed.
The simulation results are derived using Cadence environment. The results show that the comparator has 6-bit resolution and power consumption of 4.13 mW for the worst-case frequency of 250 MHz. It fulfills all the performance requirements, most of them with large margins.
Figueiredo, Michael. "Reference-free high-speed cmos pipeline analog-to-digital converters." Doctoral thesis, Faculdade de Ciências e Tecnologia, 2012. http://hdl.handle.net/10362/8776.
Повний текст джерелаMore and more signal processing is being transferred to the digital domain to profit from the technological enhancement of digital circuits. Where technology scaling enhances the capabilities of digital circuits, it degrades the performance of analog circuits. However, it is important to note that the impact that technology scaling has on digital circuits is becoming smaller and smaller, which means that, in nanotechnologies, to enhance energy and area efficiency, we can not simply depend on the benefits of this scaling. Although, a share of the efficiency can be obtained from the technology, new circuit architectures and techniques have to be developed to really push the limits of efficiency. In data converters, more specifically analog-to-digital converters (ADCs), a decision can be made: research energy and area efficient analog circuit techniques and architectures that cope with technological scaling issues, or design algorithms that use digital circuitry to assist the poor analog technological performance. The former option is the premise for the work developed in this thesis. The work reported in this thesis explores various design techniques with the purpose of enhancing the power and area efficiency of building blocks mainly to be used in multiplying digital-to-analog converter based ADCs. Therefore, novel analog techniques are developed for the three main blocks of an MDAC-based stage, namely, the flash quantizer, the amplifier, and the switched capacitor network of the MDAC. These techniques include self-biasing and inverter-based design for the flash quantizer and amplifier. Regarding the MDAC, it combines three techniques: unity feedback factor, insensitivity to capacitor mismatch, and current-mode reference shifting. In the second part of this work, the designed amplifier is implemented and experimentally characterized demonstrating its practical feasibility and performance. The final part of this work explores the design and implementation of a medium-low resolution high speed pipeline ADC incorporating all the developed circuits. Experimental results validate the feasibility of the techniques and demonstrate the attractiveness in terms of power dissipation and reduced area.
Elkafrawy, Abdelrahman [Verfasser]. "Concept and design of a high speed current mode based SAR ADC / Abdelrahman Elkafrawy." Ulm : Universität Ulm, 2016. http://d-nb.info/1108434592/34.
Повний текст джерелаКниги з теми "High speed ADC/DAC"
Gottardo, Marco. FPGA to High Speed Adc Data Streaming. Lulu Press, Inc., 2018.
Знайти повний текст джерелаTakenaka, Norio. PIC32 FRM, Section 22 High-Speed SAR ADC. Microchip Technology Incorporated, 2016.
Знайти повний текст джерелаZhou, Clarence. Designing Digital RF Receiver Using MCP37DXX High-Speed ADC. Microchip Technology Incorporated, 2020.
Знайти повний текст джерелаTakenaka, Norio. AN2497 - Designing Digital RF Receiver Using MCP37DXX High-Speed ADC. Microchip Technology Incorporated, 2020.
Знайти повний текст джерелаLee, Jade. 12-Bit High-Speed, Multiple SARs a/d Converter (ADC). Microchip Technology Incorporated, 2015.
Знайти повний текст джерелаBoles, Melanie. AN2497, Designing Digital RF Receiver Using MCP37DXX High-Speed ADC. Microchip Technology Incorporated, 2018.
Знайти повний текст джерелаJiang, Linda. 12-Bit High-Speed, Multiple SARs a/d Converter (ADC). Microchip Technology Incorporated, 2017.
Знайти повний текст джерелаJiang, Linda. 12-Bit High-Speed, Multiple SARs a/d Converter (ADC). Microchip Technology Incorporated, 2018.
Знайти повний текст джерелаJiang, Linda. SPIC33/PIC24 FRM - High-Speed Analog Comparator with Slope Compensation DAC. Microchip Technology Incorporated, 2020.
Знайти повний текст джерелаBoles, Melanie. DsPIC33/PIC24 FRM, High-Speed Analog Comparator with Slope Compensation DAC. Microchip Technology Incorporated, 2019.
Знайти повний текст джерелаЧастини книг з теми "High speed ADC/DAC"
Zhang, Feng. "ADC, DAC Data Transmission Based on JESD204 Protocol." In High-speed Serial Buses in Embedded Systems, 85–130. Singapore: Springer Singapore, 2020. http://dx.doi.org/10.1007/978-981-15-1868-3_3.
Повний текст джерелаZheng, Yong, Xiao-han Guan, and Wen-jia Li. "Design and Implementation of High-Speed ADC and DAC Based on SPI Technology in TMS320F2808DSP Control System." In 2011 International Conference in Electrics, Communication and Automatic Control Proceedings, 1697–704. New York, NY: Springer New York, 2011. http://dx.doi.org/10.1007/978-1-4419-8849-2_220.
Повний текст джерелаKrishna, K. Lokesh, Yahya Mohammed Ali Al-Naamani, and K. Anuradha. "A High Speed Two Step Flash ADC." In Soft Computing Systems, 826–36. Singapore: Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-13-1936-5_84.
Повний текст джерелаChaudhary, Kapil, B. K. Kaushik, and Kirat Pal. "Design of High Speed Optimized Flash ADC." In Computer Networks and Information Technologies, 260–63. Berlin, Heidelberg: Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-19542-6_42.
Повний текст джерелаLouwsma, Simon, Ed van Tuijl, and Bram Nauta. "Implementation of a High-speed Time-interleaved ADC." In Time-interleaved Analog-to-Digital Converters, 71–124. Dordrecht: Springer Netherlands, 2011. http://dx.doi.org/10.1007/978-90-481-9716-3_4.
Повний текст джерелаRamkaj, Athanasios T., Marcel J. M. Pelgrom, Michiel S. J. Steyaert, and Filip Tavernier. "High-Speed Wide-Bandwidth Single-Channel SAR ADC." In Analog Circuits and Signal Processing, 149–81. Cham: Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-031-22709-7_5.
Повний текст джерелаPalermo, Samuel, Sebastian Hoyos, Shiva Kiran, Shengchang Cai, and Yuanming Zhu. "ADC/DSP-Based Receivers for High-Speed Serial Links." In Analog Circuits for Machine Learning, Current/Voltage/Temperature Sensors, and High-speed Communication, 247–67. Cham: Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-030-91741-8_14.
Повний текст джерелаSin, Sai-Weng, Seng-Pan U, and Rui Paulo Martins. "Time-Interleaving: Multiplying the Speed of the ADC." In Generalized Low-Voltage Circuit Techniques for Very High-Speed Time-Interleaved Analog-to-Digital Converters, 55–74. Dordrecht: Springer Netherlands, 2010. http://dx.doi.org/10.1007/978-90-481-9710-1_4.
Повний текст джерелаKull, Lukas, Thomas Toifl, Martin Schmatz, Pier Andrea Francese, Christian Menolfi, Matthias Braendli, Marcel Kossel, Thomas Morf, Toke Meyer Andersen, and Yusuf Leblebici. "Energy-Efficient High-Speed SAR ADCs in CMOS." In High-Performance AD and DA Converters, IC Design in Scaled Technologies, and Time-Domain Signal Processing, 45–63. Cham: Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-07938-7_3.
Повний текст джерелаZhuang, Yuming, and Degang Chen. "High-Purity Sine Wave Generation Using Nonlinear DAC with Pre-distortion Based on Low-Cost Accurate DAC-ADC Co-testing." In Accurate and Robust Spectral Testing with Relaxed Instrumentation Requirements, 59–78. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-77718-4_4.
Повний текст джерелаТези доповідей конференцій з теми "High speed ADC/DAC"
Bedi, R. "Low-power, high-speed, ADC/DAC design for satellite communications." In 5th IEE International Conference on ADDA 2005. Advanced A/D and D/A Conversion Techniques and their Applications. IEE, 2005. http://dx.doi.org/10.1049/cp:20050133.
Повний текст джерелаKilic, Mustafa, and Yusuf Leblebici. "A DAC assisted speed enhancement technique for high resolution SAR ADC." In 2017 13th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME). IEEE, 2017. http://dx.doi.org/10.1109/prime.2017.7974155.
Повний текст джерелаHeikkinen, Veli, Eveliina Juntunen, Mikko Karppinen, Kari Kautio, Aila Sitomaniemi, Antti Tanskanen, Hélène Gachon, et al. "High-speed ADC and DAC modules with fibre optic interconnections for telecom satellites." In International Conference on Space Optics 2008, edited by Josiane Costeraste, Errico Armandillo, and Nikos Karafolas. SPIE, 2017. http://dx.doi.org/10.1117/12.2308251.
Повний текст джерелаElkafrawy, Abdelrahman, Jens Anders, Timon Bruckner, and Maurits Ortmanns. "Design of a current steering DAC for a high speed current mode SAR ADC." In 2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS). IEEE, 2013. http://dx.doi.org/10.1109/icecs.2013.6815449.
Повний текст джерелаChun, Ji Hwan (Paul), Hak-soo Yu, and Jacob A. Abraham. "An efficient linearity test for on-chip high speed ADC and DAC using loop-back." In Proceedins of the 14th ACM Great Lakes symposium. New York, New York, USA: ACM Press, 2004. http://dx.doi.org/10.1145/988952.989031.
Повний текст джерелаVarughese, S., T. Richter, S. Tibuleac, and S. E. Ralph. "Joint optimization of DAC and ADC based on frequency dependent ENOB analysis for high speed optical systems." In 45th European Conference on Optical Communication (ECOC 2019). Institution of Engineering and Technology, 2019. http://dx.doi.org/10.1049/cp.2019.0928.
Повний текст джерелаG, Naveen I., Ramachandra A. C, and Manohara H. T. "A Low Power High-Speed 12-Bit SAR ADC using Split Capacitor Based DAC at 45 nm CMOS Technology." In 2022 IEEE 2nd Mysore Sub Section International Conference (MysuruCon). IEEE, 2022. http://dx.doi.org/10.1109/mysurucon55714.2022.9972699.
Повний текст джерелаWang, Xiaoyang, Xiong Zhou, and Qiang Li. "A energy-efficient high speed segmented prequantize and bypass DAC for SAR ADCs." In 2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS). IEEE, 2014. http://dx.doi.org/10.1109/mwscas.2014.6908361.
Повний текст джерела"Very high-speed ADCs and DACs." In 2006 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. IEEE, 2006. http://dx.doi.org/10.1109/isscc.2006.1696293.
Повний текст джерелаGrozing, Markus, Damir Ferenci, Felix Lang, Thomas Alpert, Hao Huang, Jochen Briem, Thomas Veigel, and Manfred Berroth. "High-speed CMOS DACs and ADCs for broadband communication." In 2013 IEEE/MTT-S International Microwave Symposium - MTT 2013. IEEE, 2013. http://dx.doi.org/10.1109/mwsym.2013.6697601.
Повний текст джерела