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Добірка наукової літератури з теми "Heterogeneous embedded systems"

Автор: Grafiati

Опубліковано: 22 жовтня 2022

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Статті в журналах з теми "Heterogeneous embedded systems"

Berrahou, Aissam, Nassim Sefrioui, Ouafaa Diouri, and Mohsine Eleuldj. "Exploration of Heterogeneous Resources in Embedded Systems." International Review on Computers and Software (IRECOS) 9, no. 9 (September 30, 2014): 1597. http://dx.doi.org/10.15866/irecos.v9i9.3160.

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Grimm, Christoph, Axel Jantsch, Sandeep Shukla, and Eugenio Villar. "C-Based Design of Heterogeneous Embedded Systems." EURASIP Journal on Embedded Systems 2008, no. 1 (2008): 243890. http://dx.doi.org/10.1155/2008/243890.

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Syschikov, Alexey, Yuriy Sheynin, Boris Sedov, and Vera Ivanova. "Domain-Specific Programming Environment for Heterogeneous Multicore Embedded Systems." International Journal of Embedded and Real-Time Communication Systems 5, no. 4 (October 2014): 1–23. http://dx.doi.org/10.4018/ijertcs.2014100101.

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Nowadays embedded systems are used in a broad range of domains such as avionics, space, automotive, mobile, domestic appliances etc. Sophisticated software determines the quality of embedded systems and requires high-qualified experts for software development. Software becomes the main assert of embedded systems that is valuable to retain in changing computing platforms in embedded systems evolution. Computing platforms for embedded systems became multicore processors and SoC, they can change in the embedded system lifetime that could be long (dozen of years for an automobile and airplane). It requires software porting to new platforms as a regular process. Many tools and approaches allow developing of software for domain area experts, but mainly for general-purpose computing systems. In this paper the authors present the complex technology and tools that allows involving domain experts in software development for embedded systems. The proposed technology has various aspects and abilities that can be used to build verifiable and portable software for a wide range of embedded platforms.

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Latif, Rachid, and Amine Saddik. "Embedded implementation of biomedical applications in heterogeneous systems." Biomedical Spectroscopy and Imaging 8, no. 3-4 (January 27, 2020): 73–80. http://dx.doi.org/10.3233/bsi-200192.

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Edwards, S. A., and O. Tardieu. "SHIM: a deterministic model for heterogeneous embedded systems." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 14, no. 8 (August 2006): 854–67. http://dx.doi.org/10.1109/tvlsi.2006.878473.

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Radojevic, Ivan, Zoran Salcic, and Partha Roop. "Design of Distributed Heterogeneous Embedded Systems in DDFCharts." IEEE Transactions on Parallel and Distributed Systems 22, no. 2 (February 2011): 296–308. http://dx.doi.org/10.1109/tpds.2010.69.

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Josko, Bernhard, Qin Ma, and Alexander Metzner. "5.1.2 Designing Embedded Systems using Heterogeneous Rich Components1." INCOSE International Symposium 18, no. 1 (June 2008): 558–76. http://dx.doi.org/10.1002/j.2334-5837.2008.tb00827.x.

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Monjau, D., and M. Sporer. "Semantic Modelling and Simulation of Heterogeneous Embedded Systems." International Journal of Modelling and Simulation 26, no. 3 (January 2006): 201–11. http://dx.doi.org/10.1080/02286203.2006.11442369.

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Jammalamadaka, Sastry Kodanda Rama, Valluru Sai Kumar Reddy, and Smt J Sasi Bhanu. "Networking Heterogeneous Microcontroller based Systems through Universal Serial Bus." International Journal of Electrical and Computer Engineering (IJECE) 5, no. 5 (October 1, 2015): 992. http://dx.doi.org/10.11591/ijece.v5i5.pp992-1002.

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Networking heterogeneous embedded systems is a challenge. Every distributed embedded systems requires that the network is designed specifically considering the heterogeneity that exits among different Microcontroller based systems that are used in developing a distributed embedded system. Communication architecture, which considers the addressing of the individual systems, arbitration, synchronisation, error detection and control etc., needs to be designed considering a specific application. The issue of configuring the slaves has to be addressed. It is also important that the messages, flow of the messages across the individual ES systems must be designed. Every distributed embedded system is different and needs to be dealt with separately. This paper presents an approach that addresses various issues related to networking distributed embedded systems through use of universal serial bus communication protocol (USB). The approach has been applied to design a distributed embedded that monitors and controls temperatures within a Nuclear reactor system.

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Garbo, Alessandro, and Stefano Quer. "Moving Object Detection in Heterogeneous Conditions in Embedded Systems." Sensors 17, no. 7 (July 1, 2017): 1546. http://dx.doi.org/10.3390/s17071546.

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Дисертації з теми "Heterogeneous embedded systems"

Diarra, Rokiatou. "Automatic Parallelization for Heterogeneous Embedded Systems." Thesis, Université Paris-Saclay (ComUE), 2019. http://www.theses.fr/2019SACLS485.

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L'utilisation d'architectures hétérogènes, combinant des processeurs multicoeurs avec des accélérateurs tels que les GPU, FPGA et Intel Xeon Phi, a augmenté ces dernières années. Les GPUs peuvent atteindre des performances significatives pour certaines catégories d'applications. Néanmoins, pour atteindre ces performances avec des API de bas niveau comme CUDA et OpenCL, il est nécessaire de réécrire le code séquentiel, de bien connaître l’architecture des GPUs et d’appliquer des optimisations complexes, parfois non portables. D'autre part, les modèles de programmation basés sur des directives (par exemple, OpenACC, OpenMP) offrent une abstraction de haut niveau du matériel sous-jacent, simplifiant ainsi la maintenance du code et améliorant la productivité. Ils permettent aux utilisateurs d’accélérer leurs codes séquentiels sur les GPUs en insérant simplement des directives. Les compilateurs d'OpenACC/OpenMP ont la lourde tâche d'appliquer les optimisations nécessaires à partir des directives fournies par l'utilisateur et de générer des codes exploitant efficacement l'architecture sous-jacente. Bien que les compilateurs d'OpenACC/OpenMP soient matures et puissent appliquer certaines optimisations automatiquement, le code généré peut ne pas atteindre l'accélération prévue, car les compilateurs ne disposent pas d'une vue complète de l'ensemble de l'application. Ainsi, il existe généralement un écart de performance important entre les codes accélérés avec OpenACC/OpenMP et ceux optimisés manuellement avec CUDA/OpenCL. Afin d'aider les programmeurs à accélérer efficacement leurs codes séquentiels sur GPU avec les modèles basés sur des directives et à élargir l'impact d'OpenMP/OpenACC dans le monde universitaire et industrielle, cette thèse aborde plusieurs problématiques de recherche. Nous avons étudié les modèles de programmation OpenACC et OpenMP et proposé une méthodologie efficace de parallélisation d'applications avec les approches de programmation basées sur des directives. Notre expérience de portage d'applications a révélé qu'il était insuffisant d'insérer simplement des directives de déchargement OpenMP/OpenACC pour informer le compilateur qu'une région de code particulière devait être compilée pour être exécutée sur la GPU. Il est essentiel de combiner les directives de déchargement avec celles de parallélisation de boucle. Bien que les compilateurs actuels soient matures et effectuent plusieurs optimisations, l'utilisateur peut leur fournir davantage d'informations par le biais des clauses des directives de parallélisation de boucle afin d'obtenir un code mieux optimisé. Nous avons également révélé le défi consistant à choisir le bon nombre de threads devant exécuter une boucle. Le nombre de threads choisi par défaut par le compilateur peut ne pas produire les meilleures performances. L'utilisateur doit donc essayer manuellement différents nombres de threads pour améliorer les performances. Nous démontrons que les modèles de programmation OpenMP et OpenACC peuvent atteindre de meilleures performances avec un effort de programmation moindre, mais les compilateurs OpenMP/OpenACC atteignent rapidement leur limite lorsque le code de région déchargée a une forte intensité arithmétique, nécessite un nombre très élevé d'accès à la mémoire globale et contient plusieurs boucles imbriquées. Dans de tels cas, des langages de bas niveau doivent être utilisés. Nous discutons également du problème d'alias des pointeurs dans les codes GPU et proposons deux outils d'analyse statiques qui permettent d'insérer automatiquement les qualificateurs de type et le remplacement par scalaire dans le code source
Recent years have seen an increase of heterogeneous architectures combining multi-core CPUs with accelerators such as GPU, FPGA, and Intel Xeon Phi. GPU can achieve significant performance for certain categories of application. Nevertheless, achieving this performance with low-level APIs (e.g. CUDA, OpenCL) requires to rewrite the sequential code, to have a good knowledge of GPU architecture, and to apply complex optimizations that are sometimes not portable. On the other hand, directive-based programming models (e.g. OpenACC, OpenMP) offer a high-level abstraction of the underlying hardware, thus simplifying the code maintenance and improving productivity. They allow users to accelerate their sequential codes on GPU by simply inserting directives. OpenACC/OpenMP compilers have the daunting task of applying the necessary optimizations from the user-provided directives and generating efficient codes that take advantage of the GPU architecture. Although the OpenACC / OpenMP compilers are mature and able to apply some optimizations automatically, the generated code may not achieve the expected speedup as the compilers do not have a full view of the whole application. Thus, there is generally a significant performance gap between the codes accelerated with OpenACC/OpenMP and those hand-optimized with CUDA/OpenCL. To help programmers for speeding up efficiently their legacy sequential codes on GPU with directive-based models and broaden OpenMP/OpenACC impact in both academia and industry, several research issues are discussed in this dissertation. We investigated OpenACC and OpenMP programming models and proposed an effective application parallelization methodology with directive-based programming approaches. Our application porting experience revealed that it is insufficient to simply insert OpenMP/OpenACC offloading directives to inform the compiler that a particular code region must be compiled for GPU execution. It is highly essential to combine offloading directives with loop parallelization constructs. Although current compilers are mature and perform several optimizations, the user may provide them more information through loop parallelization constructs clauses in order to get an optimized code. We have also revealed the challenge of choosing good loop schedules. The default loop schedule chosen by the compiler may not produce the best performance, so the user has to manually try different loop schedules to improve the performance. We demonstrate that OpenMP and OpenACC programming models can achieve best performance with lesser programming effort, but OpenMP/OpenACC compilers quickly reach their limit when the offloaded region code is computed/memory bound and contain several nested loops. In such cases, low-level languages may be used. We also discuss pointers aliasing problem in GPU codes and propose two static analysis tools that perform automatically at source level type qualifier insertion and scalar promotion to solve aliasing issues

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Valente, Frederico Miguel Goulão. "Static analysis on embedded heterogeneous multiprocessor systems." Master's thesis, Universidade de Aveiro, 2008. http://hdl.handle.net/10773/2180.

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Fischaber, Scott Johan. "Memory-centric system level design of heterogeneous embedded DSP systems." Thesis, Queen's University Belfast, 2008. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.491885.

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Modern embedded systems for DSP applications are increasingly being implemented on heterogeneous processing architectures, consisting of multiple processors and programmable hardware such as FPGAs. The layered memory structure of FPGAs provides an open platform for memory organisation which many algorithms can benefit from. To efficiently target these platforms, high level design tools are being developed to target these architectures; often for DSP applications, these tools have been based around process networks, and as such, their memory architectures typically closely match the simple FIFO buffering employed by these models. This is not always ideal in a hardware implementation, where off-chip memory accesses may be required, particularly when there is data reuse inherent to the algorithm. This thesis proposes a formalised methodology to synthesise efficient memory architectures for FPGA-based DSP systems from a high level dataflow model. This includes reducing the memory requirements of the system through transformations, model refinements and by including the hardware characteristics into the dataflow analysis: Standard dataflow transformations have been characterised so that their effects on the memory subsystem are apparent and these transformations have been placed appropriately in a memory-centric design flow. The memory generation techniques for hardware cores on these FPGA platforms are also analysed, providing extensions which can reduce memory requirements through automatic sub-scheduling using a range of MoCs. These techniques effectively target the distributed nature of FPGA memories to introduce memory hierarchies into the implementations, targeting any data reuse inherent to the application which can take advantage of the memory architecture. This layered memory approach is used to reduce the number of accesses reqUired to large memories, which in turn can increase performance and reduce power consumption. For a motion estimation algorithm the reqUired bandwidth for off-chip memory accesses can vary by a factor of a thousand between two DFGs. For a 2-D convolution algorithm, the total reqUired memory is reduced by half though refinement of the system level model. This methodology has been demonstrated in the design of a video encoder and template matching algorithm and used to efficiently implement the memory sub-systems.

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Hines, Kenneth J. "Coordination-centric debugging for heterogeneous distributed embedded systems /." Thesis, Connect to this title online; UW restricted, 2000. http://hdl.handle.net/1773/6914.

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Peterson, Thomas. "Dynamic Allocation for Embedded Heterogeneous Memory : An Empirical Study." Thesis, KTH, Skolan för elektroteknik och datavetenskap (EECS), 2018. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-223904.

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Embedded systems are omnipresent and contribute to our lives in many ways by instantiating functionality in larger systems. To operate, embedded systems require well-functioning software, hardware as well as an interface in-between these. The hardware and software of these systems is under constant change as new technologies arise. An actual change these systems are undergoing are the experimenting with different memory management techniques for RAM as novel non-volatile RAM(NVRAM) technologies have been invented. These NVRAM technologies often come with asymmetrical read and write latencies and thus motivate designing memory consisting of multiple NVRAMs. As a consequence of these properties and memory designs there is a need for memory management that minimizes latencies.This thesis addresses the problem of memory allocation on heterogeneous memory by conducting an empirical study. The first part of the study examines free list, bitmap and buddy system based allocation techniques. The free list allocation technique is then concluded to be superior. Thereafter, multi-bank memory architectures are designed and memory bank selection strategies are established. These strategies are based on size thresholds as well as memory bank occupancies. The evaluation of these strategies did not result in any major conclusions but showed that some strategies were more appropriate for someapplication behaviors.
Inbyggda system existerar allestädes och bidrar till våran livsstandard på flertalet avseenden genom att skapa funktionalitet i större system. För att vara verksamma kräver inbyggda system en välfungerande hård- och mjukvara samt gränssnitt mellan dessa. Dessa tre måste ständigt omarbetas i takt med utvecklingen av nya användbara teknologier för inbyggda system. En förändring dessa system genomgår i nuläget är experimentering med nya minneshanteringstekniker för RAM-minnen då nya icke-flyktiga RAM-minnen utvecklats. Dessa minnen uppvisar ofta asymmetriska läs och skriv fördröjningar vilket motiverar en minnesdesign baserad på flera olika icke-flyktiga RAM. Som en konsekvens av dessa egenskaper och minnesdesigner finns ett behov av att hitta minnesallokeringstekniker som minimerar de fördröjningar som skapas. Detta dokument adresserar problemet med minnesallokering på heterogena minnen genom en empirisk studie. I den första delen av studien studerades allokeringstekniker baserade på en länkad lista, bitmapp och ett kompissystem. Med detta som grund drogs slutsatsen att den länkade listan var överlägsen alternativen. Därefter utarbetades minnesarkitekturer med flera minnesbanker samtidigt som framtagandet av flera strategier för val av minnesbank utfördes. Dessa strategier baserades på storleksbaserade tröskelvärden och nyttjandegrad hos olika minnesbanker. Utvärderingen av dessa strategier resulterade ej i några större slutsatser men visade att olika strategier var olika lämpade för olika beteenden hos applikationer.

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Vincenzo, Stoico. "A Model-Driven Approach for modeling Heterogeneous Embedded Systems." Thesis, Mälardalens högskola, Akademin för innovation, design och teknik, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:mdh:diva-44199.

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Demands of high-performance systems guided the designers to the assessment of heterogeneous embedded systems (HES). Their complexity highlighted the need for methodologies and tools to ease their design. Model-Driven Engineering (MDE) can be crucial to facilitate the design of such a system. Research has demonstrated the usage of MDE to create platform-specific models(PSM). The aim of this work is to support HES design targeting platform-agnostic models. This work is based on a well-defined use case. It comprises a software application, written following the CUDA programming model, executing on a CPU-GPU hardware platform. The use case is analyzed to define the main characteristics of a HES. These concerns are included in a UML profile used to capture all the features of a HES. The profile is built as an extension of MARTE modeling language. Finally, the Alf action language is applied to make the model executable. The results prove the suitability of MARTE and Alf to create executable HES models. Additional research is needed to further investigate the HES domain. Finally, it is necessary to prove the validity of the UML profile targeting different programming models and hardware platforms.

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Pop, Traian. "Analysis and Optimisation of Distributed Embedded Systems with Heterogeneous Scheduling Policies." Doctoral thesis, Linköping : Department of Computer and Information Science, Linköpings universitet, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-8934.

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Eriksson, Jonas. "Partitioning methodology validation for embedded systems design." Thesis, Linköpings universitet, Programvara och system, 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-129332.

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As modern embedded systems are becoming more sophisticated the demands on their applications significantly increase. A current trend is to utilize the advances of heterogeneous platforms (i.e. platform consisting of different computational units (e.g. CPU, FPGA or GPU)) where different parts of the application can be distributed among the different computational units as software and hardware implementations. This technology can improve the application characteristics to meet requirements (e.g. execution time, power consumption and design cost), but it leads to a new challenge in finding the best combination of hardware and software implementation (referred as system configuration). The decisions whether a part of the application should be implemented in software (e.g. as C code) or hardware (e.g. as VHDL code) affect the entire product life-cycle. This is traditionally done manually by the developers in the early stage of the design phase. However, due to the increasing complexity of the application the need of a systematic process that aids the developer when making these decisions to meet the demands rises. Prior to this work a methodology called MULTIPAR has been designed to address this problem. MULTIPAR applies component-/model-based techniques to design the application, i.e. the application is modeled as a number of interconnected components, where some of the components will be implemented as software and the remaining ones as hardware. To perform the partitioning decisions, i.e. determining for each component whether it should be implemented as software or hardware, MULTIPAR proposes a set of formulas to calculate the properties of the entire system based on the properties for each component working in isolation. This thesis aims to show to what extent the proposed system formulas are valid. In particular it focuses on validating the formulas that calculate the system response time, system power consumption, system static memory and system FPGA area. The formulas were validated trough an industrial case study, where the system properties for different system configurations were measured and calculated by applying these formulas. The measured values and calculated values for the system properties were compared by conducting a statistical analysis. The case study demonstrated that the system properties can be accurately calculated by applying the system formulas.

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Pop, Traian. "Scheduling and Optimisation of Heterogeneous Time/Event-Triggered Distributed Embedded Systems." Licentiate thesis, Linköping : Univ, 2003. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-5691.

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Lifa, Adrian Alin. "Hardware/Software Codesign of Embedded Systems with Reconfigurable and Heterogeneous Platforms." Doctoral thesis, Linköpings universitet, Programvara och system, 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-117637.

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Modern applications running on today's embedded systems have very high requirements. Most often, these requirements have many dimensions: the applications need high performance as well as exibility, energy-eciency as well as real-time properties, fault tolerance as well as low cost. In order to meet these demands, the industry is adopting architectures that are more and more heterogeneous and that have reconguration capabilities. Unfortunately, this adds to the complexity of designing streamlined applications that can leverage the advantages of such architectures. In this context, it is very important to have appropriate tools and design methodologies for the optimization of such systems. This thesis addresses the topic of hardware/software codesign and optimization of adaptive real-time systems implemented on recongurable and heterogeneous platforms. We focus on performance enhancement for dynamically recongurable FPGA-based systems, energy minimization in multi-mode real-time systems implemented on heterogeneous platforms, and codesign techniques for fault-tolerant systems. The solutions proposed in this thesis have been validated by extensive experiments, ranging from computer simulations to proof of concept implementations on real-life platforms. The results have conrmed the importance of the addressed aspects and the applicability of our techniques for design optimization of modern embedded systems.

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Книги з теми "Heterogeneous embedded systems"

Ian, O'Connor, Piguet Christian, and SpringerLink (Online service), eds. Design Technology for Heterogeneous Embedded Systems. Dordrecht: Springer Science+Business Media B.V., 2012.

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Nicolescu, Gabriela, Ian O'Connor, and Christian Piguet, eds. Design Technology for Heterogeneous Embedded Systems. Dordrecht: Springer Netherlands, 2012. http://dx.doi.org/10.1007/978-94-007-1125-9.

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Peón Quirós, Miguel, Francky Catthoor, and José Manuel Mendías Cuadros. Heterogeneous Memory Organizations in Embedded Systems. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-37432-7.

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Uchiyama, Kunio. Heterogeneous Multicore Processor Technologies for Embedded Systems. New York, NY: Springer New York, 2012.

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Uchiyama, Kunio, Fumio Arakawa, Hironori Kasahara, Tohru Nojiri, Hideyuki Noda, Yasuhiro Tawara, Akio Idehara, Kenichi Iwata, and Hiroaki Shikano. Heterogeneous Multicore Processor Technologies for Embedded Systems. New York, NY: Springer New York, 2012. http://dx.doi.org/10.1007/978-1-4614-0284-8.

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Pop, Traian. Analysis and optimisation of distributed embedded systems with heterogeneous scheduling policies. Linköping: Department of Computer and Information Science, Linköpings universitet, 2007.

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Pop, Traian. Scheduling and optimisation of heterogeneous time/event-triggered distributed embedded systems. Linko ping: Univ., 2003.

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Hardware/software co-design for heterogeneous multi-core platforms: The hArtes toolchain. Dordrecht: Springer, 2012.

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Babina, Ol'ga. Theory, methodology and practice of regional strategic planning. ru: INFRA-M Academic Publishing LLC., 2021. http://dx.doi.org/10.12737/1738755.

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In the monograph, the region is presented as a complex, multilevel socio-economic system consisting of many heterogeneous, interacting economic entities of different levels (economic agents and markets, management, resources and economic processes), jointly organizing reproduction processes embedded in the economic space of the national economy on the local territory. Currently, the role of rational management of the socio-economic development of the region is increasing. In such conditions, it is advisable to use strategic planning, which, in turn, has increasingly been carried out using a simulation model. The simulation model in regional strategic planning allows government agencies to predict their activities in the presence of various controlled and uncontrolled factors of the external and internal environment. In this study, the list of principles of strategic planning focused on the processes of strategic planning of the region using the method of simulation modeling is supplemented. A methodology for organizing strategic planning processes at the meso-level using simulation modeling technology is proposed. For a wide range of readers interested in the problems of regional strategic planning.

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Programming Heterogeneous Mpsocs. Springer International Publishing AG, 2013.

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Частини книг з теми "Heterogeneous embedded systems"

Baruah, Sanjoy, Marko Bertogna, and Giorgio Buttazzo. "Real-time Scheduling upon Heterogeneous Multiprocessors." In Embedded Systems, 205–11. Cham: Springer International Publishing, 2015. http://dx.doi.org/10.1007/978-3-319-08696-5_22.

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Rutzig, Mateus Beck, Antonio Carlos Schneider Beck, and Luigi Carro. "Heterogeneous Behavior of Applications and Systems." In Adaptable Embedded Systems, 13–39. New York, NY: Springer New York, 2012. http://dx.doi.org/10.1007/978-1-4614-1746-0_2.

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Alexander, Perry, and Cindy Kong. "Heterogeneous Modeling Support for Embedded Systems Design." In Embedded Software, 1–13. Berlin, Heidelberg: Springer Berlin Heidelberg, 2001. http://dx.doi.org/10.1007/3-540-45449-7_1.

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Kriebel, Florian, Faiq Khalid, Bharath Srinivas Prabakaran, Semeen Rehman, and Muhammad Shafique. "Fault-Tolerant Computing with Heterogeneous Hardening Modes." In Dependable Embedded Systems, 161–80. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-52017-5_7.

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AbstractFault-tolerance using (full-scale) redundancy-based techniques has been employed to detect and correct reliability errors (i.e., soft errors), but they pose significant area and power overhead. On the other hand, due to the masking and the error tolerance properties at different system layers and of different applications, respectively, reliable heterogeneous architectures have been emerged as an attractive design choice for power-efficient dependable computing platforms. This chapter discusses the building blocks of such computing systems, based on both embedded and superscalar processors, with different reliability (fault-tolerant) modes at the architecture layer to memories like caches, for heterogeneous in-order and out-of-order processors. We provide a comprehensive reliability, i.e., soft error, vulnerability analysis of different components in in-order and out-of-order processors, e.g., caches. We also discuss different methodologies to improve the performance and power of such a system by analyzing these vulnerabilities. Moreover, we show how such heterogeneous hardware-level hardening modes can further be complemented by software-level techniques that can be realized using a reliability-driven compiler (as introduced in Chapter “Dependable Software Generation and Execution on Embedded Systems”).

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Gosselin, Benoit, and Mohamad Sawan. "Embedded Medical Microsystems." In Design Technology for Heterogeneous Embedded Systems, 365–87. Dordrecht: Springer Netherlands, 2012. http://dx.doi.org/10.1007/978-94-007-1125-9_17.

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Benveniste, Albert, Luca P. Carloni, Paul Caspi, and Alberto L. Sangiovanni-Vincentelli. "Heterogeneous Reactive Systems Modeling and Correct-by-Construction Deployment." In Embedded Software, 35–50. Berlin, Heidelberg: Springer Berlin Heidelberg, 2003. http://dx.doi.org/10.1007/978-3-540-45212-6_4.

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Ren, XuePing, Jian Wan, and GuangHuan Hu. "A Novel Task Scheduling for Heterogeneous Systems." In Embedded Software and Systems, 400–405. Berlin, Heidelberg: Springer Berlin Heidelberg, 2005. http://dx.doi.org/10.1007/11535409_57.

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Leduc, Yves, and Nathalie Messina. "Executable Specifications for Heterogeneous Embedded Systems." In Design Technology for Heterogeneous Embedded Systems, 41–61. Dordrecht: Springer Netherlands, 2012. http://dx.doi.org/10.1007/978-94-007-1125-9_3.

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Radojevic, Ivan, and Zoran Salcic. "Heterogeneous Reactive Architectures of Embedded Systems." In Embedded Systems Design Based on Formal Models of Computation, 125–41. Dordrecht: Springer Netherlands, 2011. http://dx.doi.org/10.1007/978-94-007-1594-3_7.

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Uchiyama, Kunio, Fumio Arakawa, Hironori Kasahara, Tohru Nojiri, Hideyuki Noda, Yasuhiro Tawara, Akio Idehara, Kenichi Iwata, and Hiroaki Shikano. "Heterogeneous Multicore Architecture." In Heterogeneous Multicore Processor Technologies for Embedded Systems, 11–18. New York, NY: Springer New York, 2012. http://dx.doi.org/10.1007/978-1-4614-0284-8_2.

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Тези доповідей конференцій з теми "Heterogeneous embedded systems"

Vachoux, Alain, and Torsten Maehne. "SystemC-based modeling of embedded heterogeneous systems." In 2008 Joint International IEEE Northeast Workshop on Circuits and Systems (NEWCAS) and TAISA Conference (NEWCAS-TAISA). IEEE, 2008. http://dx.doi.org/10.1109/newcas.2008.4606375.

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Avissar, Oren, Rajeev Barua, and Dave Stewart. "Heterogeneous memory management for embedded systems." In the international conference. New York, New York, USA: ACM Press, 2001. http://dx.doi.org/10.1145/502217.502223.

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Kumar, R., and B. H. Krogh. "Heterogeneous verification of embedded control systems." In 2006 American Control Conference. IEEE, 2006. http://dx.doi.org/10.1109/acc.2006.1657445.

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Charulatha, B. S., Paul Rodrigues, T. Chitralekha, and Arun Rajaraman. "Heterogeneous clustering." In 2014 International Conference on Information Communication and Embedded Systems (ICICES). IEEE, 2014. http://dx.doi.org/10.1109/icices.2014.7033890.

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Tumeo, Antonino, Marco Branca, Lorenzo Camerini, Christian Pilato, Pier Luca Lanzi, Fabrizio Ferrandi, and Donatella Sciuto. "Mapping pipelined applications onto heterogeneous embedded systems." In the 7th IEEE/ACM international conference. New York, New York, USA: ACM Press, 2009. http://dx.doi.org/10.1145/1629435.1629495.

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Agbaria, A., Dong-In Kang, and K. Singh. "LMPI: MPI for heterogeneous embedded distributed systems." In 12th International Conference on Parallel and Distributed Systems - (ICPADS'06). IEEE, 2006. http://dx.doi.org/10.1109/icpads.2006.56.

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Ivutin, Alexey N., Anna G. Voloshko, and Alexander S. Novikov. "Optimization Problem for Heterogeneous Computing Systems." In 2020 9th Mediterranean Conference on Embedded Computing (MECO). IEEE, 2020. http://dx.doi.org/10.1109/meco49872.2020.9134172.

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Plumbridge, Gary, and Neil Audsley. "Extending Java for heterogeneous embedded system description." In 2011 6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC). IEEE, 2011. http://dx.doi.org/10.1109/recosoc.2011.5981527.

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Manor, Erez, and Shlomo Greenberg. "Efficient Hardware/Software partitioning for Heterogeneous Embedded Systems." In 2018 IEEE International Conference on the Science of Electrical Engineering in Israel (ICSEE). IEEE, 2018. http://dx.doi.org/10.1109/icsee.2018.8646107.

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Fan, Yang-Hsin, Jan-Ou Wu, and San-Fu Wang. "Software synthesis of middleware for heterogeneous embedded systems." In 2012 2nd International Conference on Consumer Electronics, Communications and Networks (CECNet). IEEE, 2012. http://dx.doi.org/10.1109/cecnet.2012.6201427.

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Звіти організацій з теми "Heterogeneous embedded systems"

Venkataramana, Raju D. Adaptive Framework for Automated Mapping and Architecture Trades for Embedded Heterogeneous Systems. Fort Belvoir, VA: Defense Technical Information Center, May 2003. http://dx.doi.org/10.21236/ada419986.

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Russo, David, Daniel M. Tartakovsky, and Shlomo P. Neuman. Development of Predictive Tools for Contaminant Transport through Variably-Saturated Heterogeneous Composite Porous Formations. United States Department of Agriculture, December 2012. http://dx.doi.org/10.32747/2012.7592658.bard.

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The vadose (unsaturated) zone forms a major hydrologic link between the ground surface and underlying aquifers. To understand properly its role in protecting groundwater from near surface sources of contamination, one must be able to analyze quantitatively water flow and contaminant transport in variably saturated subsurface environments that are highly heterogeneous, often consisting of multiple geologic units and/or high and/or low permeability inclusions. The specific objectives of this research were: (i) to develop efficient and accurate tools for probabilistic delineation of dominant geologic features comprising the vadose zone; (ii) to develop a complementary set of data analysis tools for discerning the fractal properties of hydraulic and transport parameters of highly heterogeneous vadose zone; (iii) to develop and test the associated computational methods for probabilistic analysis of flow and transport in highly heterogeneous subsurface environments; and (iv) to apply the computational framework to design an “optimal” observation network for monitoring and forecasting the fate and migration of contaminant plumes originating from agricultural activities. During the course of the project, we modified the third objective to include additional computational method, based on the notion that the heterogeneous formation can be considered as a mixture of populations of differing spatial structures. Regarding uncertainly analysis, going beyond approaches based on mean and variance of system states, we succeeded to develop probability density function (PDF) solutions enabling one to evaluate probabilities of rare events, required for probabilistic risk assessment. In addition, we developed reduced complexity models for the probabilistic forecasting of infiltration rates in heterogeneous soils during surface runoff and/or flooding events Regarding flow and transport in variably saturated, spatially heterogeneous formations associated with fine- and coarse-textured embedded soils (FTES- and CTES-formations, respectively).We succeeded to develop first-order and numerical frameworks for flow and transport in three-dimensional (3-D), variably saturated, bimodal, heterogeneous formations, with single and dual porosity, respectively. Regarding the sampling problem defined as, how many sampling points are needed, and where to locate them spatially in the horizontal x₂x₃ plane of the field. Based on our computational framework, we succeeded to develop and demonstrate a methdology that might improve considerably our ability to describe quntitaively the response of complicated 3-D flow systems. The results of the project are of theoretical and practical importance; they provided a rigorous framework to modeling water flow and solute transport in a realistic, highly heterogeneous, composite flow system with uncertain properties under-specified by data. Specifically, they: (i) enhanced fundamental understanding of the basic mechanisms of field-scale flow and transport in near-surface geological formations under realistic flow scenarios, (ii) provided a means to assess the ability of existing flow and transport models to handle realistic flow conditions, and (iii) provided a means to assess quantitatively the threats posed to groundwater by contamination from agricultural sources.

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Dafflon, Baptiste, S. Wielandt, S. Uhlemann, Haruko Wainwright, K. Bennett, Jitendra Kumar, Sebastien Biraud, Susan Hubbard, and Stan Wullschleger. Revolutionizing observations and predictability of Arctic system dynamics through next-generation dense, heterogeneous and intelligent wireless sensor networks with embedded AI. Office of Scientific and Technical Information (OSTI), April 2021. http://dx.doi.org/10.2172/1769774.

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