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Автор: Grafiati
Опубліковано: 11 вересня 2023

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Статті в журналах з теми "GENERATING CIRCUITS"

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Materzok, Marek. "Generating circuits with generators." Proceedings of the ACM on Programming Languages 6, ICFP (August 29, 2022): 52–79. http://dx.doi.org/10.1145/3549821.

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The most widely used languages and methods used for designing digital hardware fall into two rough categories. One of them, register transfer level (RTL), requires specifying each and every component in the designed circuit. This gives the designer full control, but burdens the designer with many trivial details. The other, the high-level synthesis (HLS) method, allows the designer to abstract the details of hardware away and focus on the problem being solved. This method however cannot be used for a class of hardware design problems because the circuit's clock is also abstracted away. We present YieldFSM, a hardware description language that uses the generator abstraction to represent clock-level timing in a digital circuit. It represents a middle ground between the RTL and HLS approaches: the abstraction level is higher than in RTL, but thanks to explicit information about clock-level timing, it can be used in applications where RTL is traditionally used. We also present the YieldFSM compiler, which uses methods developed by the functional programming community -- including continuation-passsing style translation and defunctionalization -- to translate YieldFSM programs to Mealy machines. It is implemented using Template Haskell and the Clash functional hardware description language. We show that this approach leads to short and conceptually simple hardware descriptions.
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Briggman, K. L., and W. B. Kristan. "Multifunctional Pattern-Generating Circuits." Annual Review of Neuroscience 31, no. 1 (July 2008): 271–94. http://dx.doi.org/10.1146/annurev.neuro.31.060407.125552.

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Brodovskaya, Anastasia, and Jaideep Kapur. "Circuits generating secondarily generalized seizures." Epilepsy & Behavior 101 (December 2019): 106474. http://dx.doi.org/10.1016/j.yebeh.2019.106474.

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Kosarev, Boris. "FERRORESONANT PROCESSES IN POWER SUPPLY SYSTEMS WITH DISTRIBUTED GENERATION." Electrical and data processing facilities and systems 18, no. 3-4 (2022): 56–64. http://dx.doi.org/10.17122/1999-5458-2022-18-3-4-56-64.

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Relevance The article is devoted to the study of the possibility of occurrence of ferroresonant processes in power supply systems with distributed generation. Ferroresonant processes cause overvoltages in electrical installations and lead to their failure. In backbone and distribution networks without distributed generation facilities, the phenomenon of ferroresonance has been studied quite deeply, effective hardware and operational measures have been developed to prevent the occurrence of ferroresonance surges in electrical installations. However, the issue of the occurrence of ferroresonant processes in power supply systems with distributed generation, which is a promising direction in the development of the energy sector, seems to be little studied. Aim of research The main aim of the research is to investigate circuit-mode conditions for the occurrence of ferroresonant processes in power supply systems with distributed generation. Research methods To study the circuit-mode conditions for the occurrence of ferroresonant processes in power supply systems with distributed generation, the main provisions of the theory of electrical complexes and systems, the theory of nonlinear electrical circuits, and the principles of controlling objects of electrical complexes and industrial systems were used. Results The circuit-mode conditions for the occurrence of ferroresonant processes in power supply systems with distributed generation are studied. The power supply system of a HF radio center, containing a power plant with a lower installed power or corresponding to the maximum power consumption of the load, was chosen as the object of study. The features of the scheme-mode conditions for the occurrence of ferroresonant processes under conditions of distributed generation are as follows. Due to the insignificant remoteness of distributed generation facilities and consumers, additional opportunities arise for subharmonic ferroresonant processes. When a generating plant is connected to low-voltage busbars, conditions are created for the occurrence of a ferroresonant process involving low-voltage windings of power transformers. The low dynamic stability of generating installations of distributed generation facilities based on synchronous generators reduces the likelihood and duration of ferroresonant processes in the event of phase wire breaks and short circuits on the power line. Generating plants connected via grid inverters have a limited output current and can be turned off by emergency automatics in the event of an emergency operation of the grid, which, as a rule, precedes the appearance of ferroresonant overvoltages in electrical installations. Thus, in power districts with distributed generation facilities, the circuit-mode conditions for the occurrence of ferroresonant processes, known in the centralized power supply system, undergo changes, and it is also possible to form new ferroresonant oscillatory circuits. Keywords: distributed generation, ferroresonant process, power supply system, oscillatory circuit, generating plant, relay protection and automation devices Acknoledgements: The work was carried out under the state order of the Omsk Scientific Center of the Siberian Branch of the Russian Academy of Sciences (project state registration number 122011200349-3).
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SOLIMAN, AHMED M. "GENERATION OF THIRD-ORDER QUADRATURE OSCILLATOR CIRCUITS USING NAM EXPANSION." Journal of Circuits, Systems and Computers 22, no. 07 (August 2013): 1350060. http://dx.doi.org/10.1142/s0218126613500606.

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A systematic synthesis procedure for generating third-order grounded passive element quadrature oscillators is given. The synthesis procedure is based on using nodal admittance matrix (NAM) expansion applied to the Y matrix of a recently reported three Op Amp third-order oscillator circuit. Four new circuits using current conveyors (CCII) are reported. In addition four more new circuits using inverting current conveyors (ICCII) are also given. Many more quadrature third-order oscillator circuits using combinations of CCII and ICCII can be obtained. Simulation results demonstrating the practicality of one of the generated circuits are included.
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GÜNAY, ENIS, and MUSTAFA ALÇI. "n-DOUBLE SCROLLS IN SC-CNN CIRCUIT VIA DIODE-BASED PWL FUNCTION." International Journal of Bifurcation and Chaos 16, no. 04 (April 2006): 1023–33. http://dx.doi.org/10.1142/s0218127406015271.

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In this paper n-double scroll generating via diode-based PieceWise-Linear (PWL) circuit in State Controlled Cellular Neural Network (SC-CNN) is presented. It has been shown that by using simple diode-based configurations; alternative nonlinear circuit configurations for chaotic circuits and PWL-based systems can be used in the generation of n-double scrolls. With this study, while the analysis of the nonlinear block in the SC-CNN-based circuit is simplified, the implementation cost of the circuit is also reduced. Pspice simulations are proved with experimental studies.
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7

Weikle, R. M., T. W. Crowe, and E. L. Kollberg. "Multiplier and Harmonic Generator Technologies for Terahertz Applications." International Journal of High Speed Electronics and Systems 13, no. 02 (June 2003): 429–56. http://dx.doi.org/10.1142/s012915640300179x.

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Harmonic generation based on frequency multipliers has proven to be the most successful and widely used solid-state technology for generating power at submillimeter wavelengths. Over the last several years, the development of new device technologies, implementation of innovative circuits, and application of advanced integrated-circuit processing techniques to frequency multiplier design have resulted in unprecedented levels of performance throughout the submillimeter-wave frequency band. This paper reviews the technological innovations, device options, circuit architectures, and fabrication technologies that have made harmonic generation such a successful approach to source development in the submillimeter spectrum.
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8

Kim, Junyeong, and Jin Jang. "P‐2: Narrow Bezel Gate Driver Generating Positive Pulse for AMOLED Display Using LTPO Technology with Depletion Mode Oxide TFTs." SID Symposium Digest of Technical Papers 54, no. 1 (June 2023): 1782–85. http://dx.doi.org/10.1002/sdtp.16950.

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We propose a novel gate driver generating positive pulse for oxide switching TFTs in AMOLED pixel circuits using low‐temperature polycrystalline silicon and oxide (LTPO) thin‐film transistors (TFTs). The proposed gate driver circuit has only five TFTs without capacitor. The proposed circuits can operate perfectly when all oxide TFTs in the circuits have threshold voltage (VTH) of ‐3.5V, depletion mode. The circuit can be easily designed for narrow bezel due to simple structures. The one stage of the circuit was designed with the size of 50 μm × 100 μm. The fabricated circuit works well with the depletion mode oxide TFTs with VTH of ‐3.5V. The circuit operated at the pulse width of 1 μs, corresponding to operating speed of 500 kHz. The proposed gate driver can be applicable for narrow bezel AMOLED display.
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CAFAGNA, DONATO, and GIUSEPPE GRASSI. "NEW 3D-SCROLL ATTRACTORS IN HYPERCHAOTIC CHUA'S CIRCUITS FORMING A RING." International Journal of Bifurcation and Chaos 13, no. 10 (October 2003): 2889–903. http://dx.doi.org/10.1142/s0218127403008284.

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This paper presents an approach for generating new hyperchaotic attractors in a ring of Chua's circuits. By taking a closed chain of three circuits and exploiting sine functions as nonlinearities, the proposed technique enables 3D-scroll attractors to be generated. In particular, the paper shows that 3D-scroll dynamics can be designed by modifying six parameters related to the circuit nonlinearities.
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Zeng, Xian Tao, and Qian Hua Ren. "Power Generation System by Vehicle on the Downhill of Expressway." Advanced Materials Research 724-725 (August 2013): 1361–65. http://dx.doi.org/10.4028/www.scientific.net/amr.724-725.1361.

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In this paper, a method of magnetoelectricity power generation system for vehicle on the downhill of expressways is proposed. This system is a clean energy system that can be reused. Its structure includes car magnetic poles, magnetic poles imbedded in road surface, closed circuit imbedded in road surface, rectifier, inverter and storage battery. Multi-unit magnetic poles and closed circuits imbedded in the road surface are used in this invention, so when the car poles move with the running down of cars on downhill, magnetic flow in closed circuits will change to produce a technique of group control power generation. From the simulated system in the test, it can be seen that it is efficient and effective in generating power.
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Дисертації з теми "GENERATING CIRCUITS"

1

Sheikhbahaei, Shahriar. "Astroglial control of respiratory rhythm generating circuits." Thesis, University College London (University of London), 2017. http://discovery.ucl.ac.uk/10037956/.

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Astrocytes, the most numerous glial cells of the central nervous system, are well known to provide neuronal circuits with essential structural and metabolic support. There is also evidence that astrocytes may modulate the activities of neuronal circuits controlling motor rhythms including those of the brainstem’s preBötzinger complex (preBötC) that generates the rhythm of breathing in mammals. However, the extent and mechanisms of active astroglial control of the respiratory rhythm-generating circuits remain unknown. The morphological features of astrocytes in this critical brainstem region are also unknown. In this dissertation, viral gene transfer approaches designed to block or activate astroglial signaling pathways were used to determine the role of preBötC astrocytes in the control of breathing using in vitro and in vivo experimental models. Computer-aided morphometric analyses were used to investigate the structural features of brainstem astrocytes potentially contributing to their functional role. The results from these complementary, multi-faceted experiments show that (i) morphologically, preBötC astrocytes are larger, have more branches, and longer processes when compared to astrocytes residing in other regions of the brainstem; (ii) in conscious adult rats, blockade of vesicular release mechanisms or ATP-mediated signaling in preBötC astrocytes by virally-induced bilateral expression of either the light chain of tetanus toxin (TeLC), the dominant-negative SNARE proteins (dnSNARE), or a potent ectonucleotidase – transmembrane prostatic acid phosphatase – results in a significant reduction of resting respiratory frequency and frequency of sighs, augmented breaths that engage preBötC circuits to increase inspiratory effort; (iii) hypoxic- and CO2-induced ventilatory responses are significantly reduced when vesicular release mechanisms in preBötC astrocytes are blocked; (iv) activation of preBötC astrocytes expressing Gq-coupled Designer Receptor Exclusively Activated by Designer Drug is associated with higher frequency of both normal inspirations and sighs; (v) blockade of vesicular release mechanisms (expression of TeLC or dnSNARE) in preBötC astrocytes is associated with a dramatic reduction of exercise capacity. These data suggest that astroglial mechanisms involving exocytotic vesicular release of signaling molecules (gliotransmitters), provides tonic excitatory drive to the inspiratory rhythm-generating circuits of the preBötC and contributes to the generation of sighs. The role of preBötC astrocytes in central nervous mechanisms controlling breathing becomes especially important in conditions of metabolic stress requiring homeostatic adjustments of breathing such as systemic hypoxia, hypercapnia, and exercise, when enhanced respiratory efforts are critical to support physiological and behavioral demands of the body.
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Wang, Jianwei. "Generating, manipulating, distributing and analysing light's quantum states using integrated photonic circuits." Thesis, University of Bristol, 2015. https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.702227.

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The emergence of integrated quantum photonics is revolutionising the field of photonic quantum information science and technology. Quantum photonic waveguide platforms, capable of integrating single photon sources, quantum optical circuits and single photon detectors on semiconductor chips by exploring mature micro- or nano-fabrication technology, greatly promise unprecedented complexity, miniaturisation, scalability and robustness for advanced quantum information applications, including quantum communication, sensing, simulation, machine learning and computing. This thesis is to continually enlarge the scope of integrated quantum photonics technology by developing new materials, devices and systems for new functionalities including generation, manipulation, transmission, distribution, interconversion and measurement of photonic quantum states. Gallium arsenide waveguide quantum circuits are first developed to manipulate photons, demonstrating two-photon quantum interference in integrated beamsplitters and manipulation of photon number entanglement in optical interferometers utilising the linear electro-optic effect of gallium arsenide. We also demonstrate a chip-to-chip quantum photonic interconnect, by demonstrating high-fidelity entanglement generation, manipulation, transmission, distribution and measurement across two separate integrated silicon quantum photonic chips. A highfidelity interconversion of path and polarisation encoding preserves coherence across the full interconnected chip-to-chip system. This would allows quantum information encoding, processing and analysing on chips and quantum information transmission and distribution across chips, towards the multi-chip and multi-core quantum systems. We report on-chip generation of high-purity orbital angular momentum states and the fast-speed reconfigurability and switch-ability using an ultra-compact integrated silicon microring resonator embedded with angular diffractive gratings. Quantitive and qualitative measurements are performed to analyse the orbital angular momentum states from the chip. This might allow a high-capacity quantum interconnectivity of free space and integrated quantum circuits for many quantum information prototypes. This thesis demonstrates the capabilities of on-chip encoding, controlling, transferring and analysing quantum states in photon's path, polarisation and spatial modes degrees of freedom, providing a new generation of integrated quantum photonics toolbox for future quantum information technology.
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McKnight, Walter Lee. "A meta system for generating software engineering environments /." The Ohio State University, 1985. http://rave.ohiolink.edu/etdc/view?acc_num=osu1487260531958418.

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Ferraz, Rafael da Silva. "Dispositivo para medição de impedância em sistemas de aterramento elétricos em alta frequência." Universidade Federal de Goiás, 2016. http://repositorio.bc.ufg.br/tede/handle/tede/6615.

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Coordenação de Aperfeiçoamento de Pessoal de Nível Superior - CAPES
This work presents the project and the implementation of a device that is capable of measuring the electrical effects, especially the impedance, in grounding meshes when subjected to atmospherical discharges. An analysis on the influence of the atmospheric discharges in electrical protection systems is performed and also a comparison between current and voltage impulsive circuits. The device is built of electronic circuits controlled by a microcontroller, with the possibility of parameter adjusting for shaping the generated impulse wave. The device was conceived such that it can be used for tests of soil impedance measurement and for verification of the behavior of electrical grounding systems under high frequencies. The results are presented for tests in different types of systems and there was satisfactory performance for the developed equipment when compared with a commercial device
Este trabalho apresenta o projeto e a implementação do dispositivo capaz de medir os efeitos elétricos, em especial, as impedâncias, em malha de aterramento, sujeito a descargas atmosféricas. Analisa-se as influências das descargas atmosféricas nos sistemas de proteção elétricos e desenvolve-se análise comparativa dos circuitos impulsivos de corrente e de tensão. Constrói-se o dispositivo que consiste de circuitos eletrônicos controlados por microcontrolador, com possibilidade de ajuste de parâmetros da onda gerada. O dispositivo produzido é utilizado para medição da impedância do solo e verificação do comportamento de sistemas de aterramento elétrico em baixas e altas frequências. São apresentados os resultados dos testes em diferentes tipos de sistemas, demonstrando o satisfatório desempenho quando comparado com instrumento comercial.
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Krishnamurthy, Smitha. "SOLAR AND FUEL CELL CIRCUIT MODELING, ANALYSIS AND INTEGRATIONS WITH POWER CONVERSION CIRCUITS FOR DISTRIBUTED GENERATION." Master's thesis, University of Central Florida, 2009. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/3501.

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Renewable energy is considered to be one of the most promising alternatives for the growing energy demand in response to depletion of fossil fuels and undesired global warming issue. With such perspective, Solar Cells and Fuel Cells are most viable, environmentally sound, and sustainable energy sources for power generation. Solar and Fuel cells have created great interests in modern applications including distributed energy generation to provide clean energy. The purpose of this thesis was to perform a detailed analysis and modeling of Solar and Fuel cells using Cadence SPICE, and to investigate dynamic interactions between the modules and power conversion circuits. Equivalent electronic static and dynamic models for Solar and Fuel Cells, their electrical characteristics, and typical power loss mechanisms associated with them are demonstrated with simulation results. Power conversion circuits for integration with the dynamic models of these renewable low voltage sources are specifically chosen to boost and regulate the input low dc voltage from the modules. The scope of this work was to analyze and model solar and fuel cells to study their terminal characteristics, power loss mechanisms, modules and their dynamics when interfaced with power converters, which would lead to better understanding of these renewable sources in power applications.
M.S.
School of Electrical Engineering and Computer Science
Engineering and Computer Science
Electrical Engineering MSEE
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Bollinger, S. Wayne. "Hierarchical test generation for CMOS circuits." Diss., This resource online, 1992. http://scholar.lib.vt.edu/theses/available/etd-07282008-134708/.

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Lee, Kyung Tek. "Crosstalk fault test generation and hierarchical timing verification in VLSI digital circuits /." Digital version accessible at:, 1999. http://wwwlib.umi.com/cr/utexas/main.

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Lazzari, Cristiano. "Transistor level automatic generation of radiation-hardened circuits." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2007. http://hdl.handle.net/10183/15506.

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Tecnologias submicrônicas (DSM) têm inserido novos desafios ao projeto de circuitos devido a redução de geometrias, redução na tensão de alimentação, aumento da freqüência e aumento da densidade de lógica. Estas características reduzem significativamente a confiabilidade dos circuitos integrados devido a suscetibilidade a efeitos como crosstalk e acoplamento de substrato. Ainda, os efeitos da radiação são mais significantes devido as partículas com baixa energia começam a ser um problema em tecnologias DSM. Todas essas características enfatizam a necessidade de novas ferramentas de automação. Um dos objetivos desta tese é desenvolver novas ferramentas aptas a lidar com estes desafios. Esta tese é dividida em duas grandes contribuições. A primeira está relacionada com o desenvolvimento de uma nova metodologia com o objetivo de gerar circuitos otimizados em respeito ao atraso e ao consumo de potência. Um novo fluxo de projeto é apresentado na qual o circuito é otimizado no nível de transistor. Esta metodologia permite otimizar cada transistor de acordo com as capacitâncias associadas. Diferente da metodologia tradicional, o leiaute é gerado sob demanda depois do processo de otimização de transistores. Resultados mostram melhora de 11% em relação ao atraso dos circuitos e 30% de redução no consumo de potência em comparação à metodologia tradicional. A segunda contribuição está relacionada com o desenvolvimento de técnicas de geração de circuitos tolerantes a radiação. Uma técnica CWSP é usada para aplicar redundância temporal em elementos seqüenciais. Esta técnica apresenta baixa utilização de área, mas as penalidades no atraso estão totalmente relacionadas com a duração do pulso que se planeja atenuar. Além disso, uma nova metodologia de dimensionamento de transistores para falhas transientes é apresentada. A metodologia de dimensionamento é baseada em um modelo analítico. O modelo considera independente blocos de transistores PMOS e NMOS. Então, somente transistores diretamente relacionados à atenuação são dimensionados. Resultados mostram área, atraso e consumo de potência reduzido em comparação com as técnicas CWSP e TMR, permitindo o desenvolvimento de circuitos com alta freqüência.
Deep submicron (DSM) technologies have increased the challenges in circuit designs due to geometry shrinking, power supply reduction, frequency increasing and high logic density. The reliability of integrated circuits is significantly reduced as a consequence of the susceptibility to crosstalk and substrate coupling. In addition, radiation effects are also more significant because particles with low energy, without importance in older technologies, start to be a problem in DSM technologies. All these characteristics emphasize the need for new Electronic Design Automation (EDA) tools. One of the goals of this thesis is to develop EDA tools able to cope with these DSM challenges. This thesis is divided in two major contributions. The first contribution is related to the development of a new methodology able to generate optimized circuits in respect to timing and power consumption. A new design flow is proposed in which the circuit is optimized at transistor level. This methodology allows the optimization of every single transistor according to the capacitances associated to it. Different from the traditional standard cell approach, the layout is generated on demand after a transistor level optimization process. Results show an average 11% delay improvement and more than 30% power saving in comparison with the traditional design flow. The second contribution of this thesis is related with the development of techniques for radiation-hardened circuits. The Code Word State Preserving (CWSP) technique is used to apply timing redundancy into latches and flipflops. This technique presents low area overhead, but timing penalties are totally related with the glitch duration is being attenuated. Further, a new transistor sizing methodology for Single Event Transient (SET) attenuation is proposed. The sizing method is based on an analytic model. The model considers independently pull-up and pull-down blocks. Thus, only transistors directly related to the SET attenuation are sized. Results show smaller area, timing and power consumption overhead in comparison with TMR and CWSP techniques allowing the development of high frequency circuits, with lower area and power overhead.
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Hutton, Michael D. "Characterization and parameterized generation of digital circuits." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1997. http://www.collectionscanada.ca/obj/s4/f2/dsk2/tape16/PQDD_0021/NQ27666.pdf.

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Vasudevan, Dilip Prasad. "Automatic test pattern generation for asynchronous circuits." Thesis, University of Edinburgh, 2012. http://hdl.handle.net/1842/7670.

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The testability of integrated circuits becomes worse with transistor dimensions reaching nanometer scales. Testing, the process of ensuring that circuits are fabricated without defects, becomes inevitably part of the design process; a technique called design for test (DFT). Asynchronous circuits have a number of desirable properties making them suitable for the challenges posed by modern technologies, but are severely limited by the unavailability of EDA tools for DFT and automatic test-pattern generation (ATPG). This thesis is motivated towards developing test generation methodologies for asynchronous circuits. In total four methods were developed which are aimed at two different fault models: stuck-at faults at the basic logic gate level and transistor-level faults. The methods were evaluated using a set of benchmark circuits and compared favorably to previously published work. First, ABALLAST is a partial-scan DFT method adapting the well-known BALLAST technique for asynchronous circuits where balanced structures are used to guide the selection of the state-holding elements that will be scanned. The test inputs are automatically provided by a novel test pattern generator, which uses time frame unrolling to deal with the remaining, non-scanned sequential C-elements. The second method, called AGLOB, uses algorithms from strongly-connected components in graph graph theory as a method for finding the optimal position of breaking the loops in the asynchronous circuit and adding scan registers. The corresponding ATPG method converts cyclic circuits into acyclic for which standard tools can provide test patterns. These patterns are then automatically converted for use in the original cyclic circuits. The third method, ASCP, employs a new cycle enumeration method to find the loops present in a circuit. Enumerated cycles are then processed using an efficient set covering heuristic to select the scan elements for the circuit to be tested.Applying these methods to the benchmark circuits shows an improvement in fault coverage compared to previous work, which, for some circuits, was substantial. As no single method consistently outperforms the others in all benchmarks, they are all valuable as a designer’s suite of tools for testing. Moreover, since they are all scan-based, they are compatible and thus can be simultaneously used in different parts of a larger circuit. In the final method, ATRANTE, the main motivation of developing ATPG is supplemented by transistor level test generation. It is developed for asynchronous circuits designed using a State Transition Graph (STG) as their specification. The transistor-level circuit faults are efficiently mapped onto faults that modify the original STG. For each potential STG fault, the ATPG tool provides a sequence of test vectors that expose the difference in behavior to the output ports. The fault coverage obtained was 52-72 % higher than the coverage obtained using the gate level tests. Overall, four different design for test (DFT) methods for automatic test pattern generation (ATPG) for asynchronous circuits at both gate and transistor level were introduced in this thesis. A circuit extraction method for representing the asynchronous circuits at a higher level of abstraction was also implemented. Developing new methods for the test generation of asynchronous circuits in this thesis facilitates the test generation for asynchronous designs using the CAD tools available for testing the synchronous designs. Lessons learned and the research questions raised due to this work will impact the future work to probe the possibilities of developing robust CAD tools for testing the future asynchronous designs.
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Книги з теми "GENERATING CIRCUITS"

1

Martins, Ricardo M. F. Generating Analog IC Layouts with LAYGEN II. Berlin, Heidelberg: Springer Berlin Heidelberg, 2013.

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2

Givon, Lev E. An Open Pipeline for Generating Executable Neural Circuits from Fruit Fly Brain Data. [New York, N.Y.?]: [publisher not identified], 2016.

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3

Model engineering in mixed-signal circuit design: A guide to generating accurate behavioral models in VHDL-AMS. Boston: Kluwer Academic Publishers, 2001.

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4

Zeljko, Zilic, and SpringerLink (Online service), eds. Generating Hardware Assertion Checkers: For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line Monitoring. Dordrecht: Springer Science + Business Media B.V, 2008.

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5

Bobyr', Maksim, Vitaliy Titov, and Vladimir Ivanov. Design of analog and digital devices. ru: INFRA-M Academic Publishing LLC., 2020. http://dx.doi.org/10.12737/1070341.

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Анотація:
The textbook contains the material necessary for the formation of students ' knowledge of the basics of analog and digital circuitry and the principles of building digital nodes, instilling skills in the development and design of digital devices, as well as performing practical work and a course project in the discipline "electrical Engineering, electronics and circuit engineering". Methods of calculation of analog circuits and synthesis of discrete devices of combinational type and automata with memory are considered. Examples of calculation of analog circuits and implementation of digital devices for various purposes on integrated circuits are given. Meets the requirements of Federal state educational standards of higher education of the latest generation. For students of higher education institutions studying in the field of training 09.03.01 "computer Science and engineering". It can be useful for students of the areas of training "Design and technology of electronic means", "Biotechnical systems and technologies"and" Information security".
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6

IEEE Power Engineering Society. Power Generation Committee., ed. IEEE recommended practice for the design of safety-related DC auxiliary power systems for nuclear power generating stations. New York, NY, USA: Institute of Electrical and Electronics Engineers, 1985.

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7

Lin, Chieh. Mixed-signal layout generation concepts. Boston: Kluwer Academic Publishers, 2003.

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8

Lin, Chieh. Mixed-signal layout generation concepts. Boston, MA: Kluwer Academic Publishers, 2004.

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9

Lampaert, Koen. Analog layout generation for performance and manufacturability. Boston: Kluwer Academic, 1999.

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10

Dhiman, Rohit. Nanoelectronics for Next-Generation Integrated Circuits. Boca Raton: CRC Press, 2022. http://dx.doi.org/10.1201/9781003155751.

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Частини книг з теми "GENERATING CIRCUITS"

1

Mellergaard, Niels, and Jørgen Staunstrup. "Generating Proof Obligations for Circuits." In Workshops in Computing, 185–200. London: Springer London, 1993. http://dx.doi.org/10.1007/978-1-4471-3558-6_11.

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2

Tanaka, Takushi. "Generating explanations from electronic circuits." In Lecture Notes in Computer Science, 739–48. Berlin, Heidelberg: Springer Berlin Heidelberg, 1998. http://dx.doi.org/10.1007/3-540-64582-9_806.

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3

Sheeran, Mary. "Generating Fast Multipliers Using Clever Circuits." In Formal Methods in Computer-Aided Design, 6–20. Berlin, Heidelberg: Springer Berlin Heidelberg, 2004. http://dx.doi.org/10.1007/978-3-540-30494-4_2.

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4

Stent, Gunther S. "Neural Circuits for Generating Rhythmic Movements." In Self-Organizing Systems, 245–63. Boston, MA: Springer US, 1987. http://dx.doi.org/10.1007/978-1-4613-0883-6_14.

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5

Valiron, Benoît. "Generating Reversible Circuits from Higher-Order Functional Programs." In Reversible Computation, 289–306. Cham: Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-40578-0_21.

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6

Li, Zhiqiang, Jiajia Hu, Xi Wu, Juan Dai, Wei Zhang, and Donghan Yang. "An Efficient Method for Generating Matrices of Quantum Logic Circuits." In Lecture Notes in Computer Science, 142–50. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-57884-8_13.

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7

Ali Taher, Murad Ahmed. "Algorithmic Method for Generating DC-DC Converter Circuits by Using Topological Matrix." In Communications in Computer and Information Science, 714–23. Berlin, Heidelberg: Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-22603-8_62.

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8

Goldberg, Eugene, and Panagiotis Manolios. "Generating High-Quality Tests for Boolean Circuits by Treating Tests as Proof Encoding." In Tests and Proofs, 101–16. Berlin, Heidelberg: Springer Berlin Heidelberg, 2010. http://dx.doi.org/10.1007/978-3-642-13977-2_10.

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9

Sziray, József. "Test Generation for Short-Circuit Faults in Digital Circuits." In Studies in Computational Intelligence, 313–19. Cham: Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-03206-1_21.

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10

Maheshwari, Sudhanshu. "Waveform generation circuits." In Analog Circuit Design using Current-Mode Techniques, 109–33. Boca Raton: CRC Press, 2023. http://dx.doi.org/10.1201/9781003403111-7.

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Тези доповідей конференцій з теми "GENERATING CIRCUITS"

1

Gaber, Lamya, Aziza I. Hussein, and Mohammed Moness. "Incremental Automatic Correction for Digital VLSI Circuits." In 10th International Conference on Advances in Computing and Information Technology (ACITY 2020). AIRCC Publishing Corporation, 2020. http://dx.doi.org/10.5121/csit.2020.101508.

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Анотація:
The impact of the recent exponential increase in complexity of digital VLSI circuits has heavily affected verification methodologies. Many advances toward verification and debugging techniques of digital VLSI circuits have relied on Computer Aided Design (CAD). Existing techniques are highly dependent on specialized test patterns with specific numbers increased by the rising complexity of VLSI circuits. A second problem arises in the form of large sizes of injecting circuits for correction and large number of SAT solver calls with a negative impact on the resultant running time. Three goals arise: first, diminishing dependence on a given test pattern by incrementally generating compact test patterns corresponding to design errors during the rectification process. Second, to reduce the size of in-circuit mutation circuit for error-fixing process. Finally, distribution of test patterns can be performed in parallel with a positive impact on digital VLSI circuits with large numbers of inputs and outputs. The experimental results illustrate that the proposed incremental correction algorithm can fix design bugs of type gate replacements in several digital VLSI circuits from ISCAS'85 with high speed and full accuracy. The speed of proposed Auto-correction mechanism outperforms the latest existing methods around 4.8x using ISCAS'85 benchmarks. The parallel distribution of test patterns on digital VLSI circuits during generating new compact test patterns achieves speed around 1.2x compared to latest methods.
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2

Tabei, Kaku, and Toshinori Yamada. "On generating test sets for reversible circuits." In Systems (ICCES). IEEE, 2009. http://dx.doi.org/10.1109/icces.2009.5383305.

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3

Dubrov, Denis, and Alexander Roshal. "Generating pipeline integrated circuits using C2HDL converter." In 2013 11th East-West Design and Test Symposium (EWDTS). IEEE, 2013. http://dx.doi.org/10.1109/ewdts.2013.6673108.

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4

Kiselyov, Oleg, Kedar N. Swadi, and Walid Taha. "A methodology for generating verified combinatorial circuits." In the fourth ACM international conference. New York, New York, USA: ACM Press, 2004. http://dx.doi.org/10.1145/1017753.1017794.

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5

Mutlu, Mustafa Umut, Ümit Hakan Yildiz, and Osman Akın. "Polymer nanofiber-carbon nanotube network generating circuits." In Organic Photonic Materials and Devices XX, edited by Christopher E. Tabor, François Kajzar, Toshikuni Kaino, and Yasuhiro Koike. SPIE, 2018. http://dx.doi.org/10.1117/12.2289085.

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6

S, Riju, and Soni Meera G. V. "High Speed Built in Self-Test via Pattern Generation." In The International Conference on scientific innovations in Science, Technology, and Management. International Journal of Advanced Trends in Engineering and Management, 2023. http://dx.doi.org/10.59544/lgqz5151/ngcesi23p122.

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This paper presents the built-in self-test (BIST) design of a C-testable high-speed carry-free divider which can be fully tested by 72 test patterns irrespective of the divider size. Using a graph labelling scheme, the test patterns, expected outputs, and control signals can be represented by sets of labels and generated by a simple circuitry. As a result, test patterns can be easily generated inside chips, responses to test patterns need not to be stored, and use of expensive test equipment is not necessary. Results show that the hardware cost for generating such labels is virtually constant irrespective of the circuit size. Dividing Circuits, Integrated Circuit Testing, Integrated Circuit Design, Design For Testability, Digital Arithmetic, Built In Self-Test, Graph Theory, Built In Self-Test Design, High Speed Carry Free Dividers, C Testable Circuits, Graph Labelling, Test Patterns, Control Signals, 64 Bit, Built In Self-Test, Circuit Testing, Automatic Testing, Test Pattern Generators, Hardware, Signal Generators, Test Equipment, Costs, Controllability, Observability, In Spartan3E FPGA device family, computation of 8-bit circular convolution using Modified Karatsuba Algorithm.
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7

Lee, David, and Jehoshua Bruck. "Generating probability distributions using multivalued stochastic relay circuits." In 2011 IEEE International Symposium on Information Theory - ISIT. IEEE, 2011. http://dx.doi.org/10.1109/isit.2011.6034134.

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8

Hernandez-Araya, Deykel, Jorge Castro-Godinez, Muhammad Shafique, and Jorg Henkel. "AUGER: A Tool for Generating Approximate Arithmetic Circuits." In 2020 IEEE 11th Latin American Symposium on Circuits & Systems (LASCAS). IEEE, 2020. http://dx.doi.org/10.1109/lascas45839.2020.9069045.

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9

Moussalli, Roger, Bharat Sukhwani, and Sameh Asaad. "FINPAGE: Generating high performance feed-specific parser circuits." In 2013 IEEE Global Conference on Signal and Information Processing (GlobalSIP). IEEE, 2013. http://dx.doi.org/10.1109/globalsip.2013.6737095.

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10

Weingarten, K. J., M. J. W. Rodwell, J. L. Freeman, S. K. Diamond, and D. M. Bloom. "Electrooptic Sampling of GaAs Integrated Circuits." In International Conference on Ultrafast Phenomena. Washington, D.C.: Optica Publishing Group, 1986. http://dx.doi.org/10.1364/up.1986.ma2.

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Since its introduction [1], electrooptic (EO) sampling has rapidly developed as a tool for ultrafast electrical measurements [2], [3] with temporal resolution extending to less than a picosecond. The basic physical phenomenon underlying this technique, the Pockels effect, is well-described in the literature [1-5]. The work reported here relies on the fact that GaAs, the substrate material for many high-speed circuits, is electrooptic. Using a longitudinal probing geometry [4], [5], sub-bandgap energy infrared light is passed through the substrate of GaAs integrated circuits (IC's), reflected off some circuit metallization, and passed through a polarizer, resulting in an intensity change of the light proportional to the voltage across the substrate. In addition, the signal generating electronics for driving the IC's are phase locked to the repetition rate of a mode-locked laser laser, allowing sampled measurements of voltage waveforms due to sinusoidal excitation of the circuit. Figure 1 shows the system schematic.
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Звіти організацій з теми "GENERATING CIRCUITS"

1

Ghosh, Abhijit, Srinivas Devadas, and A. R. Newton. Test Generation for Highly Sequential Circuits. Fort Belvoir, VA: Defense Technical Information Center, August 1989. http://dx.doi.org/10.21236/ada211932.

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2

Author, Not Given. Advanced Gate Dielectric Materials for Next-Generation Integrated Circuits. Office of Scientific and Technical Information (OSTI), October 2018. http://dx.doi.org/10.2172/1483866.

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3

Cardwell, Suma, John Smith, and Douglas Crowder. AI-enhanced Codesign for Next-Generation Neuromorphic Circuits and Systems. Office of Scientific and Technical Information (OSTI), September 2022. http://dx.doi.org/10.2172/1889339.

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4

Boppana, Vamsi, and W. Kent Fuchs. Dynamic Fault Collapsing and Diagnostic Test Pattern Generation for Sequential Circuits. Fort Belvoir, VA: Defense Technical Information Center, November 1998. http://dx.doi.org/10.21236/ada351548.

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5

Vawter, G. A., A. Mar, J. Zolper, and V. Hietala. Photonic integrated circuit for all-optical millimeter-wave signal generation. Office of Scientific and Technical Information (OSTI), March 1997. http://dx.doi.org/10.2172/469141.

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6

Eshed, Yuval, and Sarah Hake. Exploring General and Specific Regulators of Phase Transitions for Crop Improvement. United States Department of Agriculture, November 2012. http://dx.doi.org/10.32747/2012.7699851.bard.

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Анотація:
The transition of plants from a juvenile to adult growth phase entails a wide range of changes in growth habit, physiological competence and composition. Strikingly, most of these changes are coordinated by the expression of a single regulator, micro RNA 156 (miR156) that coordinately regulates a family of SBP genes containing a miR156 recognition site in the coding region or in their 3’ UTR. In the framework of this research, we have taken a broad taxonomic approach to examine the role of miR156 and other genetic regulators in phase change transition and its implication to plant development and crop improvement. We set to: Determine the common and unique factors that are altered upon juvenile to adult phase transition. Determine the functions of select miR156 target genes in tomato and maize, and identify those targets that mediate phase transition. Characterize the role of miR172 and its targets in tomato phase change. Determine the relationships between the various molecular circuits directing phase change. Determine the effects of regulated manipulation of phase change genes on plant architecture and if applicable, productivity. In the course of the study, a new technology for gene expression was introduced – next generation sequencing (NGS). Hence some of the original experiments that were planned with other platforms of RNA profiling, primarily Affymetrix arrays, were substituted with the new technology. Yet, not all were fully completed. Moreover, once the initial stage was completed, each group chose to focus its efforts on specific components of the phase change program. The Israeli group focused on the roles of the DELAYED SYMPODIAL TERMINATION and FALSIFLORA factors in tomato age dependent programs whereas the US group characterized in detail the role of miR156 (also termed Cg) in other grasses and in maize, its interplay with the many genes encoding miR172.
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7

Modeling a Printed Circuit Heat Exchanger with RELAP5-3D for the Next Generation Nuclear Plant. Office of Scientific and Technical Information (OSTI), December 2010. http://dx.doi.org/10.2172/1004237.

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