Добірка наукової літератури з теми "Gate array circuits"
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Статті в журналах з теми "Gate array circuits":
Abraitis, Vidas, and Žydrūnas Tamoševičius. "Transition Test Patterns Generation for BIST Implemented in ASIC and FPGA." Solid State Phenomena 144 (September 2008): 214–19. http://dx.doi.org/10.4028/www.scientific.net/ssp.144.214.
Mowafy, Aya Nabeel. "Asynchronous Circuits Design Using a Field Programmable Gate Array." International Journal for Research in Applied Science and Engineering Technology 6, no. 4 (April 30, 2018): 2423–32. http://dx.doi.org/10.22214/ijraset.2018.4412.
Mohammadi, Hossein, and Keivan Navi. "Energy-Efficient Single-Layer QCA Logical Circuits Based on a Novel XOR Gate." Journal of Circuits, Systems and Computers 27, no. 14 (August 23, 2018): 1850216. http://dx.doi.org/10.1142/s021812661850216x.
Sato, Ryoichi, Yuta Kodera, Md Arshad Ali, Takuya Kusaka, Yasuyuki Nogami, and Robert H. Morelos-Zaragoza. "Consideration for Affects of an XOR in a Random Number Generator Using Ring Oscillators." Entropy 23, no. 9 (September 5, 2021): 1168. http://dx.doi.org/10.3390/e23091168.
Kuboki, S., I. Masuda, T. Hayashi, and S. Torii. "A 4K CMOS gate array with automatically generated test circuits." IEEE Journal of Solid-State Circuits 20, no. 5 (October 1985): 1018–24. http://dx.doi.org/10.1109/jssc.1985.1052430.
AKELLA, KAPILAN MAHESWARAN VENKATESH. "PGA-STC: programmable gate array for implementing self-timed circuits." International Journal of Electronics 84, no. 3 (March 1998): 255–67. http://dx.doi.org/10.1080/002072198134823.
Murtaza, Ali Faisal, and Hadeed Ahmed Sher. "A Reconfiguration Circuit to Boost the Output Power of a Partially Shaded PV String." Energies 16, no. 2 (January 4, 2023): 622. http://dx.doi.org/10.3390/en16020622.
Jaafar, Anuar, Norhayati Soin, Sharifah F. Wan Muhamad Hatta, Sani Irwan Salim, and Zahriladha Zakaria. "Multipoint Detection Technique with the Best Clock Signal Closed-Loop Feedback to Prolong FPGA Performance." Applied Sciences 11, no. 14 (July 12, 2021): 6417. http://dx.doi.org/10.3390/app11146417.
Cherepacha, Don, and David Lewis. "DP-FPGA: An FPGA Architecture Optimized for Datapaths." VLSI Design 4, no. 4 (January 1, 1996): 329–43. http://dx.doi.org/10.1155/1996/95942.
Reaungepattanawiwat, Chalermpol, and Yutthana Kanthaphayao. "Voltage Multiplier Circuits with Coupled-Inductor Applied to a High Step-Up DC-DC Converter." Applied Mechanics and Materials 781 (August 2015): 418–21. http://dx.doi.org/10.4028/www.scientific.net/amm.781.418.
Дисертації з теми "Gate array circuits":
Sharma, Akshay. "Place and route techniques for FPGA architecture advancement /." Thesis, Connect to this title online; UW restricted, 2005. http://hdl.handle.net/1773/6108.
Baweja, Gunjeetsingh. "Gate level coverage of a behavioral test generator." Thesis, This resource online, 1993. http://scholar.lib.vt.edu/theses/available/etd-11102009-020104/.
Tan, Zhou. "Design of a Reconfigurable Pulsed Quad-Cell for Cellular-Automata-Based Conformal Computing." Thesis, North Dakota State University, 2011. https://hdl.handle.net/10365/29176.
Hu, Jhy-Fang 1961. "AUTOMATIC HARDWARE COMPILER FOR THE CMOS GATE ARRAY." Thesis, The University of Arizona, 1986. http://hdl.handle.net/10150/276948.
Balog, Michael Rosen Warren A. "The automated compilation of comprehensive hardware design search spaces of algorithmic-based implementations for FPGA design exploration /." Philadelphia, Pa. : Drexel University, 2007. http://hdl.handle.net/1860/1770.
Hall, Tyson Stuart. "Field-Programmable Analog Arrays: A Floating-Gate Approach." Diss., Available online, Georgia Institute of Technology, 2004:, 2004. http://etd.gatech.edu/theses/available/etd-07122004-124607/unrestricted/hall%5Ftyson%5Fs%5F200407%5Fphd.pdf.
Prvulovic, Milos, Committee Member ; Citrin, David, Committee Member ; Lanterman, Aaron, Committee Member ; Yalamanchili, Sudhakar, Committee Member ; Hasler, Paul, Committee Member ; Anderson, David, Committee Chair. Includes bibliographical references.
Qi, Wen-jie. "Study on high-k dielectrics as alternative gate insulators for 0.1[mu] and beyond ULSI applications /." Digital version accessible at:, 2000. http://wwwlib.umi.com/cr/utexas/main.
Mao, Yu-lung. "Novel high-K gate dielectric engineering and thermal stability of critical interface /." Digital version accessible at:, 1999. http://wwwlib.umi.com/cr/utexas/main.
Lee, Jian-hung. "Strontium titanate thin films for ULSI memory and gate dielectric applications /." Digital version accessible at:, 2000. http://wwwlib.umi.com/cr/utexas/main.
Kucic, Matthew R. "Analog programmable filters using floating-gate arrays." Thesis, Georgia Institute of Technology, 2000. http://hdl.handle.net/1853/13755.
Книги з теми "Gate array circuits":
1955-, Trimberger Stephen, ed. Field-programmable gate array technology. Boston: Kluwer Academic Publishers, 1994.
W, Read John, ed. Gate arrays: Design and applications. London: Collins, 1985.
Inc, Xilinx. The programmable gate array data book. San Jose, Calif: XILINX, Inc., 1988.
Hollis, Ernest E. Design of VLSI gate array ICs. Englewood Cliffs, NJ: Prentice-Hall, 1987.
ACM, International Symposium on Field-Programmable Gate Arrays (7th 1999 Monterey Calif ). FPGA '99: ACM/SIGDA International Symposium on Field Programmable Gate Arrays. New York, NY: ACM Press, 1999.
ACM International Symposium on Field-Programmable Gate Arrays (14th 2006 Monterey, Calif.). FPGA 2006: Fourteenth ACM/SIGDA International Symposium on Field-Programmable Gate Arrays : Hyatt Regency Monterey, Monterey, California, USA, February 22-24, 2006. New York: Association for Computing Machinery, 2006.
ACM International Symposium on Field-Programmable Gate Arrays (8th 2000 Monterey, Calif.). FPGA '00: ACM/SIGDA International Symposium on Field Programmable Gate Arrays. New York, N.Y: Association for Computing Machinery, 2000.
ACM, International Symposium on Field-Programmable Gate Arrays (3rd 1995 Monterey Calif ). FPGA '95: 1995 ACM Third International Sympsosium on Field-Programmable Gate Arrays : February 12-14, 1995, Monterey Marriott, Monterey, California, USA. New York, N.Y: ACM Press, 1995.
ACM International Symposium on Field-Programmable Gate Arrays (15th 2007 Monterey, Calif.). FPGA 2007: Fifteenth ACM/SIGDA International Symposium on Field-Programmable Gate Arrays : Monterey Beach Resort, Monterey, California, USA, February 18-20, 2007. New York: Association for Computing Machinery, 2007.
ACM International Symposium on Field-Programmable Gate Arrays (10th 2002 Monterey, Calif.). FPGA 2002: Tenth ACM International Symposium on Field-Programmable Gate Arrays, Monterey, California, USA : February 24-26, 2002. New York, N.Y: ACM Press, 2002.
Частини книг з теми "Gate array circuits":
Sanchez, Eduardo. "Field programmable gate array (FPGA) circuits." In Towards Evolvable Hardware, 1–18. Berlin, Heidelberg: Springer Berlin Heidelberg, 1996. http://dx.doi.org/10.1007/3-540-61093-6_1.
Babu, Hafiz Md Hasan. "Place and Route Algorithm for Field Programmable Gate Array." In VLSI Circuits and Embedded Systems, 207–12. Boca Raton: CRC Press, 2022. http://dx.doi.org/10.1201/9781003269182-20.
Babu, Hafiz Md Hasan. "BCD Adder Using a LUT-Based Field Programmable Gate Array." In VLSI Circuits and Embedded Systems, 287–98. Boca Raton: CRC Press, 2022. http://dx.doi.org/10.1201/9781003269182-23.
Murray, Alan F., and H. Martin Reekie. "The GATEWAY Gate Array Design Exercise." In Integrated Circuit Design, 119–45. New York, NY: Springer New York, 1987. http://dx.doi.org/10.1007/978-1-4899-6675-9_8.
Murray, Alan F., and H. Martin Reekie. "The GATEWAY Gate Array Design Exercise." In Integrated Circuit Design, 119–45. London: Macmillan Education UK, 1987. http://dx.doi.org/10.1007/978-1-349-18758-4_8.
Pau, L. F. "Inspection of Integrated Circuits and Gate Arrays." In Computer Vision for Electronics Manufacturing, 61–86. Boston, MA: Springer US, 1990. http://dx.doi.org/10.1007/978-1-4613-0507-1_5.
Watanabe, Takahiro, and Minoru Watanabe. "Triple Module Redundancy of a Laser Array Driver Circuit for Optically Reconfigurable Gate Arrays." In Lecture Notes in Computer Science, 163–73. Berlin, Heidelberg: Springer Berlin Heidelberg, 2012. http://dx.doi.org/10.1007/978-3-642-28365-9_14.
Trainor, D. W., and R. F. Woods. "Architectural synthesis and efficient circuit implementation for field programmable gate arrays." In Lecture Notes in Computer Science, 116–25. Berlin, Heidelberg: Springer Berlin Heidelberg, 1996. http://dx.doi.org/10.1007/3-540-61730-2_12.
Ramalingam, Suresh, Henley Liu, Myongseob Kim, Boon Ang, Woon-Seong Kwon, Tom Lee, Susan Wu, et al. "A New Class of High-Capacity, Resource-Rich Field-Programmable Gate Arrays Enabled by Three- Dimensional Integration Chip-Stacked Silicon Interconnect Technology." In 3D Integration in VLSI Circuits, 41–69. Boca Raton, FL : CRC Press/Taylor & Francis Group, 2018. |: CRC Press, 2018. http://dx.doi.org/10.1201/9781315200699-3.
Valdés, M. D., M. J. Moure, L. Rodríguez, and A. del Río. "Interactive practical teaching of digital circuits design by means of Field Programmable Gate Arrays." In Computer Aided Learning and Instruction in Science and Engineering, 408–14. Berlin, Heidelberg: Springer Berlin Heidelberg, 1996. http://dx.doi.org/10.1007/bfb0022632.
Тези доповідей конференцій з теми "Gate array circuits":
Larkins, B., S. Canaga, G. Lee, B. Terrell, and I. Deyhimy. "13000 gate ECL compatible GaAs gate array." In 1989 Proceedings of the IEEE Custom Integrated Circuits Conference. IEEE, 1989. http://dx.doi.org/10.1109/cicc.1989.56764.
Gallia, J., A. Yee, I. Wang, K. Chau, H. Davis, S. Swamy, T. Sridhar, et al. "A 100 K gate sub-micron BiCMOS gate array." In 1989 Proceedings of the IEEE Custom Integrated Circuits Conference. IEEE, 1989. http://dx.doi.org/10.1109/cicc.1989.56717.
Takechi, Yamagiwa, Okabe, Arai, Maejima, Zurita, Hara, Takahashi, and Ikuzaki. "A 630k Transistor Cmos Gate Array." In 1988 IEEE International Solid-State Circuits Conference. IEEE, 1988. http://dx.doi.org/10.1109/isscc.1988.663629.
EI-Ajat, El Gamal, Guo, Chang, Hamdy, McCollum, and Mohsen. "A Cmos Electrically Configurable Gate Array." In 1988 IEEE International Solid-State Circuits Conference. IEEE, 1988. http://dx.doi.org/10.1109/isscc.1988.663633.
Krestinskaya, Olga, Akshay Kumar Maan, and Alex Pappachen James. "Programmable Memristive Threshold Logic Gate Array." In 2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS). IEEE, 2018. http://dx.doi.org/10.1109/apccas.2018.8605646.
Kotani, S., A. Inoue, and S. Hasuo. "A 7.6 K-gate Josephson macrocell array." In Digest of Technical Papers., 1990 Symposium on VLSI Circuits. IEEE, 1990. http://dx.doi.org/10.1109/vlsic.1990.111099.
Morita, H., and M. Watanabe. "MEMS optically differential reconfigurable gate array." In 2009 IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC 2009). IEEE, 2009. http://dx.doi.org/10.1109/edssc.2009.5394174.
Nakajima, Mao, and Minoru Watanabe. "A 100-context optically reconfigurable gate array." In 2010 IEEE International Symposium on Circuits and Systems - ISCAS 2010. IEEE, 2010. http://dx.doi.org/10.1109/iscas.2010.5536965.
Notomi, S., T. Kondo, Y. Watanabe, M. Kosugi, S. Hanyu, M. Suzuki, A. Kaneko, T. Mimura, and M. Abe. "A 45k HEMT Gate Array With 35ps DCFL And 50ps BDCFL Gates." In 1991 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. IEEE, 1991. http://dx.doi.org/10.1109/isscc.1991.689105.
Yordanov, Rumen, Irena Yordanova, and Juriy Ivanov. "Automated design system for gate array-based CMOS integrated circuits." In 2012 35th International Spring Seminar on Electronics Technology (ISSE). IEEE, 2012. http://dx.doi.org/10.1109/isse.2012.6273150.