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Автор: Grafiati
Опубліковано: 11 вересня 2023

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Статті в журналах з теми "FILTER IMPLEMENTATION"

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Singh, Gurpadam, and Neelam R. Prakash. "FPGA Implementation of Higher Order FIR Filter." International Journal of Electrical and Computer Engineering (IJECE) 7, no. 4 (August 1, 2017): 1874. http://dx.doi.org/10.11591/ijece.v7i4.pp1874-1881.

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The digital Finite-Impulse-Response (FIR) filters are mainly employed in digital signal processing applications. The main components of digital FIR filters designed on FPGAs are the register bank to save the samples of signals, adder to implement sum operations and multiplier for multiplication of filter coefficients to signal samples. Although, design and implementation of digital FIR filters seem simple but the design bottleneck is multiplier block for speed, power consumption and FPGA chip area occupation. The multipliers are an integral part in FIR structures and these use a large part of the chip area. This limits the number of processing elements (PE) available on the chip to realize a higher order of filter. A model is developed in the Matlab/Simulink environment to investigate the performance of the desired higher order FIR filter. An equivalent FIR filter representation is designed by the Xilinx FIR Compiler by using the exported FIR filter coefficients. The Xilinx implementation flow is completed with the help of Xilinx ISE 14.5. It is observed how the use of higher order FIR filter impacts the resource utilization of the FPGA and it’s the maximum operating frequency.
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2

Horváth, Dušan, Zuzana Červeňanská, and Janette Kotianová. "Digital Implementation of Butterworth First–Order Filter Type IIR." Research Papers Faculty of Materials Science and Technology Slovak University of Technology 27, no. 45 (September 1, 2019): 85–93. http://dx.doi.org/10.2478/rput-2019-0030.

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Abstract The paper deals with the solution of the first–order passive filters (low–pass and high–pass) applying electrotechnical elements (resistor, capacitor - analogue filter) and digital Butterworth filter type IIR (Infinite Impulse Response). Procedure of the filters design and implementation is described, and the analogue and digital filter outputs with the same input signal are compared. The designed filters have already served for education purposes with the intention to bring an explanation of techniques for designing required functionality of the signal processing filters.
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3

Wen, Hui, and Shu Ming Li. "DSP-Based FIR Filter Design and Circular Buffer Implementation." Advanced Materials Research 403-408 (November 2011): 1755–58. http://dx.doi.org/10.4028/www.scientific.net/amr.403-408.1755.

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The digital filter technology includes two aspects, which are the filter design process and filter realization. The article expounded the basic structure of FIR filter, with examples on the use Matlab to determine the FIR filter coefficient, analysis of the cycle of the buffer zone algorithm Principle, based on the algorithm, combination of filters designed to achieve the input of mixed-signal FIR digital filter. In the end, the filter is given before and after the input and output signal waveform simulation.
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4

Satyanarayana, Dr S. V. V., K. Teja Sri, K. Madhavi, G. Jhansi, and B. Jaya Sri. "Design and Implementation of High Speed Low Power Decimation Filter for Hearing AID Applications." International Journal of Recent Technology and Engineering (IJRTE) 12, no. 1 (May 30, 2023): 27–32. http://dx.doi.org/10.35940/ijrte.a7564.0512123.

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This work is focused on designing and implementing a decimation filter specifically intended for use in hearing aid applications. The filter utilizes distributed arithmetic (DA) and is described in this brief. Our proposal involves the development of a reconfigurable finite impulse response (FIR) filter, which utilizes both offset binary code (OBC) and binary distributed arithmetic (DA) techniques. Additionally, we utilize canonic signed digit (CSD) representation to develop decimation filters, which include the CIC filter, half band filter, and corrector filter. In this work, we have implemented a decimation filter using Matlab Simulink. We have utilized Xilinx Vivado 19.2 to execute the FIR filters, binary DA filters, and OBC DA-based filters. Our focus is on implementing these filters using VLSI architecture, in order to achieve low power consumption, reduced latency, less area, and fast speed.
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5

Chen, Jin Lun. "A Multi-Rate Implementation of Auditory Filter Bank." Applied Mechanics and Materials 373-375 (August 2013): 579–82. http://dx.doi.org/10.4028/www.scientific.net/amm.373-375.579.

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The auditory filter-bank is the key component of auditory model, and its implementation involves a lot of computations. The time spent by an auditory filter-bank to finish its work has a significant effect on the real-time implementation of auditory model-based audio signal processing systems. In this paper, a multi-rate implementation of auditory filter bank is presented. Through using low sampling rate for the filters with low centre frequency, and using high sampling rate for the filters with high centre frequency, we can greatly reduce the computation requirement.
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6

Pushpalatha, P., and K. Babulu. "Design and implementation of systolic architecture based FIR filter." i-manager's Journal on Digital Signal Processing 10, no. 1 (2022): 17. http://dx.doi.org/10.26634/jdp.10.1.18852.

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In signal processing, a filter is a device or process that removes some unwanted components or features from a signal. Digital filters are mainly divided into Infinite Impulse Response (IIR) filters and Finite Impulse Response (FIR) filters. FIR filters are mostly used in applications like image processing, communications, Digital Signal Processing (DSP) etc. One of the most used filters for designing of VLSI circuits is FIR filter. Systolic architecture is a Processing Element (PE) network that generates and passes data rhythmically through the system. The concept of systolic architecture can map high-level computing into hardware structures. FIR filter with systolic architectures provide better examples for efficient VLSI and FPGA implementations of many digital signal processing applications because of their modularity and regularity features.
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7

Shaik, Samdhani, and P. Balanagu. "Functional Verification Architecture Implementation for Power Optimized FIR Filter." International Journal of Engineering & Technology 7, no. 2.20 (April 18, 2018): 287. http://dx.doi.org/10.14419/ijet.v7i2.20.14780.

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Digital-filters are having universal for audio applications. So that, great digital-filter execution ought to be taken as an imperative for outline of audio system Applications. The utilization of accuracy with limited in Digital filters for speaking to signals which likewise contrast from that of simple filters as computerized filters utilizing a limited exactness number juggling for registering the filter reaction. Here, FIR-filter has been actualized in Xilinx ISE utilizing VERILOG dialect. VERILOG coding for FIR-filter has been actualized here too waveforms are additionally seen in the reproduction.Viper comprises of less weight as contrasted and multipliers as far as silicon territory and this plays a profitable in FIR structure. This paper has picked multipliers as stall and Wallace and the taken the adders as convey spare and convey skip. In this paper it needs to build up a RTL in the purpose of structures and check the usefulness of structures contrasted and playing out the union utilizing Xilinx synthesizer. The outcomes were thought about regarding region (LUT'S), power, deferral and memory for different fir structures.
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8

Qiu, Xinyi, Hui Feng, and Bo Hu. "Fractional Order Graph Filters: Design and Implementation." Electronics 10, no. 4 (February 10, 2021): 437. http://dx.doi.org/10.3390/electronics10040437.

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Existing graph filters, polynomial or rational, are mainly of integer order forms. However, there are some frequency responses which are not easily achieved by integer order approximation. It will substantially increase the flexibility of the filters if we relax the integer order to fractional ones. Motivated by fractional order models, we introduce the fractional order graph filters (FOGF), and propose to design the filter coefficients by genetic algorithm. In order to implement distributed computation on a graph, an FOGF can be approximated by the continued fraction expansion and transformed to an infinite impulse response graph filter.
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9

Baranowski, Jerzy, and Paweł Piątek. "Fractional Band-Pass Filters: Design, Implementation and Application to EEG Signal Processing." Journal of Circuits, Systems and Computers 26, no. 11 (March 21, 2017): 1750170. http://dx.doi.org/10.1142/s0218126617501705.

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Fractional band-pass filters are a promising area in the signal processing. They are especially attractive as a method for processing of biomedical signals, such as EEG, where large signal distortion is undesired. We present two structures of fractional band-pass filters: one as an analog of classical second-order filter, and one arising from parallel connection of two fractional low-pass filters. We discuss a method for filter implementation — Laguerre Impulse Response Approximation (LIRA) — along with sufficient conditions for when the filter can be realized with it. We then discuss methods of filter tuning, in particular we present some analytical results along with optimization algorithm for numerical tuning. Filters are implemented and tested with EEG signals. We discuss the results highlighting the possible limitations and potential for development.
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10

Stojanovic, Vidosav, Negovan Stamenkovic, and Nikola Stojanovic. "Active RC filter based implementation analysis part of two channel hybrid filter bank." Serbian Journal of Electrical Engineering 11, no. 4 (2014): 565–84. http://dx.doi.org/10.2298/sjee1404565s.

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In the present paper, a new design method for continuous-time powersymmetric active RC filters for Hybrid Filter Bank (HFB) is proposed. Some theoretical properties of continious-time power-symmetric filters bank in a more general perspective are studied. This includes the derivation of a new general analytical form, and a study of poles and zeros locations in s-plane. In the proposed design method the analytic solution of filter coefficients is solved in sdomain using only one nonlinear equation Finally, the proposed approximation is compared to standard approximations. It was shown that attenuation and group delay characteristic of the proposed filter lie between Butterworth and elliptic characteristics.
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Дисертації з теми "FILTER IMPLEMENTATION"

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Chen, Tsuhan Vaidyanathan P. P. Vaidyanathan P. P. "Multidimensional multirate filters and filter banks : theory, design, and implementation /." Diss., Pasadena, Calif. : California Institute of Technology, 1993. http://resolver.caltech.edu/CaltechETD:etd-08232007-095226.

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2

Davati, Soheil. "VLSI implementation of recursive digital notch filter." Ohio : Ohio University, 1986. http://www.ohiolink.edu/etd/view.cgi?ohiou1183128831.

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3

Chen, Min. "Implementation and optimization of a modulated filter bank based on allpass filters." Thesis, University of Ottawa (Canada), 2001. http://hdl.handle.net/10393/9192.

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A filter bank based on an allpass IIR filter with brick-wall response was designed by A. J. Van Leest in [17]; however, the delay in the filter bank is too long to be used in real time applications. In order to reduce the delay, the orders of coefficients, transition bandwidth and filter bank structures must be optimized. The order of coefficients can be reduced by increasing the stopband attenuation. In order to further reduce the delay, the sharpness of the filter bank has to be reduced. This thesis also discussed the number of band and filter bank structure against to filter bank delay. The filter bank can be used in non-real time application such as CD compression with high order coefficient. The minimum transition bandwidth can be reached at 0.03257pi/number of band. This thesis expands upon DCT modulations of IIR based modulated filter banks and investigate the Hartley transformation in filter bank modulation as a new modulation technique. These modulation techniques generate the real output signal with real input signals. The quantization errors from quantizing the coefficient are studied. It is concluded that at least 16 bits are required in order for a filter bank to give a good performance as designed without quantization.
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4

Gebart, Joakim. "GPU Implementation of the Particle Filter." Thesis, Linköpings universitet, Reglerteknik, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-94190.

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This thesis work analyses the obstacles faced when adapting the particle filtering algorithm to run on massively parallel compute architectures. Graphics processing units are one example of massively parallel compute architectures which allow for the developer to distribute computational load over hundreds or thousands of processor cores. This thesis studies an implementation written for NVIDIA GeForce GPUs, yielding varying speed ups, up to 3000% in some cases, when compared to the equivalent algorithm performed on CPU. The particle filter, also known in the literature as sequential Monte-Carlo methods, is an algorithm used for signal processing when the system generating the signals has a highly nonlinear behaviour or non-Gaussian noise distributions where a Kalman filter and its extended variants are not effective. The particle filter was chosen as a good candidate for parallelisation because of its inherently parallel nature. There are, however, several steps of the classic formulation where computations are dependent on other computations in the same step which requires them to be run in sequence instead of in parallel. To avoid these difficulties alternative ways of computing the results must be used, such as parallel scan operations and scatter/gather methods. Another area where parallel programming still is not widespread is the area of pseudo-random number generation. Pseudo-random numbers are required by the algorithm to simulate the process noise as well as for avoiding the particle depletion problem using a resampling step. In this thesis a recently published counter-based pseudo-random number generator is used.
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5

Ozkaya, Hasan. "Parallel Active Filter Design, Control, And Implementation." Master's thesis, METU, 2007. http://etd.lib.metu.edu.tr/upload/12608438/index.pdf.

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The parallel active filter (PAF) is the modern solution for harmonic current mitigation and reactive power compensation of nonlinear loads. This thesis is dedicated to detailed analysis, design, control, and implementation of a PAF for a 3- phase 3-wire rectifier load. Specifically, the current regulator and switching ripple filter (SRF) are thoroughly investigated. A novel discrete time hysteresis current regulator with multi-rate current sampling and flexible PWM output, DHCR3, is proposed. DHCR3 exhibits a high bandwidth while limiting the maximum switching frequency for thermal stability and its implementation is simple. In addition to the development of DHCR3, in the thesis state of the art current regulation methods are considered and thoroughly compared with DHCR3. Since the current regulator type determines the SRF topology choice, various SRF topologies are considered and a thorough design study is conducted and SRF topology selection and parameter determination methods are presented via numerical examples. Through a PAF designed for a 10kW diode/thyristor rectifier load, the superior performance of DHCR3 is verified through simulations and experiments and via comparison to other current regulators. The sufficient switching ripple attenuation of the SRF structures for the designed PAF system and the overall performance of the designed and built PAF system are demonstrated via detailed computer simulations and laboratory experiments. This thesis aids the PAF current regulator and SRF selection, design, and implementation.
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6

Dempster, Andrew. "Digital filter design for low-complexity implementation." Thesis, University of Cambridge, 1995. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.362967.

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Einarsson, Henrik. "Implementation and Performance Analysis of Filternets." Thesis, Linköping University, Department of Biomedical Engineering, 2006. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-5601.

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Nord, Magnus. "Cosine Modulated Filter Banks." Thesis, Linköping University, Department of Electrical Engineering, 2003. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-1641.

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The initial goal of this report was to implement and compare cosine modulated filter banks. Because of time limitations, focus shifted towards the implementation. Filter banks and multirate systems are important in a vast range of signal processing systems. When implementing a design, there are several considerations to be taken into account. Some examples are word length, number systems and type of components. The filter banks were implemented using a custom made software, especially designed to generate configurable gate level code. The generated code was then synthesized and the results were compared. Some of the results were a bit curious. For example, considerable effort was put into implementing graph multipliers, as these were expected to be smaller and faster than their CSDC (Canonic Signed Digit Code) counterparts. However, with one exception, they turned out to generate larger designs. Another conclusion drawn is that the choice of FPGA is important. There are several things left to investigate, though. For example, a more thorough comparison between CSDC and graph multipliers should be carried out, and other DCT (Discrete Cosine Transform) implementations should be investigated.

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9

Alam, Syed Asad. "Techniques for Efficient Implementation of FIR and Particle Filtering." Doctoral thesis, Linköpings universitet, Datorteknik, 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-124195.

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FIR filters occupy a central place many signal processing applications which either alter the shape, frequency or the sampling frequency of the signal. FIR filters are used because of their stability and possibility to have linear-phase but require a high filter order to achieve the same magnitude specifications as compared to IIR filters. Depending on the size of the required transition bandwidth the filter order can range from tens to hundreds to even thousands. Since the implementation of the filters in digital domain requires multipliers and adders, high filter orders translate to a large number of these arithmetic units for its implementation. Research towards reducing the complexity of FIR filters has been going on for decades and the techniques used can be roughly divided into two categories; reduction in the number of multipliers and simplification of the multiplier implementation.  One technique to reduce the number of multipliers is to use cascaded sub-filters with lower complexity to achieve the desired specification, known as FRM. One of the sub-filters is a upsampled model filter whose band edges are an integer multiple, termed as the period L, of the target filter's band edges. Other sub-filters may include complement and masking filters which filter different parts of the spectrum to achieve the desired response. From an implementation point-of-view, time-multiplexing is beneficial because generally the allowable maximum clock frequency supported by the current state-of-the-art semiconductor technology does not correspond to the application bound sample rate. A combination of these two techniques plays a significant role towards efficient implementation of FIR filters. Part of the work presented in this dissertation is architectures for time-multiplexed FRM filters that benefit from the inherent sparsity of the periodic model filters. These time-multiplexed FRM filters not only reduce the number of multipliers but lowers the memory usage. Although the FRM technique requires a higher number delay elements, it results in fewer memories and more energy efficient memory schemes when time-multiplexed. Different memory arrangements and memory access schemes have also been discussed and compared in terms of their efficiency when using both single and dual-port memories. An efficient pipelining scheme has been proposed which reduces the number of pipelining registers while achieving similar clock frequencies. The single optimal point where the number of multiplications is minimum for non-time-multiplexed FRM filters is shown to become a function of both the period, L and time-multiplexing factor, M. This means that the minimum number of multipliers does not always correspond to the minimum number of multiplications which also increases the flexibility of implementation. These filters are shown to achieve power reduction between 23% and 68% for the considered examples. To simplify the multiplier, alternate number systems like the LNS have been used to implement FIR filters, which reduces the multiplications to additions. FIR filters are realized by directly designing them using ILP in the LNS domain in the minimax sense using finite word length constraints. The branch and bound algorithm, a typical algorithm to implement ILP problems, is implemented based on LNS integers and several branching strategies are proposed and evaluated. The filter coefficients thus obtained are compared with the traditional finite word length coefficients obtained in the linear domain. It is shown that LNS FIR filters provide a better approximation  error compared to a standard FIR filter for a given coefficient word length. FIR filters also offer an opportunity in complexity reduction by implementing the multipliers using Booth or standard high-radix multiplication. Both of these multiplication schemes generate pre-computed multiples of the multiplicand which are then selected based on the encoded bits of the multiplier. In TDF FIR filters, one input data is multiplied with a number of coefficients and complexity can be reduced by sharing the pre-computation of the multiplies of the input data for all multiplications. Part of this work includes a systematic and unified approach to the design of such computation sharing multipliers and a comparison of the two forms of multiplication. It also gives closed form expressions for the cost of different parts of multiplication and gives an overview of various ways to implement the select unit with respect to the design of multiplexers. Particle filters are used to solve problems that require estimation of a system. Improved resampling schemes for reducing the latency of the resampling stage is proposed which uses a pre-fetch technique to reduce the latency between 50% to 95%  dependent on the number of pre-fetches. Generalized division-free architectures and compact memory structures are also proposed that map to different resampling algorithms and also help in reducing the complexity of the multinomial resampling algorithm and reduce the number of memories required by up to 50%.
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10

Velmurugan, Rajbabu. "Implementation Strategies for Particle Filter based Target Tracking." Diss., Georgia Institute of Technology, 2007. http://hdl.handle.net/1853/14611.

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This thesis contributes new algorithms and implementations for particle filter-based target tracking. From an algorithmic perspective, modifications that improve a batch-based acoustic direction-of-arrival (DOA), multi-target, particle filter tracker are presented. The main improvements are reduced execution time and increased robustness to target maneuvers. The key feature of the batch-based tracker is an image template-matching approach that handles data association and clutter in measurements. The particle filter tracker is compared to an extended Kalman filter~(EKF) and a Laplacian filter and is shown to perform better for maneuvering targets. Using an approach similar to the acoustic tracker, a radar range-only tracker is also developed. This includes developing the state update and observation models, and proving observability for a batch of range measurements. From an implementation perspective, this thesis provides new low-power and real-time implementations for particle filters. First, to achieve a very low-power implementation, two mixed-mode implementation strategies that use analog and digital components are developed. The mixed-mode implementations use analog, multiple-input translinear element (MITE) networks to realize nonlinear functions. The power dissipated in the mixed-mode implementation of a particle filter-based, bearings-only tracker is compared to a digital implementation that uses the CORDIC algorithm to realize the nonlinear functions. The mixed-mode method that uses predominantly analog components is shown to provide a factor of twenty improvement in power savings compared to a digital implementation. Next, real-time implementation strategies for the batch-based acoustic DOA tracker are developed. The characteristics of the digital implementation of the tracker are quantified using digital signal processor (DSP) and field-programmable gate array (FPGA) implementations. The FPGA implementation uses a soft-core or hard-core processor to implement the Newton search in the particle proposal stage. A MITE implementation of the nonlinear DOA update function in the tracker is also presented.
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Книги з теми "FILTER IMPLEMENTATION"

1

Magnus, Karlsson. Implementation of digital-serial filters. Linköping: Dept. of Electrical Engineering, Univ., 2005.

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2

Wilbur, Mickey Joe D. The VLSI implementation of a GIC switched capacitor filter. Monterey, Calif: Naval Postgraduate School, 1998.

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3

İzzet, Kale, ed. DSP system design: Complexity reduced IIR filter implementation for practical applications. Boston: Kluwer Academic Publishers, 2003.

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4

Krukowski, Artur. DSP system design: Complexity reduced IIR filter implementation for practical applications. Boston, MA: Kluwer Academic, 2004.

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5

David, Banks. The design, implementation, and testing of an imaging system to provide quantitative ion position information at the exit of a quadrupole mass filter. [Toronto, Ont.]: Graduate Dept. of Aerospace Science and Engineering, University of Toronto, 1992.

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6

Banks, David. The design, implementation, and testing of an imaging system to provide quantitative ion position information at the exit of a quadrupole mass filter. Ottawa: National Library of Canada = Bibliothèque nationale du Canada, 1993.

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7

Chen, Wai-Kai. Passive andactive filters: Theory and implementations. New York: Wiley, 1986.

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8

Passive and active filters: Theory and implementations. New York: Wiley, 1986.

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9

Passive and active filters: Theory and implementations. New York: Wiley, 1986.

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10

Poon, Wai-Leong. Implementation of a pipelined delta-sigma biquad filters. Ottawa: National Library of Canada, 1994.

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Частини книг з теми "FILTER IMPLEMENTATION"

1

Jackson, Leland B. "Digital-Filter Implementation." In Digital Filters and Signal Processing, 427–49. Boston, MA: Springer US, 1996. http://dx.doi.org/10.1007/978-1-4757-2458-5_12.

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2

Davey, Samuel, Neil Gordon, Ian Holland, Mark Rutten, and Jason Williams. "Particle Filter Implementation." In SpringerBriefs in Electrical and Computer Engineering, 55–61. Singapore: Springer Singapore, 2016. http://dx.doi.org/10.1007/978-981-10-0379-0_8.

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3

Jackson, Leland B. "Digital-Filter Implementation." In Digital Filters and Signal Processing, 343–63. Boston, MA: Springer US, 1989. http://dx.doi.org/10.1007/978-1-4615-3262-0_12.

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4

Serra, Hugo Alexandre de Andrade, and Nuno Paulino. "Switched Capacitor Filter Implementation." In SpringerBriefs in Electrical and Computer Engineering, 63–78. Cham: Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-11791-1_6.

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5

Williamson, Darrell. "Finite Wordlength IIR Filter Implementation." In Advanced Textbooks in Control and Signal Processing, 327–417. London: Springer London, 1999. http://dx.doi.org/10.1007/978-1-4471-0541-1_5.

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6

Schobben, Daniel W. E. "An Efficient Adaptive Filter Implementation." In Real-time Adaptive Concepts in Acoustics, 47–57. Dordrecht: Springer Netherlands, 2001. http://dx.doi.org/10.1007/978-94-010-0812-9_4.

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7

Banerjee, Amal. "Automated Electronic Filter Design Scheme Implementation and Design Examples." In Automated Electronic Filter Design, 25–56. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-61554-7_3.

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8

Terrell, Trevor J. "Quantisation Considerations in Digital Filter Implementation." In Introduction to Digital Filters, 124–59. London: Palgrave Macmillan UK, 1988. http://dx.doi.org/10.1007/978-1-349-19345-5_4.

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9

Alessio, Silvia Maria. "Digital Filter Properties and Filtering Implementation." In Signals and Communication Technology, 185–221. Cham: Springer International Publishing, 2015. http://dx.doi.org/10.1007/978-3-319-25468-5_6.

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10

Abdelkhalik, Ossama. "Implementation of Kalman Filter for Localization." In Handbook of Position Location, 629–47. Hoboken, NJ, USA: John Wiley & Sons, Inc., 2011. http://dx.doi.org/10.1002/9781118104750.ch19.

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Тези доповідей конференцій з теми "FILTER IMPLEMENTATION"

1

Mahlab, Uri, and Joseph Shamir. "Phase-only entropy optimized filter by simulated annealing." In OSA Annual Meeting. Washington, D.C.: Optica Publishing Group, 1989. http://dx.doi.org/10.1364/oam.1989.tuc5.

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Анотація:
The recently introduced concept of entropy optimized filters1 led to optical correlators of very good discrimination even in the presence of substantial noise. Various numerical procedures were found to be quite effective in the generation of regular holographic filters. However, the convergence of most of these algorithms was inadequate for phase-only filters due to the fast variations in these filters. In this work we show that procedures of simulated annealing are suitable also for the generation of phase-only filters leading to high quality performance. To improve the process of filter generation, electrooptic architectures are proposed for their implementation.
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2

Liu, Duncan T. H., Li-Jen Cheng, and Shin-Tson Wu. "High-Resolution Optical Novelty Filter Using Photorefractive GaAs And High-Speed Nematic Liquid Crystal Phase Modulator." In Photorefractive Materials, Effects, and Devices II. Washington, D.C.: Optica Publishing Group, 1990. http://dx.doi.org/10.1364/pmed.1990.jp1.

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Recently, optical novelty filters [1] have attracted much attention because of their potential applications in motion detection and optical tracking. Most optical novelty filters reported to date use BaTiO3 crystal as the needed nonlinear medium. In a previous report [2], we have shown that, owing to the shorter response time of GaAs, the output resolution of a GaAs based optical novelty filter is potentially much higher than that of a BaTiO3 based optical novelty filter. However, a relatively high-speed spatial phase modulator is needed for such an implementation. As a result, the usual nematic liquid crystal (NLC) modulators used in other implementations of optical novelty filter would respond too slow for the current implementation. Nevertheless, recently, the speed of NLC modulator has been greatly improved by various methods. For example, using the transient nematic effect, a frame time of less than 50 μs have been demonstrated [3]. Such a frame time is more than adequate for the current implementation. In this paper, we report the result of an investigation on the potential of building a high-resolution optical novelty filter using photorefractive GaAs and high-speed nematic liquid crystal phase modulator.
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3

Karimov, Timur I., Denis N. Butusov, Valerii S. Andreev, Vyacheslav G. Rybin, and Dmitry I. Kaplun. "Compact Fixed-Point Filter Implementation." In 2018 22nd Conference of Open Innovations Association (FRUCT). IEEE, 2018. http://dx.doi.org/10.23919/fruct.2018.8468289.

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4

Trimale, Manish B., and Chilveri. "A review: FIR filter implementation." In 2017 2nd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT). IEEE, 2017. http://dx.doi.org/10.1109/rteict.2017.8256573.

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5

Xiao-li Hu, Feng-ying Wang, and Min Zhang. "Hardware implementation of FIR filter." In 2011 International Conference on Multimedia Technology. IEEE, 2011. http://dx.doi.org/10.1109/icmt.2011.6001961.

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6

Shen, Xinglin, Zhiyong Song, Hongqi Fan, and Qiang Fu. "Particle filter implementation of CPHD filter for unknown clutter." In 2017 6th International Conference on Electrical Engineering and Informatics (ICEEI). IEEE, 2017. http://dx.doi.org/10.1109/iceei.2017.8312450.

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7

Prakash, Matcha Surya, and Rafi Ahamed Shaik. "A Distributed Arithmetic Based Approach for the Realization of the Signed-Regressor LMS Adaptive Filter." In International Conference on Signal Processing and Vision. Academy and Industry Research Collaboration Center (AIRCC), 2022. http://dx.doi.org/10.5121/csit.2022.122214.

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This paper presents a distributed arithmetic (DA) based approach for the implementation of signedregressor LMS adaptive filter. DA, although is an efficient technique for the implementation of fixed coefficient filters, the adaptive filter implementation using DA is not a straight-forward task as the partialproducts of the filter weights have to be updated in every iteration. This is achieved by storing the partialproducts of the signum values of the input samples in a look-up-table (LUT). It has been shown that this LUT can be updated to accommodate the partial-products of newest set of samples in an efficient way using the circular- shifting of its address bits. Results indicate that the proposed filter can give better throughputs compared to multiply-and-accumulate (MAC) based implementation and can be effective when implementing large filters. With proper choice of system parameters, the proposed architecture for a 32- tap filter consumes around 87% less number of adder units while providing similar throughput performance compared to most recent existing DA based architecture.
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8

Marin, Sandra, Jorge D. Martinez, and Vicente E. Boria. "Resistorless Implementation of Lossy Filters Using Coaxial SIW Resonators With Non-uniform Q." In 2021 IEEE MTT-S International Microwave Filter Workshop (IMFW). IEEE, 2021. http://dx.doi.org/10.1109/imfw49589.2021.9642374.

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9

Pohl, Zdenek, Rudolf Matoušek, Jirí Kadlec, Milan Tichý, and Miroslav Lícko. "Lattice adaptive filter implementation for FPGA." In the 2003 ACM/SIGDA eleventh international symposium. New York, New York, USA: ACM Press, 2003. http://dx.doi.org/10.1145/611817.611877.

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10

Salah, Mohamed, Abdel-Halim Zekry, and Mohammed Kamel. "FPGA implementation of LMS adaptive filter." In 2011 28th National Radio Science Conference (NRSC). IEEE, 2011. http://dx.doi.org/10.1109/nrsc.2011.5873634.

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Звіти організацій з теми "FILTER IMPLEMENTATION"

1

Moore, Murray E., Kirk Patrick Reeves, Douglas Kirk Veirs, Paul Herrick Smith, and Timothy Amos Stone. SAVY 4000 Container Filter Design Life and Extension Implementation. Office of Scientific and Technical Information (OSTI), August 2017. http://dx.doi.org/10.2172/1377375.

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2

Moore, Murray E., Kirk Patrick Reeves, Douglas Kirk Veirs, Paul Herrick Smith, and Timothy Amos Stone. SAVY 4000 Container Filter Design Life and Extension Implementation. Office of Scientific and Technical Information (OSTI), April 2015. http://dx.doi.org/10.2172/1177522.

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3

Whitney, James E. Implementation of a Kalman Filter for Single-Sensor Tracking. Fort Belvoir, VA: Defense Technical Information Center, September 2000. http://dx.doi.org/10.21236/ada385404.

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4

RADDER, JERAHMIE WILLIAM. Implementation of a High Throughput Variable Decimation Pane Filter Using the Xilinx System Generator. Office of Scientific and Technical Information (OSTI), January 2003. http://dx.doi.org/10.2172/808628.

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5

Hatch, Andrew G., Ralph C. Smith, Tathagata De, and Murti V. Salapaka. Construction and Experimental Implementation of a Model-Based Inverse Filter to Attenuate Hysteresis in Ferroelectric Transducers. Fort Belvoir, VA: Defense Technical Information Center, January 2005. http://dx.doi.org/10.21236/ada440154.

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6

Hatch, Andrew, Ralph G. Smith, and Tathagata De. Experimental Implementation of a Model-Based Inverse Filter to Attenuate Hysteresis in an Atomic Force Microscope. Fort Belvoir, VA: Defense Technical Information Center, January 2004. http://dx.doi.org/10.21236/ada452004.

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7

Kanagavel, Rameshkumar, and Indragandhi Vairavasundaram. FPGA Implementation and Investigation of Hybrid Artificial Bee Colony Algorithm-based Single Phase Shunt Active Filter. "Prof. Marin Drinov" Publishing House of Bulgarian Academy of Sciences, May 2020. http://dx.doi.org/10.7546/crabs.2020.05.13.

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8

Bethel, E. Wes, and E. Wes Bethel. Exploration of Optimization Options for Increasing Performance of a GPU Implementation of a Three-dimensional Bilateral Filter. Office of Scientific and Technical Information (OSTI), January 2012. http://dx.doi.org/10.2172/1082192.

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9

Collier, Wiehrs L. VLSI (Very Large Scale Integrated Circuits) Implementation of a Quantized Sinusoid Filter Algorithm and Its Use to Compute the Discrete Fourier Transform. Fort Belvoir, VA: Defense Technical Information Center, March 1986. http://dx.doi.org/10.21236/ada168605.

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10

Daniel, Michael M., and Alan S. Willsky. Efficient Implementations of 2-D Noncasual IIR Filters. Fort Belvoir, VA: Defense Technical Information Center, March 1995. http://dx.doi.org/10.21236/ada459571.

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