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Статті в журналах з теми "Digital processor architectures"
Lee, Jongbok. "Performance Study of Multicore Digital Signal Processor Architectures." Journal of the Institute of Webcasting, Internet and Telecommunication 13, no. 4 (August 31, 2013): 171–77. http://dx.doi.org/10.7236/jiibc.2013.13.4.171.
Повний текст джерелаShirai, Katsuhiko, and Toshiyuki Takezawa. "Expert system for designing digital signal processor architectures." Microprocessors and Microsystems 12, no. 2 (March 1988): 83–91. http://dx.doi.org/10.1016/0141-9331(88)90046-4.
Повний текст джерелаShirai, K., and T. Takezawa. "Expert system for designing digital signal processor architectures." Computer-Aided Design 20, no. 7 (September 1988): 423. http://dx.doi.org/10.1016/0010-4485(88)90220-5.
Повний текст джерелаVehlies, Uwe. "Stepwise Transformation of Algorithms into Array Processor Architectures by the DECOMP." VLSI Design 3, no. 1 (January 1, 1995): 67–80. http://dx.doi.org/10.1155/1995/76861.
Повний текст джерелаBakó, László, Szabolcs Hajdú, and Fearghal Morgan. "Evaluation and Comparison of Low FPGA Footprint, Embedded Soft-Core Processors." MACRo 2015 2, no. 1 (October 1, 2017): 23–30. http://dx.doi.org/10.1515/macro-2017-0003.
Повний текст джерелаHasler, Jennifer. "Analog Architecture Complexity Theory Empowering Ultra-Low Power Configurable Analog and Mixed Mode SoC Systems." Journal of Low Power Electronics and Applications 9, no. 1 (January 21, 2019): 4. http://dx.doi.org/10.3390/jlpea9010004.
Повний текст джерелаFahmy, M. M., and Y. Wan. "New array processor architectures for two-dimensional FIR digital filters." IEE Proceedings E Computers and Digital Techniques 136, no. 4 (1989): 234. http://dx.doi.org/10.1049/ip-e.1989.0032.
Повний текст джерелаLee, Jongbok. "A Performance Study of Asymmetric Multi-core Digital Signal Processor Architectures." Journal of The Institute of Internet, Broadcasting and Communication 15, no. 5 (October 31, 2015): 219–24. http://dx.doi.org/10.7236/jiibc.2015.15.5.219.
Повний текст джерелаPadma, Chennagiri Rajarao, and Dr K. M. Ravikumar. "Low-cost Magnetic Resonance Console Architecture using an Open Source for Laboratory Scale Systems." International Journal of Innovative Technology and Exploring Engineering 12, no. 2 (January 30, 2023): 26–32. http://dx.doi.org/10.35940/ijitee.b9413.0112223.
Повний текст джерелаL. M. Hassan, S., N. Sulaiman, S. S. Shariffudin, and T. N. T. Yaakub. "Signal-to-noise Ratio Study on Pipelined Fast Fourier Transform Processor." Bulletin of Electrical Engineering and Informatics 7, no. 2 (June 1, 2018): 230–35. http://dx.doi.org/10.11591/eei.v7i2.1167.
Повний текст джерелаДисертації з теми "Digital processor architectures"
Omundsen, Daniel (Daniel Simon) Carleton University Dissertation Engineering Electrical. "A pipelined, multi-processor architecture for a connectionless server for broadband ISDN." Ottawa, 1992.
Знайти повний текст джерелаPatel, Dipesh Ishwerbhai. "Architectural considerations for a control system processor." Thesis, Loughborough University, 1996. https://dspace.lboro.ac.uk/2134/11075.
Повний текст джерелаVermillion, Joshua D. "The digital craftsperson : an investigation into digital tools/processes/craft." Virtual Press, 2005. http://liblink.bsu.edu/uhtbin/catkey/1318944.
Повний текст джерелаDepartment of Architecture
Runyon, Ginger R. "Parallel processor architecture for a digital beacon receiver." Thesis, Virginia Tech, 1990. http://hdl.handle.net/10919/41422.
Повний текст джерелаSinger, Jonathan Noam. "A shared bus architecture for a digital signal processor and a microcontroller." Thesis, Massachusetts Institute of Technology, 1996. http://hdl.handle.net/1721.1/38810.
Повний текст джерелаNetzer, Gilbert. "Efficient LU Factorization for Texas Instruments Keystone Architecture Digital Signal Processors." Thesis, KTH, Skolan för datavetenskap och kommunikation (CSC), 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-170445.
Повний текст джерелаEnergiförbrukningen av storskaliga högpresterande datorsystem (HPC) har blivit ett av de främsta problemen för såväl ägare av dessa system som datortillverkare. Det har lett till ett förnyat intresse för alternativa datorarkitekturer som kan vara betydligt mer effektiva ur energiförbrukningssynpunkt. För detaljerade analyser av prestanda och energiförbrukning av dessa för HPC-industrin nya arkitekturer krävs väloptimerade implementationer av standard HPC-bänkmärkningsproblem. Syftet med detta examensarbete är att tillhandhålla ett sådant högkvalitativt verktyg i form av en implementation av ett bänkmärkesprogram för LU-faktorisering för den åttakärniga digitala signalprocessorn (DSP) TMS320C6678 från Texas Instruments. Bänkmärkningsproblemet är samma som för det inom HPC-industrin välkända bänkmärket “high-performance LINPACK” (HPL). Den här presenterade implementationen nådde upp till en prestanda av 30,9 GF/s vid 1,25 GHz klockfrekvens genom att samtidigt använda alla åtta kärnor i DSP:n. Detta motsvarar 77% av den teoretiskt uppnåbara prestandan, vilket är jämförbart med förväntningar på effektivteten av mer traditionella x86-baserade system. En detaljerad prestandaanalys visar att detta tillstor del uppnås genom den högoptimerade implementationen av den ingående matris-matris-multiplikationen. Användandet av specialiserade “direct memory access” (DMA) hårdvaruenheter för kopieringen av data mellan det externa DDR3 minnet och det interna kärn-privata och delade arbetsminnet tillät att överlappa dessa operationer med beräkningar. Optimerade mjukvaruimplementationer av dessa beräkningar, delvis utförda i maskinspåk, tillät att utföra matris-multiplikationen med upp till 95% av den teoretiskt nåbara prestandan. I rapporten ges en detaljerad beskrivning av dessa två nyckeltekniker. Energiförbrukningen vid exekvering av det implementerade bänkmärket kunde med hjälp av en för ändamålet anpassad Advantech TMDXEVM6678L evalueringsmodul bestämmas till maximalt 2,92 GF/J. Resultat från verifikationen av bänkmärkesimplementationen och en uppskattning av mätosäkerheten vid de experimentella mätningarna presenteras också.
Nascimento, Anelise Ventura. "Fronteiras permeáveis entre a arquitetura e a biologia: processos de projeto digital." Universidade de São Paulo, 2015. http://www.teses.usp.br/teses/disponiveis/102/102132/tde-31082015-155107/.
Повний текст джерелаThe research aims to study the interrelationship between the contemporary architecture design processes, mediated by computer technology and the biology processes, with a view under the concepts of ecology, supported on system theory and cybernetics. The analyzes aim to relate issues on the spheres of theory and practice, within the observation of design processes, through the following steps: 1. Introduction and understanding of the current paradigm shifts in biology, ecology and computer science, which directly holds the modes of producing information in architecture digital design processes; 2. Thoughts on cybernetic theory and complex systems like links between biological processes and architectural design processes, with implications in emergence and innovation in architecture 3. Analyses of study cases about design processes and digital production integration recurrent from the interrelationship between architecture and biology.
Alves, Gilfranco Medeiros. "Cibersemiótica e processos de projeto: metodologia em revisão." Universidade de São Paulo, 2014. http://www.teses.usp.br/teses/disponiveis/102/102132/tde-07012015-105828/.
Повний текст джерелаThe thesis explores the Cibersemiotic approach to design processes from the perspective of digital mediation and its relationship with contemporary architecture. It presents a review of existing digital design processes, based on the assumption that the practice of architects and designers, according to the contemporary modes of life, currently requires a different position in relation to the management of information, as well as a critical reflection on the design methods used in the architecture of the digital age. The thesis\' theoretical foundation is based on the Cibersimiotic work produced by the Danish philosopher Søren Brier, which unifies two important conceptual frameworks: the Semiotics by Charles Sanders Peirce and the Second Order Cybernetics proposed by Heinz von Foerster. The thesis proposes a structure (or framework) to analyze existing designs from the cibersemiotic point of view, as well as a structure (or framework) for the digital design processes themselves. The work is presented in two parts. The first examines the digital processes and production as well as the theories they are based on. This part also presents the theoretical context for the structure (or framework) used to analyse selected existing designs and introduces the framework. The second part presents strategies for digital design and proposes the cibersemiotic framework for digital design processes. It is believed the thesis contributes towards the expansion of the Cibersemiotic theoretical paradigm as well as provides a working framework for the increasingly complex processes of digital design. Assuming other spatialities and interconnections will arise from the update levels established from communication between different systems as well as new social and cultural challenges, it is essential that architects are aware of available theories and processes for optimizing design potential and expand the possibilities for Architecture and Urbanism.
Gambarato, Roberto Rampazzo. "A linguagem do movimento na arquitetura contemporânea." Universidade de São Paulo, 2006. http://www.teses.usp.br/teses/disponiveis/16/16136/tde-26052010-111343/.
Повний текст джерелаThis research is characterized as a study of graphconceptual analysis concerning to the importance of processes of creative action related to the subject of the movement by means of representation forms and exploration of space and time in the Architecture. It introduces the representation in the architectural language, understood as the relationship between time and space. It investigates how the movement - being a possible synthesis of this equation - can be noticed, represented and interpreted in the generation of an architectural project. The dissertation contemplates the change of paradigms which characterize the transition of the representational methods, from analogical to digital movement expressions in the architectural language, as well as new parameters of projetual reasoning by means of the analysis of projects of architects, designers and artists. It contextualizes the manifestations of clear relationships in Architecture within the understanding of space, time and movement as a basis of comparative reflection between the modernity and the contemporaneity.
Bednarski, Andrzej. "Integrated Optimal Code Generation for Digital Signal Processors." Doctoral thesis, Linköping : Department of Computer and Information Science, Linköpings universitet, 2006. http://www.bibl.liu.se/liupubl/disp/disp2006/tek1021s.pdf.
Повний текст джерелаКниги з теми "Digital processor architectures"
1965-, Lapsley Phil, ed. DSP processor fundamentals: Architectures and features. New York: IEEE Press, 1997.
Знайти повний текст джерелаWoon-Seng, Gan, ed. Digital signal processors: Architectures, implementations, and applications. Upper Saddle River, N.J: Pearson/Prentice Hall, 2005.
Знайти повний текст джерелаA digital optical cellular image processor: Theory, architecture, and implementation. Singapore: World Scientific, 1990.
Знайти повний текст джерелаMaterial strategies in digital fabrication. New York: Routledge, 2012.
Знайти повний текст джерелаHoffmann, Andreas. Architecture exploration for embedded processors with LISA. Boston: Kluwer Academic Publishers, 2002.
Знайти повний текст джерелаPoppelbaum, W. J. The UNIFIELD processor: A matrix computer using strings of "ones" to represent decimals. Urbana, Ill. (1304 W. Springfield Ave., Urbana 61801): Dept. of Computer Science, University of Illinois at Urbana-Champaign, 1986.
Знайти повний текст джерелаInternational Conference on Application Specific Systems, Architectures and Processors (12th 2000 Boston, Massachusetts). IEEE International Conference on Application-Specific Systems, Architectures and Processors: Proceedings, July 10-12, 2000, Boston, Massachusetts. Los Alamitos, Calif: IEEE Computer Society Press, 2000.
Знайти повний текст джерела1967-, Schulte Michael Joseph, and IEEE Computer Society. Technical Committee on VLSI., eds. IEEE International Conference on Application-Specific Systems, Architectures and Processors: Proceedings : 17-19 July, 2002 ; San Jose, California. Los Alamitos, California: IEEE Computer Society, 2002.
Знайти повний текст джерелаIEEE International Conference on Application-Specific Systems, Architectures, and Processors (16th 2005 Samos, Greece). 16th IEEE International Conference on Application-Specific Systems, Architectures, and Processors: ASAP 2005 : 23-25 July 2005, Samos, Greece. Los Alamitos, Calif: IEEE Computer Society, 2005.
Знайти повний текст джерела1944-, Deprettere Ed F., and IEEE Computer Society, eds. IEEE International Conference on Application-Specific Systems, Architectures and Processors: Proceedings : ASAP 2003 : 24-26 June, 2003, The Hague, The Netherlands. Los Alamitos, Calif: IEEE Computer Society, 2003.
Знайти повний текст джерелаЧастини книг з теми "Digital processor architectures"
Crovato, César, Delfim Torok, Regina Heidrich, Bernardo de Cerqueira, and Eduardo Velho. "A Preprocessing Algorithm to Increase OCR Performance on Application Processor-Centric FPGA Architectures." In Inclusive Smart Cities and Digital Health, 27–34. Cham: Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-39601-9_3.
Повний текст джерелаBrennecke, R. "Image Processors for Digital Angiography Algorithms and Architectures." In Digital Radiography, 13–33. Boston, MA: Springer US, 1986. http://dx.doi.org/10.1007/978-1-4684-5068-2_2.
Повний текст джерелаBonwetsch, Tobias. "Robotic Assembly Processes as a Driver in Architectural Design." In Digital Fabrication, 483–94. Basel: Springer Basel, 2012. http://dx.doi.org/10.1007/978-3-0348-0582-7_7.
Повний текст джерелаBreitfuss, D., G. Šibenik, and M. Srećković. "Digital traceability for planning processes." In ECPPM 2021 – eWork and eBusiness in Architecture, Engineering and Construction, 132–38. London: CRC Press, 2021. http://dx.doi.org/10.1201/9781003191476-18.
Повний текст джерелаCarlini, Alessandra. "Museum Education Between Digital Technologies and Unplugged Processes. Two Case Studies." In Makers at School, Educational Robotics and Innovative Learning Environments, 155–63. Cham: Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-77040-2_21.
Повний текст джерелаChiarella, Mauro, Andrés Martín-Pastor, and Nicolás Saez. "Graphic Thinking and Digital Processes: Three Built Case Studies of Digital Materiality (COCOON/Colombia, BANCAPAR/Chile, SSFS/Argentina)." In Architectural Draughtsmanship, 1033–44. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-58856-8_81.
Повний текст джерелаJullien, G. A. "Architectures and Building Blocks for Data Stream DSP Processors." In VLSI Design Methodologies for Digital Signal Processing Architectures, 319–63. Boston, MA: Springer US, 1994. http://dx.doi.org/10.1007/978-1-4615-2762-6_9.
Повний текст джерелаTous, Rubén, Roberto García, Eva Rodríguez, and Jaime Delgado. "Architecture of a Semantic XPath Processor. Application to Digital Rights Management." In E-Commerce and Web Technologies, 1–10. Berlin, Heidelberg: Springer Berlin Heidelberg, 2005. http://dx.doi.org/10.1007/11545163_1.
Повний текст джерелаReyserhove, Hans, and Wim Dehaene. "Near-Threshold Operation: Technology, Building Blocks and Architecture." In Efficient Design of Variation-Resilient Ultra-Low Energy Digital Processors, 17–51. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-12485-4_2.
Повний текст джерелаStavrić, Milena, Predrag Šiđanin, and Bojan Tepavčević. "Manufacturing Scale Models & Scale Model Components: Methods And Processes." In Architectural Scale Models in the Digital Age, 123–60. Vienna: Springer Vienna, 2013. http://dx.doi.org/10.1007/978-3-7091-1448-3_5.
Повний текст джерелаТези доповідей конференцій з теми "Digital processor architectures"
Petrov, P., and A. Orailoglu. "Customizable embedded processor architectures." In Proceedings. Euromicro Symposium on Digital System Design. IEEE, 2003. http://dx.doi.org/10.1109/dsd.2003.1231986.
Повний текст джерелаSchaffer, R., R. Merker, and F. Catthoor. "Causality constraints for processor architectures with sub-word parallelism." In Proceedings. Euromicro Symposium on Digital System Design. IEEE, 2003. http://dx.doi.org/10.1109/dsd.2003.1231904.
Повний текст джерелаWolinski, Christophe, Krzysztof Kuchcinski, Jürgen Teich, and Frank Hannig. "Communication Network Reconfiguration Overhead Optimization in Programmable Processor Array Architectures." In 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools. IEEE, 2008. http://dx.doi.org/10.1109/dsd.2008.1.
Повний текст джерелаTulabandhula, Theja, Amit Patra, and Nirmal B. Chakrabarti. "Design of a Two Dimensional PRSI Image Processor." In 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools. IEEE, 2008. http://dx.doi.org/10.1109/dsd.2008.80.
Повний текст джерелаDanese, G., M. Giachero, F. Leporati, and N. Nazzicari. "A Multicore Embedded Processor for Fingerprint Recognition." In 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD). IEEE, 2010. http://dx.doi.org/10.1109/dsd.2010.101.
Повний текст джерелаJeitler, Marcus, and Jakob Lechner. "Low Latency Recovery from Transient Faults for Pipelined Processor Architectures." In 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD). IEEE, 2010. http://dx.doi.org/10.1109/dsd.2010.87.
Повний текст джерелаFunaki, Toshimasa, and Toshinori Sato. "Formulating MITF for a Multicore Processor with SEU Tolerance." In 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools. IEEE, 2008. http://dx.doi.org/10.1109/dsd.2008.48.
Повний текст джерелаKundeti, Vamsi, Yunsi Fei, and Sanguthevar Rajasekaran. "An efficient digital circuit for implementing Sequence Alignment algorithm in an extended processor." In 2008 International Conference on Application-Specific Systems, Architectures and Processors (ASAP). IEEE, 2008. http://dx.doi.org/10.1109/asap.2008.4580171.
Повний текст джерелаAntichi, Gianni, Andrea Di Pietro, Domenico Ficara, Stefano Giordano, Gregorio Procissi, and Fabio Vitucci. "Design of a High Performance Traffic Generator on Network Processor." In 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools. IEEE, 2008. http://dx.doi.org/10.1109/dsd.2008.36.
Повний текст джерелаHempel, Gerald, and Christian Hochberger. "A resource optimized Processor Core for FPGA based SoCs." In 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007). IEEE, 2007. http://dx.doi.org/10.1109/dsd.2007.4341449.
Повний текст джерелаЗвіти організацій з теми "Digital processor architectures"
Bequillard, A. L., D. O. Carhoun, and W. L. Eastman. Advanced Architectures for Digital Signal Processors. Fort Belvoir, VA: Defense Technical Information Center, October 1985. http://dx.doi.org/10.21236/ada166921.
Повний текст джерелаAndrews, Michael, and David James. SBNR (Signed Binary Number Representations) Digital Signal Processor Architecture. Fort Belvoir, VA: Defense Technical Information Center, May 1987. http://dx.doi.org/10.21236/ada184603.
Повний текст джерелаParhi, Keshab K. Design Tools and Architectures for Dedicated Digital Signal Processing (DSP) Processors. Fort Belvoir, VA: Defense Technical Information Center, July 1996. http://dx.doi.org/10.21236/ada397589.
Повний текст джерелаUrquidi, Manuel, Gloria Ortega, Víctor Arza, and Julia Ortega. New Employment Technologies: The Benefits of Implementing Services within an Enterprise Architecture Framework: Executive Summary. Inter-American Development Bank, July 2021. http://dx.doi.org/10.18235/0003403.
Повний текст джерелаINNOVATION AND PRACTICE IN BUILDING STRUCTURE DESIGN. The Hong Kong Institute of Steel Construction, August 2022. http://dx.doi.org/10.18057/icass2020.p.158.
Повний текст джерела