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Автор: Grafiati
Опубліковано: 10 грудня 2022
Оновлено: 28 січня 2023

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Статті в журналах з теми "Delta sigma data converter"

1

Galton, Ian, Richard Schreier, and Gabor C. Temes. "Book review: Delta-Sigma data converters." IEEE Solid-State Circuits Society Newsletter 10, no. 3 (September 2005): 5–6. http://dx.doi.org/10.1109/n-ssc.2005.6500102.

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2

Palumbo, G. "Understanding Delta- Sigma Data Converters [Book Review]." IEEE Circuits and Devices Magazine 22, no. 4 (July 2006): 31–32. http://dx.doi.org/10.1109/mcd.2006.1708376.

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3

Yang, Fuwen, and Mahbub Gani. "Robust Calibration of an Improved Delta-Sigma Data Converter Using Convex Optimization." IEEE Journal of Selected Topics in Signal Processing 1, no. 4 (December 2007): 678–85. http://dx.doi.org/10.1109/jstsp.2007.910280.

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4

NERURKAR, SHAILESH B., and KHALID H. ABED. "A LOW POWER CASCADED FEED-FORWARD DELTA-SIGMA MODULATOR FOR RF WIRELESS APPLICATIONS." Journal of Circuits, Systems and Computers 18, no. 02 (April 2009): 407–29. http://dx.doi.org/10.1142/s0218126609005149.

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This paper presents a design of a novel cascaded third-order feed-forward delta-sigma analog-to-digital converter (ADC). This ADC is realized using fully differential switched capacitor architecture and produces a 12-bit resolution at a data output rate (DOR) of 2.5 MS/s for RF wireless applications. The delta-sigma modulator consists of a second-order single-bit feed-forward modulator cascaded with a multi-bit first-order modulator. The cascaded feed-forward third-order (2-1) ADC is simulated using Matlab and Simulink. The delta-sigma modulator was designed using Cadence Virtuoso in TSMC 0.18 μm CMOS technology. The power consumption of the designed modulator is 12.74 mW, and the resolution is 11.85 bits for an over-sampling ratio (M = 32). The figure of merit is 1.38 pJ at a sample rate of 80 MS/s. The proposed delta-sigma modulator is compared with other state-of-the-art low-pass delta-sigma modulators in terms of their speed, power, DOR, and the proposed modulator has one of the lowest power consumption.
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5

DOLEV, NOAM, AVNER KORNFELD, and AVINOAM KOLODNY. "COMPARISON OF SIGMA–DELTA CONVERTER CIRCUIT ARCHITECTURES IN DIGITAL CMOS TECHNOLOGY." Journal of Circuits, Systems and Computers 14, no. 03 (June 2005): 515–32. http://dx.doi.org/10.1142/s0218126605002507.

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Integration of analog-to-digital signal conversion circuits into digital submicron silicon chips is required for many applications. This is typically implemented by sigma–delta circuits, which can provide good resolution without requiring trimming of component values. This paper presents an analytical comparison of noise performance in four alternative sigma–delta circuit configurations which have been presented in the literature, consisting of discrete-time and continuous-time integration in voltage-mode and in current-mode. For high resolution, superiority of switched-capacitor circuits over the alternatives is shown, based on process technology considerations. Design guidelines are outlined for selecting oversampling rate and other key parameters, in order to obtain maximal data resolution.
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6

Morozov, D. V., M. M. Pilipko, and A. S. Korotkov. "Delta-sigma modulator of the analog-to-digital converter with ternary data encoding." Russian Microelectronics 40, no. 1 (January 2011): 59–69. http://dx.doi.org/10.1134/s1063739710061034.

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7

Herkle, Andreas, Joachim Becker, and Maurits Ortmanns. "Exploiting Weak PUFs From Data Converter Nonlinearity—E.g., A Multibit CT $\Delta\Sigma$ Modulator." IEEE Transactions on Circuits and Systems I: Regular Papers 63, no. 7 (July 2016): 994–1004. http://dx.doi.org/10.1109/tcsi.2016.2555238.

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8

Morozov, D. V., M. M. Pilipko, and A. S. Korotkov. "Decimation filter of the delta-sigma analog-to-digital converter with ternary data encoding." Russian Microelectronics 40, no. 5 (September 2011): 352–60. http://dx.doi.org/10.1134/s1063739711050064.

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9

Osawa, Yusuke, Daiki Hirabayashi, Naohiro Harigai, Haruo Kobayashi, Osamu Kobayashi, Masanobu Tsuji, Sadayoshi Umeda, et al. "Phase Noise Measurement and Testing with Delta-Sigma TDC." Key Engineering Materials 643 (May 2015): 149–55. http://dx.doi.org/10.4028/www.scientific.net/kem.643.149.

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This paper describes a phase noise measurement and testing technique for a clock using a delta-sigma time-to-digital converter (TDC) and verifies its effectiveness with MATLAB simulations. The proposed technique can be implemented with relatively small circuitry, based on the following: (i) The clock under test (CUT) is a repetitive signal. (ii) The time resolution with CUT and a reference clock can be finer with longer measurement time with the delta-sigma TDC. (iii) The phase noise power spectrum can be calculated from the delta-sigma TDC output data using FFT. High performance spectrum analyzers with long measurement time (several ten seconds order due to average of several-time phase measurement results), which are very costly in mass production testing, are not be needed for phase noise measurement with the proposed technique. Our simulation used the input clock of 1 MHz in several phase fluctuation cases, and we observed that the phase fluctuation spectrum at the expected frequency from TDC output power spectrum obtained by FFT. We also investigated the amount of phase fluctuation with our theoretical calculation, which agrees with the simulation results.
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10

Nahar, Ali Kareem, and Hussain K. Khleaf. "Delta-sigma ADC modulator for multibit data converters using passive adder entrenched second order noise shaping." Bulletin of Electrical Engineering and Informatics 10, no. 4 (August 1, 2021): 1952–59. http://dx.doi.org/10.11591/eei.v10i4.2934.

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This paper introduces a multi-bit data converters (MDC) modulator of the 2nd order delta-sigma analog-to-digital converter use the passive adder proposed. The noise shaping quantizer can provide feedback that has generated quantization noise and perform additional shaping noise first-order by coupling noise method.Thus, two Integrator's with ring amplifier and the MDC is shaped by noise coupling quantizer know the 2nd-order noise coupled with somewhat of a DAC modulator. At a summing point, the inputs are summed and then filtered with a low pass filter. A cyclic second order response is generated with a data weighted averaging (DWA) technique in which the DACs ' outputs are limited to one of two states in the noise shaping responses. Mainly as a result of the harmonic distortion in circuits of amplifier. Transistor rate is equipped for the fully differential switched condenser integrator used, a comparator and DWA. The modulator with proposed DWA design, almost quarterly improved timing margin. A simulated SNDR of 92dB is obtained at 20 MHz sampling frequency; while a sinusoidal output of 4.112 dBFS is tested at 90µs besides 20 MHz as the bandwidth. The power consumption is 0.33 mW while the voltage of the supply is 1.2V.
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Дисертації з теми "Delta sigma data converter"

1

Gelhaar, B., K. Alvermann, and F. Dzaak. "A MULTICHANNEL DATA ACQUISITION SYSTEM BASED ON PARALLEL PROCESSOR ARCHITECTURES." International Foundation for Telemetering, 1992. http://hdl.handle.net/10150/608884.

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International Telemetering Conference Proceedings / October 26-29, 1992 / Town and Country Hotel and Convention Center, San Diego, California
For research purposes on helicopter rotor acoustics a large data acquisition system called TEDAS (Transputer based Expandable Data Acquisition System) has been developed. The key features of this system are: unlimited expandability and sum data rate, local storage of data during operation, very simple analog anti aliasing filtering due to extensive digital filtering, and integrated computational power which scales with the number of channels. The sample rate is up to 50 kHz/channel, the resolution is 16 bit, 360 channels are realized now. TEDAS consists of blocks with 8 A/D converters which are controlled by one transputer T800. The size of the local memory is 4 Mbyte. Any number of blocks (IDAM = Intelligent Data Acquisition Module) can be combined to a complete system. Data preprocessing is done in parallel inside the IDAMs. As for 16 bit systems the analog antialiasing filtering becomes a dominant factor of the costs, delta sigma ADCs with oversampling and internal digital filtering are used. This produces an exact linear phase and a stop band rejection of -90 dB.
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2

Vijjapu, Sudheer Paarmann Larry D. "RC implementation of an audio frequency band Butterworth MASH delta-sigma analog to digital data converter." Diss., The archival copy of this thesis can be found at SOAR (password protected), 2006. http://soar.wichita.edu/dspace/handle/10057/568.

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Thesis (M.S.)--Wichita State University, College of Engineering, Dept. of Electrical and Computer Engineering.
"August 2006." Title from PDF title page (viewed on May 2, 2007). Thesis adviser: Larry D. Paarmann. Includes bibliographic references (leaves 41-43).
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3

Baig, Shams Javid Paarmann Larry D. "RC implementation of an audio frequency band fourth-order Chebyshev type II Delta-Sigma analog to digital data converter." Diss., A link to full text of this thesis in SOAR, 2006. http://soar.wichita.edu/dspace/handle/10057/614.

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Thesis (M.S.)--Wichita State University, College of Engineering, Dept. of Electrical and Computer Engineering.
UMI Number: 1443931 "December 2006." Title from PDF title page (viewed on Sept. 18, 2007). Thesis adviser: Larry D. Paarmann. Includes bibliographic references (leaves 37-38).
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4

Iuzzolino, Ricardo Javier [Verfasser], and Meinhard [Akademischer Betreuer] Schilling. "Josephson Waveforms Characterization of a Sigma-Delta Analog-to-Digital Converter for Data Acquisition in Metrology / Ricardo Javier Iuzzolino ; Betreuer: Meinhard Schilling." Braunschweig : Technische Universität Braunschweig, 2011. http://d-nb.info/1175824739/34.

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5

Yu, Xinyu. "High-temperature Bulk CMOS Integrated Circuits for Data Acquisition." Case Western Reserve University School of Graduate Studies / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=case1144420886.

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6

Kook, Se Hun. "Low-cost testing of high-precision analog-to-digital converters." Diss., Georgia Institute of Technology, 2011. http://hdl.handle.net/1853/41170.

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The advent of deep submicron technology has resulted in a new generation of highly integrated mixed-signal system-on-chips (SoCs) and system-on-packages (SoPs). As a result, the cost of electrical products has sharply declined, and their performance has greatly improved. However, a testing throughput still remains one of the major contribution factors to final cost of the electrical products. In addition, highly precise and robust test methods and equipment are needed to promise non-defective products to customers. Hence, the testing is a critical part of the manufacturing process in the semiconductor industry. Testing such highly integrated systems and devices requires high-performance and high-cost equipment. Analog-to-digital converters (A/D converters) are the largest volume mixed-signal circuits, and they play a key role in communication between the analog and digital domains in many mixed-signal systems. Due to the increasing complexity of the mixed-signal systems and the availability of the new generations of highly integrated systems, reliable and robust data conversion schemes are necessary for many mixed-signal designs. Many applications such as telecommunications, instrumentation, sensing, and data acquisition have demanded data converters that support ultra high-speed, wide-bandwidths, and high-precision with excellent dynamic performance and low-noise. However, as resolutions and speeds in the A/D converters increase, testing becomes much harder and more expensive. In this research work, low-cost test strategies to reduce overall test cost for high-precision A/D converters are developed. The testing of data converters can be classified as dynamic (or alternating current (AC)) performance test and static (or direct current (DC)) performance test [1]. In the dynamic specification test, a low-cost test stimulus is generated using an optimization algorithm to stimulate high-precision sigma-delta A/D converters under test. Dynamic specifications are accurately predicted in two different ways using concepts of an alternate-based test and a signature-based test. For this test purpose, the output pulse stream of a sigma-delta modulator is made observable and useful. This technique does not require spectrally pure input signals, so the test cost can be reduced compared to a conventional test method. In addition, two low-cost test strategies for static specification testing of high-resolution A/D converters are developed using a polynomial-fitting method. The cost of testing can be significantly reduced as a result of the measurement of fewer samples than a conventional histogram test. While one test strategy needs no expensive high-precision stimulus generator, which can reduce the test cost, the other test strategy finds the optimal set of test-measurement points for the maximum fault coverage, which can use minimum-code measurement as a production test solution. The theoretical concepts of the proposed test strategies are developed in software simulation and validated by hardware experiments using a commercially available A/D converter and designed converters on printed circuit board (PCB). This thesis provides low-cost test solutions for the high-resolution A/D converters.
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7

Liu, Xiyang. "Measurement of Delta-Sigma Converter." Thesis, Högskolan i Gävle, Avdelningen för elektronik, matematik och naturvetenskap, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:hig:diva-9701.

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With today’s technology, digital signal processing plays a major role. It is used widely in many applications. Many applications require high resolution in measured data to achieve a perfect digital processing technology. The key to achieve high resolution in digital processing systems is analog-to-digital converters. In the market, there are many types ADC for different systems. Delta-sigma converters has high resolution and expected speed because it’s special structure. The signal-to-noise-and-distortion (SINAD) and total harmonic distortion (THD) are two important parameters for delta-sigma converters. The paper will describe the theory of parameters and test method.
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8

Lok, Chi Fung. "Multimode switched-capacitor delta-sigma analog-to-digital converter /." View abstract or full-text, 2007. http://library.ust.hk/cgi/db/thesis.pl?ECED%202007%20LOK.

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9

Ertan, Sevgi 1976. "Comparison of two bandpass delta-sigma A/D converter architectures." Thesis, Massachusetts Institute of Technology, 2000. http://hdl.handle.net/1721.1/86435.

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10

Pan, Yaobin, and Xizhuo Li. "Design and Implementation of Sigma-Delta Converter : in Oversampling frequency." Thesis, Linnéuniversitetet, Institutionen för fysik och elektroteknik (IFE), 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:lnu:diva-53052.

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Nowadays, Sigma-Delta analog-to-digital converters have been widely used in the technology of analog-to-digital conversion. It depends on the merits that the approach of Sigma-Delta has. The signal converted by oversampling is precise and well-suited in signal processing systems.This thesis mainly focuses on the principles and simulations of fundamental first-order Sigma-Delta converter, and some brief introductions about other Sigma-Delta converters.The main researches of this thesis are as follows: (1)This thesis shows not only the path about development of technology of different ADCs, but also the features and principles of these ADCs and their structures. (2)The thesis discusses how the technologies of oversampling and noise shaping are used in Sigma-Delta analog-to-digital conversion. (3)Illustrate different orders Sigma-Delta converters in different bits and their advantages and disadvantages, respectively. (4)The simulation is given in Matlab(Simulink). Typical first-order SigmaDelta converter is simulated with additional noise which will impact the input signal when implement.
Sigma-Delta Converter
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Книги з теми "Delta sigma data converter"

1

Schreier, Richard, Shanthi Pavan, and Gabor C. Temes. Understanding Delta-Sigma Data Converters. Hoboken, NJ, USA: John Wiley & Sons, Inc., 2017. http://dx.doi.org/10.1002/9781119258308.

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2

1929-, Temes Gabor C., ed. Understanding delta-sigma data converters. Piscataway, NJ: IEEE Press, 2005.

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3

C, Candy James, Temes Gabor C. 1929-, Institute of Electrical and Electronics Engineers., and IEEE Circuits and Systems Society., eds. Oversampling delta-sigma data converters: Theory, design, and simulation. Piscataway, NJ: IEEE Press, 1992.

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4

Casier, Herman. Analog Circuit Design: Robust Design, Sigma Delta Converters, RFID. Dordrecht: Springer Science+Business Media B.V., 2011.

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5

Geerts, Yves. Design of multi-bit delta-sigma A/D converters. Boston: Kluwer Academic Publishers, 2002.

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6

Dufort, Benoit. Analog test signal generation using periodic [sigma delta]-encoded data streams. New York: Springer Science+Business Media, 2000.

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7

1959-, Roberts Gordon W., ed. Analog test signal generation using periodic [sigma delta]-encoded data streams. Boston: Kluwer Academic, 2000.

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8

Maskey, Liam. Digital filtering of sigma-delta modulator data using FPGA's. (s.l: The Author), 2000.

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9

Chik, Raymond Y. V. Building blocks for a gallium arsenide realization of a sigma-delta analog-to-digital converter. Ottawa: National Library of Canada = Bibliothèque nationale du Canada, 1992.

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10

Morgado, Alonso. Nanometer CMOS Sigma-Delta Modulators for Software Defined Radio. New York, NY: Springer Science+Business Media, LLC, 2012.

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Частини книг з теми "Delta sigma data converter"

1

Gerfers, F., Y. Manoli, and M. Ortmanns. "Continuous-Time Sigma-Delta for IF." In CMOS Telecom Data Converters, 345–77. Boston, MA: Springer US, 2003. http://dx.doi.org/10.1007/978-1-4757-3724-0_10.

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2

Fernández, Francisco V., Rocío del Río, Rafael Castro-López, Oscar Guerra, Fernando Medeiro, and Belén Pérez-Verdú. "Design Methodologies for Sigma-Delta Converters." In CMOS Telecom Data Converters, 523–59. Boston, MA: Springer US, 2003. http://dx.doi.org/10.1007/978-1-4757-3724-0_15.

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3

Kester, Walt, and James Bryant. "Sigma-Delta Converters." In Data Conversion Handbook, 231–54. Elsevier, 2005. http://dx.doi.org/10.1016/b978-075067841-4/50017-8.

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4

"Delta-Sigma DACs." In Understanding Delta-Sigma Data Converters, 425–50. Hoboken, NJ, USA: John Wiley & Sons, Inc., 2017. http://dx.doi.org/10.1002/9781119258308.ch13.

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5

"A 16Bit 4th Order NoiseShaping D/A Converter." In Oversampling Delta-Sigma Data Converters, 482–85. IEEE, 2009. http://dx.doi.org/10.1109/9780470545461.ch61.

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"An l8b Oversamplinq A/D Converter for Digital Audio." In Oversampling Delta-Sigma Data Converters, 340–41. IEEE, 2009. http://dx.doi.org/10.1109/9780470545461.ch43.

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"A CMOS Stereo 16Bit DIA Converter for Digital Audio." In Oversampling Delta-Sigma Data Converters, 486–90. IEEE, 2009. http://dx.doi.org/10.1109/9780470545461.ch62.

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8

Ndjountche, Tertulien. "Delta-Sigma Data Converters." In CMOS Analog Integrated Circuits, 651–768. CRC Press, 2017. http://dx.doi.org/10.1201/b10943-12.

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"An Oversampling AnalogtoDigital Converter Topology for HighResolution Signal Acquisition Systems." In Oversampling Delta-Sigma Data Converters, 184–91. IEEE, 2009. http://dx.doi.org/10.1109/9780470545461.ch16.

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"Constraints Analysis for Oversampling AtoD Converter Structures on VLSl Implementation." In Oversampling Delta-Sigma Data Converters, 270–75. IEEE, 2009. http://dx.doi.org/10.1109/9780470545461.ch33.

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Тези доповідей конференцій з теми "Delta sigma data converter"

1

Temes, Gabor C. "Multicell Delta-Sigma Data Converters." In 2006 49th IEEE International Midwest Symposium on Circuits and Systems. IEEE, 2006. http://dx.doi.org/10.1109/mwscas.2006.382184.

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2

Brandt, Brian, and Gerhard Mitteregger. "Session 8 overview: Delta-sigma converters: Data converters subcommittee." In 2012 IEEE International Solid-State Circuits Conference (ISSCC). IEEE, 2012. http://dx.doi.org/10.1109/isscc.2012.6177127.

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3

Lai, Yen-Po, Hao-Hsuan Chang, and Tai-Cheng Lee. "An Asynchronous Zero-Crossing-Based Incremental Delta-Sigma Converter." In 2022 International Symposium on VLSI Design, Automation and Test (VLSI-DAT). IEEE, 2022. http://dx.doi.org/10.1109/vlsi-dat54769.2022.9768072.

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4

Yi Ke, J. Craninckx, and G. Gielen. "A design methodology for fully reconfigurable Delta-Sigma data converters." In 2009 Design, Automation & Test in Europe Conference & Exhibition (DATE'09). IEEE, 2009. http://dx.doi.org/10.1109/date.2009.5090879.

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5

de Carvalho, Dionisio, and J. Navarro. "A power optimized decimator for sigma-delta data converters." In 2013 IEEE 4th Latin American Symposium on Circuits and Systems (LASCAS). IEEE, 2013. http://dx.doi.org/10.1109/lascas.2013.6519018.

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6

Kundu, auSandipan, auSubhanshu Gupta, auDavid J. Allstot, and auJeyanandh Paramesh. "DAC mismatch shaping for quadrature sigma-delta data converters." In 2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS). IEEE, 2015. http://dx.doi.org/10.1109/mwscas.2015.7282149.

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Akram, Waqas, and Earl E. Swartzlander. "Tunable mismatch shaping for quadrature bandpass delta-sigma data converters." In 2010 IEEE Workshop On Signal Processing Systems (SiPS). IEEE, 2010. http://dx.doi.org/10.1109/sips.2010.5624787.

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8

Roberts, Gordon W. "Test Methods For Sigma-Delta Data Converters and Related Devices." In the twenty-first annual symposium. New York, New York, USA: ACM Press, 2008. http://dx.doi.org/10.1145/1404371.1404375.

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Duggal, Ashwin, Sameer Sonkusale, and John Lachappelle. "Calibration of delta-sigma data converters in synchronous demodulation sensing applications." In 2009 IEEE Sensors. IEEE, 2009. http://dx.doi.org/10.1109/icsens.2009.5398470.

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Del Signore, Bruce P., Donald A. Kerth, Eric J. Swanson, Navdeep S. Sooch, and David K. Welland. "Monolithic 20‐bit delta‐sigma A/D converter suitable for use in portable seismic data capture instrumentation." In SEG Technical Program Expanded Abstracts 1989. Society of Exploration Geophysicists, 1989. http://dx.doi.org/10.1190/1.1889707.

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