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Статті в журналах з теми "Computers – Circuits – Performance"
Blume-Kohout, Robin, and Kevin C. Young. "A volumetric framework for quantum computer benchmarks." Quantum 4 (November 15, 2020): 362. http://dx.doi.org/10.22331/q-2020-11-15-362.
Повний текст джерелаChilds, Andrew M., Dmitri Maslov, Yunseong Nam, Neil J. Ross, and Yuan Su. "Toward the first quantum simulation with quantum speedup." Proceedings of the National Academy of Sciences 115, no. 38 (September 6, 2018): 9456–61. http://dx.doi.org/10.1073/pnas.1801723115.
Повний текст джерелаFan, Yi, Jie Liu, Xiongzhi Zeng, Zhiqian Xu, Honghui Shang, Zhenyu Li, and Jinlong Yang. "Q<sup>2</sup>Chemistry: A quantum computation platform for quantum chemistry." JUSTC 52, no. 12 (2022): 2. http://dx.doi.org/10.52396/justc-2022-0118.
Повний текст джерелаStamatopoulos, Nikitas, Daniel J. Egger, Yue Sun, Christa Zoufal, Raban Iten, Ning Shen, and Stefan Woerner. "Option Pricing using Quantum Computers." Quantum 4 (July 6, 2020): 291. http://dx.doi.org/10.22331/q-2020-07-06-291.
Повний текст джерелаCzarnik, Piotr, Andrew Arrasmith, Patrick J. Coles, and Lukasz Cincio. "Error mitigation with Clifford quantum-circuit data." Quantum 5 (November 26, 2021): 592. http://dx.doi.org/10.22331/q-2021-11-26-592.
Повний текст джерелаLiu, Xiaonan, Ming He, Junchao Wang, Haoshan Xie, and Chenyan Zhao. "Automated Quantum Volume Test." Journal of Physics: Conference Series 2221, no. 1 (May 1, 2022): 012029. http://dx.doi.org/10.1088/1742-6596/2221/1/012029.
Повний текст джерелаAaron D’costa, Mr, Dr Abdul Razak, and Dr Shazia Hasan. "Analysis and comparison of fast multiplier circuits based on different parameters." International Journal of Engineering & Technology 7, no. 3 (June 26, 2018): 1189. http://dx.doi.org/10.14419/ijet.v7i3.12945.
Повний текст джерелаSong, Gyeongju, Kyungbae Jang, Hyunji Kim, and Hwajeong Seo. "A Parallel Quantum Circuit Implementations of LSH Hash Function for Use with Grover’s Algorithm." Applied Sciences 12, no. 21 (October 27, 2022): 10891. http://dx.doi.org/10.3390/app122110891.
Повний текст джерелаBravyi, Sergey, Dan Browne, Padraic Calpin, Earl Campbell, David Gosset, and Mark Howard. "Simulation of quantum circuits by low-rank stabilizer decompositions." Quantum 3 (September 2, 2019): 181. http://dx.doi.org/10.22331/q-2019-09-02-181.
Повний текст джерелаOu, Qiao-Feng, Bang-Shu Xiong, Lei Yu, Jing Wen, Lei Wang, and Yi Tong. "In-Memory Logic Operations and Neuromorphic Computing in Non-Volatile Random Access Memory." Materials 13, no. 16 (August 10, 2020): 3532. http://dx.doi.org/10.3390/ma13163532.
Повний текст джерелаДисертації з теми "Computers – Circuits – Performance"
Md, Ali Sawal Hamid. "System level performance and yield optimisation for analogue integrated circuits." Thesis, University of Southampton, 2009. https://eprints.soton.ac.uk/69724/.
Повний текст джерелаShahidipour, Hamed. "A study on the effects of variability on performance of CNFET based digital circuits." Thesis, University of Southampton, 2012. https://eprints.soton.ac.uk/364216/.
Повний текст джерелаLowe, Jeffrey. "A high-performance, hybrid wave-pipelined linear feedback shift register with skew tolerant clocks." Online access for everyone, 2004. http://www.dissertations.wsu.edu/Thesis/Summer2004/j%5Flowe%5F072104.pdf.
Повний текст джерелаBingham, Philip R. "The effect of message length distribution on the performance of fully connected switches." Diss., Georgia Institute of Technology, 1999. http://hdl.handle.net/1853/15389.
Повний текст джерелаAppleton, Samuel Scott. "Performance-directed design of asynchronous VLSI systems /." Title page, contents and abstract only, 1997. http://web4.library.adelaide.edu.au/theses/09PH/09pha651.pdf.
Повний текст джерелаKhasawneh, Shadi Turki. "Low-power high-performance register file design for chip multiprocessors." Diss., Online access via UMI:, 2006.
Знайти повний текст джерелаSerrano, Guillermo J. "High Performance Analog Circuit Design Using Floating-Gate Techniques." Diss., Georgia Institute of Technology, 2007. http://hdl.handle.net/1853/19819.
Повний текст джерелаQiao, Hao. "Sparse hierarchical model order reduction for high speed interconnects." Thesis, McGill University, 2009. http://digitool.Library.McGill.CA:8881/R/?func=dbin-jump-full&object_id=32359.
Повний текст джерелаMa, Albert. "Circuits for high-performance low-power VLSI logic." Thesis, Massachusetts Institute of Technology, 2006. http://hdl.handle.net/1721.1/37906.
Повний текст джерелаIncludes bibliographical references (p. 85-88).
The demands of future computing, as well as the challenges of nanometer-era VLSI design, require new digital logic techniques and styles that are simultaneously high performance, energy efficient, and robust to noise and variation. We propose a new family of logic styles called Preset Skewed Static Logic (PSSL). PSSL bridges the gap between the two main logic styles, static CMOS logic and domino logic, occupying an intermediate region in the energy-delay-robustness space between the two. PSSL is better than domino in terms of energy and robustness, and is better than static CMOS in terms of delay. PSSL works by partially overlapping the execution of consecutive iterations through speculative evaluation. This is accomplished by presetting nodes at register boundaries before input arrival.
by Albert Ma.
Ph.D.
Weyer, Daniel J. "TRADEOFFS BETWEEN PERFORMANCE AND RELIABILITY IN INTEGRATED CIRCUITS." Case Western Reserve University School of Graduate Studies / OhioLINK, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=case155508829933554.
Повний текст джерелаКниги з теми "Computers – Circuits – Performance"
1943-, Elmasry Mohamed I., ed. Optimal VLSI architectural synthesis: Area, performance, and testability. Boston: Kluwer Academic Publishers, 1992.
Знайти повний текст джерелаM, Schoen Joel, ed. Performance and fault modeling with VHDL. Englewood Cliffs, N.J: Prentice Hall, 1992.
Знайти повний текст джерелаRoermund, Arthur H. M. van, Casier Herman, and SpringerLink (Online service), eds. Analog Circuit Design: High-speed Clock and Data Recovery, High-performance Amplifiers, Power Management. Dordrecht: Springer Science+Business Media B.V., 2009.
Знайти повний текст джерелаHigh-performance ASIC design: Using synthesizable domino logic in an ASIC flow. Cambridge: Cambridge University Press, 2008.
Знайти повний текст джерела1941-, Venetsanopoulos A. N., ed. Artificial neural networks: Learning algorithms, performance evaluation, and applications. Boston: Kluwer Academic, 1993.
Знайти повний текст джерелаKrishnaswamy, Smita. Design, Analysis and Test of Logic Circuits Under Uncertainty. Dordrecht: Springer Netherlands, 2013.
Знайти повний текст джерелаG, Oklobdzija Vojin, ed. Digital system clocking: High-performance and low-power aspects. New York: IEEE, 2003.
Знайти повний текст джерелаDavid, Hutchison. Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation: 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008. Revised Selected Papers. Berlin, Heidelberg: Springer Berlin Heidelberg, 2009.
Знайти повний текст джерелаBraulio, García-Cámara, Prieto Manuel, Ruggiero Martino, Sicard Gilles, and SpringerLink (Online service), eds. Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation: 21st International Workshop, PATMOS 2011, Madrid, Spain, September 26-29, 2011. Proceedings. Berlin, Heidelberg: Springer-Verlag GmbH Berlin Heidelberg, 2011.
Знайти повний текст джерелаOchotta, Emil S. Practical Synthesis of High-Performance Analog Circuits. Boston, MA: Springer US, 1998.
Знайти повний текст джерелаЧастини книг з теми "Computers – Circuits – Performance"
Raoufifard, Somaye, Behnam Ghavami, Mehrdad Najibi, and Hossein Pedram. "Performance Enhancement of Asynchronous Circuits." In Communications in Computer and Information Science, 671–78. Berlin, Heidelberg: Springer Berlin Heidelberg, 2008. http://dx.doi.org/10.1007/978-3-540-89985-3_82.
Повний текст джерелаDao, Hoang Q., Bart R. Zeydel, and Vojin G. Oklobdzija. "Energy Optimization of High-Performance Circuits." In Lecture Notes in Computer Science, 399–408. Berlin, Heidelberg: Springer Berlin Heidelberg, 2003. http://dx.doi.org/10.1007/978-3-540-39762-5_46.
Повний текст джерелаZlatanovici, Radu, and Borivoje Nikolić. "Power – Performance Optimization for Custom Digital Circuits." In Lecture Notes in Computer Science, 404–14. Berlin, Heidelberg: Springer Berlin Heidelberg, 2005. http://dx.doi.org/10.1007/11556930_42.
Повний текст джерелаChattopadhyay, Ankush, Chayanika Bose, and K. Sarkar Chandan. "Performance and Circuit Analysis of Independent Gate FinFET." In Computers and Devices for Communication, 427–33. Singapore: Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-15-8366-7_63.
Повний текст джерелаRius, Josep, José Pineda, and Maurice Meijer. "An Activity Monitor for Power/Performance Tuning of CMOS Digital Circuits." In Lecture Notes in Computer Science, 187–96. Berlin, Heidelberg: Springer Berlin Heidelberg, 2005. http://dx.doi.org/10.1007/11556930_20.
Повний текст джерелаTajalli, Armin, Massimo Alioto, Elizabeth J. Brauer, and Yusuf Leblebici. "Improving the Power-Delay Performance in Subthreshold Source-Coupled Logic Circuits." In Lecture Notes in Computer Science, 21–30. Berlin, Heidelberg: Springer Berlin Heidelberg, 2009. http://dx.doi.org/10.1007/978-3-540-95948-9_3.
Повний текст джерелаRaji, Mohsen, Behnam Ghavami, Hamid R. Zarandi, and Hossein Pedram. "Process Variation Aware Performance Analysis of Asynchronous Circuits Considering Spatial Correlation." In Lecture Notes in Computer Science, 5–15. Berlin, Heidelberg: Springer Berlin Heidelberg, 2010. http://dx.doi.org/10.1007/978-3-642-11802-9_5.
Повний текст джерелаJadon, Ekta, and Shyam Akashe. "Performance Analysis and Comparison of Low Power Various Full Adder Circuits." In Communications in Computer and Information Science, 312–21. Singapore: Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-16-8896-6_25.
Повний текст джерелаTao, Jun, Fa Wang, Paolo Cachecho, Wangyang Zhang, Shupeng Sun, Xin Li, Rouwaida Kanj, Chenjie Gu, and Xuan Zeng. "Large-Scale Circuit Performance Modeling by Bayesian Model Fusion." In Machine Learning in VLSI Computer-Aided Design, 403–22. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-04666-8_14.
Повний текст джерелаHarjani, Ramesh, and Jianfeng Shao. "Feasibility and Performance Region Modeling of Analog and Digital Circuits." In The Kluwer International Series in Engineering and Computer Science, 23–43. Boston, MA: Springer US, 1996. http://dx.doi.org/10.1007/978-1-4613-1405-9_3.
Повний текст джерелаТези доповідей конференцій з теми "Computers – Circuits – Performance"
Zatsarinny, Aleksandr, Yuriy Stepchenkov, Yuriy Diachenko, and Yuriy Rogdestvenski. "SELF-TIMED CIRCUITS AS A BASIS FOR DEVELOPING NEXT GENERATION HIGH-RELIABLE HIGH-PERFORMANCE COMPUTERS." In Mathematical modeling in materials science of electronic component. LLC MAKS Press, 2020. http://dx.doi.org/10.29003/m1535.mmmsec-2020/114-116.
Повний текст джерелаPaliwal, Wasundhara D., P. V. S. Shastry, and Sudarshan Dighade. "High performance using synchronous elastic circuits with lower overheads." In 2014 International Conference on Advances in Electronics, Computers and Communications (ICAECC). IEEE, 2014. http://dx.doi.org/10.1109/icaecc.2014.7002453.
Повний текст джерелаThakur, Ravikant, Ajay Kumar Dadoria, and Tarun Kumar Gupta. "Comparative analysis of various Domino logic circuits for better performance." In 2014 International Conference on Advances in Electronics, Computers and Communications (ICAECC). IEEE, 2014. http://dx.doi.org/10.1109/icaecc.2014.7002416.
Повний текст джерелаSau, Swagata Saha, and Rajat Kumar Pal. "An efficient high performance parallel algorithm to yield reduced wire length VLSI circuits." In 2012 International Conference on Computers and Devices for Communication (CODEC). IEEE, 2012. http://dx.doi.org/10.1109/codec.2012.6509278.
Повний текст джерелаHo, Hoang Thien Long, Anh Tien Doan, Duy Tinh Nguyen, and Hoang-Anh Pham. "A LoRaWanbased IoT Testbed for Performance Investigation." In 2022 37th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC). IEEE, 2022. http://dx.doi.org/10.1109/itc-cscc55581.2022.9894925.
Повний текст джерелаBumrungkit, Acharaporn, Watid Phakphisut, and Pornchai Supnithi. "Preliminary results of EPB impact on GBAS performance." In 2019 34th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC). IEEE, 2019. http://dx.doi.org/10.1109/itc-cscc.2019.8793387.
Повний текст джерелаHan, Sangwoo, Tae Yang Jeong, and Eui-Young Chung. "Multi-node Power/Performance Modeling for HPC System." In 2019 34th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC). IEEE, 2019. http://dx.doi.org/10.1109/itc-cscc.2019.8793388.
Повний текст джерелаSrisomboon, Kanabadee, and Wilaiporn Lee. "Performance Evaluation of Spectrum Sensing Under PU Random Access." In 2022 37th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC). IEEE, 2022. http://dx.doi.org/10.1109/itc-cscc55581.2022.9895108.
Повний текст джерелаChoi, Yuho, Byungguk Kim, and Seon Wook Kim. "Performance Analysis of PointPillars on CPU and GPU Platforms." In 2021 36th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC). IEEE, 2021. http://dx.doi.org/10.1109/itc-cscc52171.2021.9611297.
Повний текст джерелаSong, W. S., M. M. Vai, and H. T. Nguyen. "High-performance low-power bit-level systolic array signal processor with low-threshold dynamic logic circuits." In Conference Record. Thirty-Fifth Asilomar Conference on Signals, Systems and Computers. IEEE, 2001. http://dx.doi.org/10.1109/acssc.2001.986895.
Повний текст джерела