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Статті в журналах з теми "CMOS Device and Integration":
Shawkat, Mst Shamim Ara, Mohammad Habib Ullah Habib, Md Sakib Hasan, Mohammad Aminul Haque, and Nicole McFarlane. "Perimeter Gated Single Photon Avalanche Diodes in Sub-Micron and Deep-Submicron CMOS Processes." International Journal of High Speed Electronics and Systems 27, no. 03n04 (September 2018): 1840018. http://dx.doi.org/10.1142/s0129156418400189.
Krupar, Joerg, Heiko Hauswald, and Ronny Naumann. "A Substrate Current Less Control Method for CMOS Integration of Power Bridges." Advances in Power Electronics 2010 (September 23, 2010): 1–11. http://dx.doi.org/10.1155/2010/909612.
Kogut, Igor T., Victor I. Holota, Anatoly Druzhinin, and V. V. Dovhij. "The Device-Technological Simulation of Local 3D SOI-Structures." Journal of Nano Research 39 (February 2016): 228–34. http://dx.doi.org/10.4028/www.scientific.net/jnanor.39.228.
Leenheer, Andrew, Connor Halsey, Daniel Ward, Deanna Campbell, John S. Mincey, Evan M. Anderson, Scott W. Schmucker, et al. "Atomic-scale Dopant Integration During CMOS Device Fabrication." ECS Meeting Abstracts MA2021-02, no. 30 (October 19, 2021): 918. http://dx.doi.org/10.1149/ma2021-0230918mtgabs.
Huey, Sidney, Balaji Chandrasekaran, Doyle Bennett, Stan Tsai, Kun Xu, Jun Qian, Siva Dhandapani, Jeff David, Bogdan Swedek, and Lakshmanan Karuppiah. "CMP Process Control for Advanced CMOS Device Integration." ECS Transactions 44, no. 1 (December 15, 2019): 543–52. http://dx.doi.org/10.1149/1.3694367.
Perez-Bosch Quesada, E., E. Perez, M. Kalishettyhalli Mahadevaiah, and C. Wenger. "Memristive-based in-memory computing: from device to large-scale CMOS integration." Neuromorphic Computing and Engineering 1, no. 2 (November 18, 2021): 024006. http://dx.doi.org/10.1088/2634-4386/ac2cd4.
Kitchen, Jennifer, Soroush Moallemi, and Sumit Bhardwaj. "Multi-chip module integration of Hybrid Silicon CMOS and GaN Technologies for RF Transceivers." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2019, DPC (January 1, 2019): 000339–82. http://dx.doi.org/10.4071/2380-4491-2019-dpc-presentation_tp1_010.
Tabata, Toshiyuki, Fabien Rozé, Louis Thuries, Sébastien Halty, Pierre-Edouard Raynal, Imen Karmous, and Karim Huet. "Recent Progresses and Perspectives of UV Laser Annealing Technologies for Advanced CMOS Devices." Electronics 11, no. 17 (August 23, 2022): 2636. http://dx.doi.org/10.3390/electronics11172636.
Pan, James N. "Chromatic and Panchromatic Nonlinear Optoelectronic CMOSFETs for CMOS Image Sensors, Laser Multiplexing, Computing, and Communication." MRS Advances 5, no. 37-38 (2020): 1965–74. http://dx.doi.org/10.1557/adv.2020.273.
Ostling, Mikael, and Per-Erik Hellstrom. "(Invited) Sequential 3D Integration of Ge Transistors on Si CMOS." ECS Meeting Abstracts MA2023-02, no. 30 (December 22, 2023): 1511. http://dx.doi.org/10.1149/ma2023-02301511mtgabs.
Дисертації з теми "CMOS Device and Integration":
Darwish, Mohamed. "Graphene Devices for Beyond-CMOS Heterogeneous Integration." Research Showcase @ CMU, 2017. http://repository.cmu.edu/dissertations/1072.
Hållstedt, Julius. "Integration of epitaxial SiGe(C) layers in advanced CMOS devices /." Stockholm : Kungliga Tekniska högskolan, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-4498.
Hållstedt, Julius. "Integration of epitaxial SiGe(C) layers in advanced CMOS devices." Doctoral thesis, KTH, Mikroelektronik och tillämpad fysik, MAP, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-4498.
QC 20100715
Pacella, Nan Yang. "Platform for monolithic integration of III-V devices with Si CMOS technology." Thesis, Massachusetts Institute of Technology, 2012. http://hdl.handle.net/1721.1/76119.
Cataloged from PDF version of thesis.
Includes bibliographical references (p. 169-165).
Monolithic integration of III-V compound semiconductors and Si complementary metal-oxide- semiconductor (CMOS) enables the creation of advanced circuits with new functionalities. In order to merge the two technologies, compatible substrate platforms and processing approaches must be developed. The Silicon on Lattice Engineered Silicon (SOLES) substrate allows monolithic integration. It is a Si substrate with embedded III-V template layer, which supports epitaxial IIIV device growth, consistent with present II-V technology. The structure is capped with a silicon-on-insulator (SOI) layer, which enables processing of CMOS devices. The processes required for fabricating and utilizing SOLES wafers which have Ge or InP as the III-V template layers are explored. Allowable thermal budgets are important to consider because the substrate must withstand the thermal budget of all subsequent device processing steps. The maximum processing temperature of Ge SOLES is found to be limited by its melting point. However, Ge diffuses through the buried Si0 2 and must be contained. Solutions include 1) limiting device processing thermal budgets, 2) improving buried silicon dioxide quality and 3) incorporating a silicon nitride diffusion barrier. InP SOLES substrates are created using wafer bonding and layer transfer of silicon, SOI and InP-on-Si wafers, established using a two-step growth method. Two different InP SOLES structures are demonstrated and their allowable thermal budgets are investigated. The thermal budgets appear to be limited by low quality silicon dioxide used for wafer bonding. For ultimate integration, parallel metallization of the III-V and CMOS devices is sought. A method of making ohmic contact to III-V materials through Si encapsulation layers, using Si CMOS technology, is established. The metallurgies and electrical characteristics of nickel silicide structures on Si/III-V films are investigated and the NiSi/Si/III-V structure is found to be optimal. This structure is composed of a standard NiSi/Si interface and novel Si/III-V interface. Specific contact resistivity of the double hetero-interface stack can be tuned by controlling Si/IIIV band alignments at the epitaxial growth interface. P-type Si/GaAs interfaces and n-type Si/InGaAs interfaces create ohmic contacts with the lowest specific contact resistivity and present viable structures for integration. A Si-encapsulated GaAs/AlGaAs laser with NiSi front-side contact is demonstrated and confirms the feasibility of these contact structures.
by Nan Yang Pacella.
Ph.D.
London, Joanna M. 1974. "Wafer bonding for monolithic integration of Si CMOS VLSI electronics with III-V optoelectronic devices." Thesis, Massachusetts Institute of Technology, 1998. http://hdl.handle.net/1721.1/45498.
Includes bibliographical references (p. 90-91).
GaAs-on-silicon epitaxy techniques as well as wafer bonding GaAs to Si, have been developed to overcome lattice mismatch in order to integrate optoelectronic and Si devices. However, the thermal expansion differences between these materials continues to be a limitation in using either of these approaches. After recognizing that Si devices, such as MOSFETs, are intrinsically thin and relatively strain tolerant, while optoelectronic devices, such as LEDs and lasers, are thick and very strain sensitive, this research was based on developing a better approach which involved bonding thin Si layers to thick GaAs substrates with various dielectric layers as the interface, to produce silicon-on-gallium arsenide (SonG) wafers. Such wafers are suitable for the fabrication of Si SOICMOS electronics and the subsequent monolithic integration of high performance optoelectronic devices. Future goals for this work include bonding fully processed SOI-CMOS wafers to the GaAs, rather than silicon wafers containing no electronics. With the successful development of SonG techniques for monolithic integration, it will be possible to use full-wafer and batch processing techniques for the production of sophisticated economically viable optoelectronic integrated circuits.
by Joanna M. London.
S.M.
Riverola, Borreguero Martín. "Micro and Nano-electro-mechanical devices in the CMOS back end and their applications." Doctoral thesis, Universitat Autònoma de Barcelona, 2017. http://hdl.handle.net/10803/458694.
Recently, several new emerging devices are starting to be explored because the traditional down-scaling approach of the complementary metal-oxide-semiconductor (CMOS) technology (often called “More Moore”) is reaching fundamental limits; mainly due to non-zero transistor off-state leakage. This brand-new domain that goes beyond the boundaries of Moore’s law is commonly named ``More than Moore'' and is driving interest in new devices for information processing and memory, new technologies for heterogeneous integration of multiple functions, and new paradigms for system architecture. One of these new promising technologies for logic and information processing is the micro- and nanoelectromechanical (M/NEM) relay technology, because of its immeasurably low off-state leakage current and super-steep switching behavior. This dissertation proposes to explore the possibilities of leveraging the available layers of the commercial CMOS technology AMS 0.35 µm to implement M/NEM relays. Specifically, two different approaches are explored: in-plane actuated relays defined using solely the via layer, and torsional actuated relays formed with metal and via layers (usually named composite) while supported by vias. Both approaches are supported by the tungsten VIA3 layer, which includes key features such as high hardness, high melting point, low stress and resistance to hydrofluoric (HF) acid, since the mechanical structures are released in a maskless post-CMOS process based on a wet HF enchant. Based on the key structural features that the developed relays showed, MEMS resonators based on the VIA3 platform were also fabricated. In this dissertation, we also present a particular contribution involving the design and characterization of a dual-frequency oscillator that consist of such reliable torsional tungsten resonators and a high gain, low power and ultra-compact transimpedance amplifier (TIA). Finally and parallel to the main thread of this dissertation, RF MEMS switched capacitors are developed as a result of the collaboration with the semiconductor manufacturing enterprise SilTerra Malaysia Sdn. Bhd. These devices have the particularity of being fully integrated into the process flow of a low cost, commercial 180 nm CMOS technology (using the SilTerra MEMS-on-CMOS process platform).
Pearson, Brian (Brian Sung-Il). "Large grain Ge growth on amorphous substrates for CMOS back-end-of-line integration of active optoelectronic devices." Thesis, Massachusetts Institute of Technology, 2012. http://hdl.handle.net/1721.1/78240.
Cataloged from PDF version of thesis.
Includes bibliographical references (p. 97-104).
The electronic-photonic integrated circuit (EPIC) has emerged as a leading technology to surpass the interconnect bottlenecks that threaten to limit the progress of Moore's Law in microprocessors. Compared to conventional metal interconnects, photonic interconnects have the potential to increase bandwidth density while simultaneously reducing power consumption. However, photonic devices are orders of magnitude larger than electronic devices and therefore consume valuable substrate real estate. The ideal solution, in order to take advantage of optical interconnects without decreasing transistor counts, is to monolithically implement dense threedimensional integration of electronics and photonics. This involves moving the photonic devices off the substrate, and into the metal interconnect stack. Moving photonic devices into the interconnect stack imposes two fabrication limitations. First, the available thermal budget allowed for photonic device processing is limited to 450 °C. Second, the metal interconnects are embedded within amorphous dielectrics and therefore there is no crystalline seed to initiate epitaxial growth. This thesis addresses two major barriers for integration of photonics in the back end: (1) how to fabricate high quality Ge for active regions of optoelectronic devices while adhering to back-end processing constraints, and (2) how to couple optical power to these devices. First, an approach was developed to fabricate the active region of Ge-based optoelectronic devices. A new technique, known as two-dimensional geometrically confined lateral growth (2D GCLG), has demonstrated single crystalline Ge on an amorphous substrate. This thesis presents the first application of the 2D GCLG technique to fill a lithographically defined Si0 2 trench with large grain Ge, while adhering to back-end processing constraints. A modified design is then proposed to increases the yield of 2D GCLG structures. This trench filling technique is an integral step towards fabricating Ge-based optoelectronic devices that are capable of being integrated into the back-end of a microprocessor. Once it was established that high quality Ge trenches could be fabricated in the back-end, optical coupling to devices was addressed. For dense three-dimensional integration of photonic devices, vertical coupling between photonic planes is necessary. Therefore, this thesis begins with the design and simulation of vertical couplers. These couplers utilize evanescent coupling between two overlapping inversely tapered waveguides, which ensure efficient coupling due to optical impedance matching. These couplers are designed to exhibit coupling efficiencies in excess of 98.4%, equivalent to a 0.07 dB coupling loss. The technique of evanescent coupling between overlapping inverse tapers is then applied to electro-absorption modulators (EAMs). A design for low-loss evanescent coupling from a waveguide to a Ge EAM is modeled and optimized. The design implements lateral evanescent coupling from overlapping inverse taper structures. Simulation results show that the coupling efficiency into and out of the modulator can be as high as 99%, equivalent to a 0.04 dB coupling loss.
by Brian Pearson.
S.M.
Smith, Anderson. "Graphene-based Devices for More than Moore Applications." Doctoral thesis, KTH, Integrerade komponenter och kretsar, 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-188134.
QC 20160610
Bari, Mohammad Rezaul. "Fabrication, Characterization, and Modelling of Self-Assembled Silicon Nanostructure Vacuum Field Emission Devices." Thesis, University of Canterbury. Electrical and Computer Engineering, 2011. http://hdl.handle.net/10092/6601.
Dubreuil, Théophile. "Architecture 3D 1T1R innovante à base de RRAMs pour le calcul hyperdimensionnel." Electronic Thesis or Diss., Université Grenoble Alpes, 2023. http://www.theses.fr/2023GRALT085.
In the years to come, due to the insatiable need for data-intensive machine learning applications, a drastic expansion of computing power is required to confront a veritable “data deluge”. To meet this challenge, high-performance In-Memory-Computing (IMC) architectures require the development of novel storage devices that are also suited for local computations. In this context, this thesis work presents a novel 3D 1T1R memory array derived from vertically stacked-nanosheet technology, which is used for Hyperdimensional Computing (HDC), an error-resilient and highly parallel brain-inspired computing paradigm. Firstly, the IMC paradigm can greatly benefit from novel 3D non-volatile memory (NVM) architectures which increase the density and the computing performances. However, the fabrication challenges and parasitics can greatly limit the potential benefits of these architectures. With the 3D 1T1R technology, made by coupling new disruptive gate-independent stacked-nanosheets with drain-based RRAM cells, we show that some of these issues can be overcome, thus leading to high-density 3D NVM arrays. We demonstrate various technological modules necessary for the fabrication of 3D 1T1R structures. Devices are fabricated and electrically characterized for both storage and computing applications. In particular, functional MEOL drain-based RRAM cells are demonstrated with a doped-Si bottom electrode for various types of selector technologies. Finally, we propose a full-IMC architecture of HDC to take advantage of the 3D 1T1R structure. Different hardware implementations are proposed and compared with SPICE simulations. We also show with software-based simulations that language and gesture recognition can be realistically performed with our 3D 1T1R implementation
Книги з теми "CMOS Device and Integration":
Chen, John Y. CMOS devices and technology for VLSI. Englewood Cliffs, N.J: Prentice Hall, 1990.
Madrid, Philip E. Device design and process window analysis of a deep submicron CMOS VLSI technology. Reading, Mass: Addison-Wesley, 1992.
Laconte, J. Micromachined thin-film sensors for SOI-CMOS co-integration. New York: Springer, 2011.
Taur, Yuan. Fundamentals of modern VLSI devices. 2nd ed. Cambridge: Cambridge University Press, 2009.
Taur, Yuan. Fundamentals of modern VLSI devices. Cambrige, UK: Cambridge University Press, 1998.
Incorporated, Advanced Micro Devices. PAL device data book: Bipolar and CMOS. [Sunnyvale, CA]: Advanced Micro Devices Inc., 1990.
Simon, Deleonibus, ed. Electronic device architectures for the nano-CMOS era: From ultimate CMOS scaling to beyond CMOS devices. Singapore: Pan Stanford, 2009.
Simon, Deleonibus, ed. Electronic device architectures for the nano-CMOS era: From ultimate CMOS scaling to beyond CMOS devices. Singapore: Pan Stanford, 2009.
V, Heinbuch Dennis, ed. CMOS 3 cell library. Reading, Mass: Addison-Wesley Pub. Co., 1988.
Ytterdal, Trond, Yuhua Cheng, and Tor A. Fjeldly. Device Modeling for Analog and RF CMOS Circuit Design. Chichester, UK: John Wiley & Sons, Ltd, 2003. http://dx.doi.org/10.1002/0470863803.
Частини книг з теми "CMOS Device and Integration":
Mahadevaiah, Mamathamba Kalishettyhalli, Marco Lisker, Mirko Fraschke, Steffen Marschmeyer, Eduardo Perez, Emilio Perez-Bosch Quesada, Christian Wenger, and Andreas Mai. "Integration of Memristive Devices into a 130 nm CMOS Baseline Technology." In Springer Series on Bio- and Neurosystems, 177–90. Cham: Springer International Publishing, 2023. http://dx.doi.org/10.1007/978-3-031-36705-2_7.
Dubois, E., G. Larrieu, R. Valentin, N. Breil, and F. Danneville. "Introduction to Schottky-Barrier MOS Architectures: Concept, Challenges, Material Engineering and Device Integration." In Nanoscale CMOS, 157–204. Hoboken, NJ, USA: John Wiley & Sons, Inc., 2013. http://dx.doi.org/10.1002/9781118621523.ch5.
Xia, Qiangfei. "Memristor Device Engineering and CMOS Integration for Reconfigurable Logic Applications." In Memristors and Memristive Systems, 327–51. New York, NY: Springer New York, 2013. http://dx.doi.org/10.1007/978-1-4614-9068-5_11.
Wang, Guilei. "SiGe S/D Integration and Device Verification." In Investigation on SiGe Selective Epitaxy for Source and Drain Engineering in 22 nm CMOS Technology Node and Beyond, 49–92. Singapore: Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-15-0046-6_4.
Götzlich, J., R. Kircher, K. Giesen, and G. Pöschl. "Characterization and Simulation of SOI-CMOS Devices for 3D-integration." In ESSDERC ’89, 873–76. Berlin, Heidelberg: Springer Berlin Heidelberg, 1989. http://dx.doi.org/10.1007/978-3-642-52314-4_180.
Nourbakhsh, Amirhasan, Lili Yu, Yuxuan Lin, Marek Hempel, Ren-Jye Shiue, Dirk Englund, and Tomás Palacios. "Heterogeneous Integration of 2D Materials and Devices on a Si Platform." In Beyond-CMOS Technologies for Next Generation Computer Design, 43–84. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-90385-9_3.
Liu, Ming, Hua Yu, and Wei Wang. "FPAA Based on Integration of CMOS and Nanojunction Devices for Neuromorphic Applications." In Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering, 44–48. Berlin, Heidelberg: Springer Berlin Heidelberg, 2009. http://dx.doi.org/10.1007/978-3-642-02427-6_9.
Xie, Huikai, and Ying Zhou. "CMOS-CNT Integration." In Encyclopedia of Nanotechnology, 549–57. Dordrecht: Springer Netherlands, 2016. http://dx.doi.org/10.1007/978-94-017-9780-1_196.
Peroulis, Dimitrios, Prashant R. Waghmare, Sushanta K. Mitra, Supone Manakasettharn, J. Ashley Taylor, Tom N. Krupenkin, Wenguang Zhu, et al. "CMOS-CNT Integration." In Encyclopedia of Nanotechnology, 449–56. Dordrecht: Springer Netherlands, 2012. http://dx.doi.org/10.1007/978-90-481-9751-4_196.
Thejas and Navakanta Bhat. "CMOS MEMS Integration." In Materials and Failures in MEMS and NEMS, 361–80. Hoboken, NJ, USA: John Wiley & Sons, Inc., 2015. http://dx.doi.org/10.1002/9781119083887.ch12.
Тези доповідей конференцій з теми "CMOS Device and Integration":
Xu, Kaikai, Beiju Huang, Kingsley A. Ogudo, Lukas W. Snyman, Hongda Chen, and G. P. Li. "Silicon Light-emitting Device in Standard CMOS technology." In Optoelectronic Devices and Integration. Washington, D.C.: OSA, 2015. http://dx.doi.org/10.1364/oedi.2015.ot1c.3.
Hussain, Muhammad M., Sohail F. Shaikh, Galo A. Torres Sevilla, Joanna M. Nassar, Aftab M. Hussain, Rabab R. Bahabry, Sherjeel M. Khan, et al. "Manufacturable Heterogeneous Integration for Flexible CMOS Electronics." In 2018 76th Device Research Conference (DRC). IEEE, 2018. http://dx.doi.org/10.1109/drc.2018.8442163.
Ohno, Hideo. "Three-terminal spintronics devices for CMOS integration." In 2017 75th Device Research Conference (DRC). IEEE, 2017. http://dx.doi.org/10.1109/drc.2017.7999490.
Salimy, S., S. Toutain, D. Averty, F. Challali, A. Goullet, M.-P. Besland, A. Rhallabi, J.-P. Landesman, J.-C. Saubat, and A. Charpentier. "Passive components integration in CMOS technology." In ESSDERC 2010 - 40th European Solid State Device Research Conference. IEEE, 2010. http://dx.doi.org/10.1109/essderc.2010.5618467.
Fulbert, Laurent, and Jean-Marc Fedeli. "Photonics — Electronics integration on CMOS." In ESSDERC 2011 - 41st European Solid State Device Research Conference. IEEE, 2011. http://dx.doi.org/10.1109/essderc.2011.6044241.
Pi, Shuang, Peng Lin, Hao Jiang, Can Li, and Qiangfei Xia. "Device engineering and CMOS integration of nanoscale memristors." In 2014 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2014. http://dx.doi.org/10.1109/iscas.2014.6865156.
Holz, J., I. Koren, and U. Ramacher. "Technology and System Integration of CMOS Image Sensors." In 30th European Solid-State Device Research Conference. IEEE, 2000. http://dx.doi.org/10.1109/essderc.2000.194724.
Waldo, Whitson G., Ibrahim Turkman, and Rickey Brownson. "Device and process integration for a 0.55-um channel length CMOS device." In Microelectronic Manufacturing 1996, edited by Ih-Chin Chen, Nobuo Sasaki, Divyesh N. Patel, and Girish A. Dixit. SPIE, 1996. http://dx.doi.org/10.1117/12.250858.
Beals, Mark, J. Michel, J. F. Liu, D. H. Ahn, D. Sparacin, R. Sun, C. Y. Hong, et al. "Process flow innovations for photonic device integration in CMOS." In Integrated Optoelectronic Devices 2008, edited by Joel A. Kubby and Graham T. Reed. SPIE, 2008. http://dx.doi.org/10.1117/12.774576.
Matsushita, K., N. Takayama, Ning Li, S. Ito, K. Okada, and A. Matsuzawa. "CMOS device modeling for millimeter-wave power amplifiers." In 2009 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT 2009). IEEE, 2009. http://dx.doi.org/10.1109/rfit.2009.5383690.
Звіти організацій з теми "CMOS Device and Integration":
Smith, J. H., S. Montague, J. J. Sniegowski, and J. R. Murray. Characterization of the embedded micromechanical device approach to the monolithic integration of MEMS with CMOS. Office of Scientific and Technical Information (OSTI), October 1996. http://dx.doi.org/10.2172/380312.
Smith, J. H., S. Montague, J. J. Sniegowski, and P. J. McWhorter. Embedded micromechanical devices for the monolithic integration of MEMS and CMOS. Office of Scientific and Technical Information (OSTI), July 1995. http://dx.doi.org/10.2172/114489.
Fonstad, Clifton G. Monolithic Integration of Optoelectronic Devices and Si-CMOS on Gallium Arsenide. Fort Belvoir, VA: Defense Technical Information Center, November 2000. http://dx.doi.org/10.21236/ada391141.
MYERS, DAVID R., JEFFREY R. JESSING, OLGA B. SPAHN, and MARTY R. SHANEYFELT. LDRD Final Report - Investigations of the impact of the process integration of deposited magnetic films for magnetic memory technologies on radiation-hardened CMOS devices and circuits - LDRD Project (FY99). Office of Scientific and Technical Information (OSTI), January 2000. http://dx.doi.org/10.2172/750886.
James F. Christian, PhD, and PhD Christopher Stapels. Next-Generation Active Pixel Sensor Device With CMOS APDs. Office of Scientific and Technical Information (OSTI), March 2007. http://dx.doi.org/10.2172/900308.
Xie, Y. H. A Quantum Dot Optical Modulator for Integration With Si CMOS. Fort Belvoir, VA: Defense Technical Information Center, August 2005. http://dx.doi.org/10.21236/ada459498.
Xu, Xiaodong, Mark Mirotznik, Michael Hochberg, and David Castner. Optoelectronic Device Integration in Silicon (OpSIS). Fort Belvoir, VA: Defense Technical Information Center, October 2015. http://dx.doi.org/10.21236/ad1003428.
Cerjan, C. J., and T. W. Sigmon. Integration of Radiation-Hard Magnetic Random Access Memory with CMOS ICs. Office of Scientific and Technical Information (OSTI), February 2000. http://dx.doi.org/10.2172/792430.
Brotman, Susan. The Evaluation of Device Model Dependence in the Design of a High-Frequency, Analog, CMOS Transconductance-C Filter. Portland State University Library, January 2000. http://dx.doi.org/10.15760/etd.6585.
Martinez, Carlos J., Amit Goyal, Alberto Saiani, David Gracias, and Rajesh R. Naik. Integrated Miniaturized Materials - From Self-Assembly to Device Integration. Volume 1272. Fort Belvoir, VA: Defense Technical Information Center, January 2011. http://dx.doi.org/10.21236/ada537907.