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Статті в журналах з теми "CMOS device"
Yedukondalu, Udara, Vinod Arunachalam, Vasudha Vijayasri Bolisetty, and Ravikumar Guru Samy. "Fully synthesizable multi-gate dynamic voltage comparator for leakage reduction and low power application." Indonesian Journal of Electrical Engineering and Computer Science 28, no. 2 (November 1, 2022): 716. http://dx.doi.org/10.11591/ijeecs.v28.i2.pp716-723.
Повний текст джерелаXiong, Qi, Shao Hua Zhou, and Jiang Ping Zeng. "The Analysis of Device Model in CMOS Integrated Temperature Sensor." Advanced Materials Research 986-987 (July 2014): 1600–1605. http://dx.doi.org/10.4028/www.scientific.net/amr.986-987.1600.
Повний текст джерелаChiovetti, Bob. ""Chip Wars" Heat Up On The Digital Imaging Front." Microscopy Today 7, no. 2 (March 1999): 3–4. http://dx.doi.org/10.1017/s1551929500063847.
Повний текст джерелаShawkat, Mst Shamim Ara, Mohammad Habib Ullah Habib, Md Sakib Hasan, Mohammad Aminul Haque, and Nicole McFarlane. "Perimeter Gated Single Photon Avalanche Diodes in Sub-Micron and Deep-Submicron CMOS Processes." International Journal of High Speed Electronics and Systems 27, no. 03n04 (September 2018): 1840018. http://dx.doi.org/10.1142/s0129156418400189.
Повний текст джерелаWong, Hei. "Abridging CMOS Technology." Nanomaterials 12, no. 23 (November 29, 2022): 4245. http://dx.doi.org/10.3390/nano12234245.
Повний текст джерелаFOSSUM, JERRY G. "A SIMULATION-BASED PREVIEW OF EXTREMELY SCALED DOUBLE-GATE CMOS DEVICES AND CIRCUITS." International Journal of High Speed Electronics and Systems 12, no. 02 (June 2002): 563–72. http://dx.doi.org/10.1142/s0129156402001460.
Повний текст джерелаMOONEY, P. M. "MATERIALS FOR STRAINED SILICON DEVICES." International Journal of High Speed Electronics and Systems 12, no. 02 (June 2002): 305–14. http://dx.doi.org/10.1142/s0129156402001265.
Повний текст джерелаBirla, Shilpi, Sudip Mahanti, and Neha Singh. "Leakage reduction technique for nano-scaled devices." Circuit World 47, no. 1 (May 29, 2020): 97–104. http://dx.doi.org/10.1108/cw-12-2019-0195.
Повний текст джерелаWon, Jongun, Youngchae Roh, Minseung Kang, Yeaji Park, Jaehyeon Kang, Hyeongjun Seo, Changhoon Joe, and SangBum Kim. "A Capacitor-Based Synaptic Device with IGZO Access Transistors for Neuromorphic Computing." ECS Transactions 111, no. 2 (May 19, 2023): 133–36. http://dx.doi.org/10.1149/11102.0133ecst.
Повний текст джерелаTang, L., S. Latif, and D. A. B. Miller. "Plasmonic device in silicon CMOS." Electronics Letters 45, no. 13 (2009): 706. http://dx.doi.org/10.1049/el.2009.0839.
Повний текст джерелаДисертації з теми "CMOS device"
Rakheja, Shaloo. "Interconnects for post-CMOS devices: physical limits and device and circuit implications." Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/45866.
Повний текст джерелаYu, Chuanzhao. "STUDY OF NANOSCALE CMOS DEVICE AND CIRCUIT RELIABILITY." Doctoral diss., University of Central Florida, 2006. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/3551.
Повний текст джерелаPh.D.
Department of Electrical and Computer Engineering
Engineering and Computer Science
Electrical Engineering
Jain, Ishita. "Modeling and simulation of self-heating effects in sub-14NM CMOS devices." Thesis, IIT Delhi, 2019. http://eprint.iitd.ac.in:80//handle/2074/8137.
Повний текст джерелаWu, Dongping. "Novel concepts for advanced CMOS : Materials, process and device architecture." Doctoral thesis, KTH, Microelectronics and Information Technology, IMIT, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-3805.
Повний текст джерелаThe continuous and aggressive dimensional miniaturization ofthe conventional complementary-metal-oxide semiconductor (CMOS)architecture has been the main impetus for the vast growth ofIC industry over the past decades. As the CMOS downscalingapproaches the fundamental limits, unconventional materials andnovel device architectures are required in order to guaranteethe ultimate scaling in device dimensions and maintain theperformance gain expected from the scaling. This thesisinvestigates both unconventional materials for the gate stackand the channel and a novel notched-gate device architecture,with the emphasis on the challenging issues in processintegration.
High-κ gate dielectrics will become indispensable forCMOS technology beyond the 65-nm technology node in order toachieve a small equivalent oxide thickness (EOT) whilemaintaining a low gate leakage current. HfO2and Al2O3as well as their mixtures are investigated assubstitutes for the traditionally used SiO2in our MOS transistors. These high-κ filmsare deposited by means of atomic layer deposition (ALD) for anexcellent control of film composition, thickness, uniformityand conformality. Surface treatments prior to ALD are found tohave a crucial influence on the growth of the high-κdielectrics and the performance of the resultant transistors.Alternative gate materials such as TiN and poly-SiGe are alsostudied. The challenging issues encountered in processintegration of the TiN or poly-SiGe with the high-k are furtherelaborated. Transistors with TiN or poly-SiGe/high-k gate stackare successfully fabricated and characterized. Furthermore,proof-of-concept strained-SiGe surface-channel pMOSFETs withALD high-κ dielectrics are demonstrated. The pMOSFETs witha strained SiGe channel exhibit a higher hole mobility than theuniversal hole mobility in Si. A new procedure for extractionof carrier mobility in the presence of a high density ofinterface states found in MOSFETs with high-κ dielectricsis developed.
A notched-gate architecture aiming at reducing the parasiticcapacitance of a MOSFET is studied. The notched gate is usuallyreferred to as a local thickness increase of the gatedielectric at the feet of the gate above the source/drainextensions. Two-dimensional simulations are carried out toinvestigate the influence of the notched gate on the static anddynamic characteristics of MOSFETs. MOSFETs with optimizednotch profile exhibit a substantial enhancement in the dynamiccharacteristics with a negligible effect on the staticcharacteristics. Notched-gate MOSFETs are also experimentallyimplemented with the integration of a high-κ gatedielectric and a poly-SiGe/TiN bi-layer gate electrode.
Key words:CMOS technology, MOSFET, high-κ, gatedielectric, ALD, surface pre-treatment, metal gate, poly-SiGe,strained SiGe, surface-channel, buried-channel, notchedgate.
Xu, Chen. "Low voltage CMOS digital imaging architecture with device scaling considerations /." View abstract or full-text, 2004. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202004%20XU.
Повний текст джерелаIncludes bibliographical references (leaves 131-136). Also available in electronic version. Access restricted to campus users.
Kopalle, Deepika Niu Guofu. "RF linearity analysis in nano scale CMOS using harmonic balance device simulations." Auburn, Ala., 2005. http://repo.lib.auburn.edu/2005%20Fall/Thesis/KOPALLE_DEEPIKA_43.pdf.
Повний текст джерелаOdanaka, Shinji. "A STUDY OF NUMERICAL PROCESS AND DEVICE MODELING CAD FOR SUBMICROMETER CMOS." Kyoto University, 1990. http://hdl.handle.net/2433/86214.
Повний текст джерелаWang, Haihong. "Advanced transport models development for deep submicron low power CMOS device design /." Digital version accessible at:, 1999. http://wwwlib.umi.com/cr/utexas/main.
Повний текст джерелаHUSSAIN, IZHAR. "TAMTAMS: A web based performance estimation tool from Device to System level for advanced CMOS processes to beyond CMOS technologies." Doctoral thesis, Politecnico di Torino, 2018. http://hdl.handle.net/11583/2710840.
Повний текст джерелаAbel, Christopher J. "An investigation of nonideal process and device effects in fundamental CMOS analog subcircuits /." The Ohio State University, 1995. http://rave.ohiolink.edu/etdc/view?acc_num=osu1487865929454587.
Повний текст джерелаКниги з теми "CMOS device"
Simon, Deleonibus, ed. Electronic device architectures for the nano-CMOS era: From ultimate CMOS scaling to beyond CMOS devices. Singapore: Pan Stanford, 2009.
Знайти повний текст джерелаSimon, Deleonibus, ed. Electronic device architectures for the nano-CMOS era: From ultimate CMOS scaling to beyond CMOS devices. Singapore: Pan Stanford, 2009.
Знайти повний текст джерелаIncorporated, Advanced Micro Devices. PAL device data book: Bipolar and CMOS. [Sunnyvale, CA]: Advanced Micro Devices Inc., 1990.
Знайти повний текст джерелаYtterdal, Trond, Yuhua Cheng, and Tor A. Fjeldly. Device Modeling for Analog and RF CMOS Circuit Design. Chichester, UK: John Wiley & Sons, Ltd, 2003. http://dx.doi.org/10.1002/0470863803.
Повний текст джерелаDevice modeling for analog and RF CMOS circuit design. Chichester: John Wiley & Sons, 2004.
Знайти повний текст джерелаSemenov, Oleg, Hossein Sarbishaei, and Manoj Sachdev. ESD Protection Device and Circuit Design for Advanced CMOS Technologies. Dordrecht: Springer Netherlands, 2008. http://dx.doi.org/10.1007/978-1-4020-8301-3.
Повний текст джерелаHossein, Sarbishaei, and Sachdev Manoj, eds. ESD protection device and circuit design for advanced CMOS technologies. [Dordrecht]: Springer, 2008.
Знайти повний текст джерелаMadrid, Philip E. Device design and process window analysis of a deep submicron CMOS VLSI technology. Reading, Mass: Addison-Wesley, 1992.
Знайти повний текст джерелаUnited States. National Aeronautics and Space Administration., ed. Application of linear response theory to experimental data of simultasneous radiation and annealing response of a CMOS device. [Washington, DC: National Aeronautics and Space Administration, 1989.
Знайти повний текст джерелаL, Helms Harry, ed. CMOS devices: 1987 source book. Englewood Cliffs, N.J: Technipubs, 1987.
Знайти повний текст джерелаЧастини книг з теми "CMOS device"
Martinez, A., A. Asenov, and M. Pala. "NEGF for 3D Device Simulation of Nanometric Inhomogenities." In Nanoscale CMOS, 335–80. Hoboken, NJ, USA: John Wiley & Sons, Inc., 2013. http://dx.doi.org/10.1002/9781118621523.ch10.
Повний текст джерелаGrasser, T., R. Strasser, M. Knaipp, K. Tsuneno, H. Masuda, and S. Selberherr. "Device Simulator Calibration for Quartermicron CMOS Devices." In Simulation of Semiconductor Processes and Devices 1998, 93–96. Vienna: Springer Vienna, 1998. http://dx.doi.org/10.1007/978-3-7091-6827-1_26.
Повний текст джерелаDavies, M. S., and P. D. T. O’Connor. "Reliability Assessment of Cmos Asic Designs." In Semiconductor Device Reliability, 137–46. Dordrecht: Springer Netherlands, 1990. http://dx.doi.org/10.1007/978-94-009-2482-6_8.
Повний текст джерелаSolomon, P. M. "Device Proposals Beyond Silicon CMOS." In Future Trends in Microelectronics, 127–40. Hoboken, NJ, USA: John Wiley & Sons, Inc., 2010. http://dx.doi.org/10.1002/9780470649343.ch10.
Повний текст джерелаGharavi, Sam, and Babak Heydari. "mm-Wave Device Modeling." In Ultra High-Speed CMOS Circuits, 5–21. New York, NY: Springer New York, 2011. http://dx.doi.org/10.1007/978-1-4614-0305-0_2.
Повний текст джерелаGharavi, Sam, and Babak Heydari. "mm-Wave Device Optimization." In Ultra High-Speed CMOS Circuits, 23–34. New York, NY: Springer New York, 2011. http://dx.doi.org/10.1007/978-1-4614-0305-0_3.
Повний текст джерелаDubois, E., G. Larrieu, R. Valentin, N. Breil, and F. Danneville. "Introduction to Schottky-Barrier MOS Architectures: Concept, Challenges, Material Engineering and Device Integration." In Nanoscale CMOS, 157–204. Hoboken, NJ, USA: John Wiley & Sons, Inc., 2013. http://dx.doi.org/10.1002/9781118621523.ch5.
Повний текст джерелаLabiod, Samir, Abdelmalek Mouatsi, Zakaria Hadef, and Billel Smaani. "Conventional CMOS circuit design." In Device Circuit Co-Design Issues in FETs, 21–56. Boca Raton: CRC Press, 2023. http://dx.doi.org/10.1201/9781003359234-2.
Повний текст джерелаSalama, Husien, Alain Tshipamba, and Khalifa Ahmed. "Modeling for CMOS circuit design." In Device Circuit Co-Design Issues in FETs, 1–20. Boca Raton: CRC Press, 2023. http://dx.doi.org/10.1201/9781003359234-1.
Повний текст джерелаCham, Kit Man, Soo-Young Oh, Daeje Chin, and John L. Moll. "Transistor Design for Submicron CMOS Technology." In Computer-Aided Design and VLSI Device Development, 171–97. Boston, MA: Springer US, 1986. http://dx.doi.org/10.1007/978-1-4613-2553-6_9.
Повний текст джерелаТези доповідей конференцій з теми "CMOS device"
Horstmann, Manfred, and Reinhard Mahnkopf. "CMOS Devices - Device/Design Interaction." In 2007 IEEE International Electron Devices Meeting. IEEE, 2007. http://dx.doi.org/10.1109/iedm.2007.4418974.
Повний текст джерелаChang, Chih-Sheng, and Akira Hokazono. "CMOS Devices - Advanced Device Structures." In 2007 IEEE International Electron Devices Meeting. IEEE, 2007. http://dx.doi.org/10.1109/iedm.2007.4419091.
Повний текст джерелаXiao, Yang, Martin A. Trefzer, Scott Roy, James Alfred Walker, Simon J. Bale, and Andy M. Tyrrell. "Circuit optimization using device layout motifs." In 2014 5th European Workshop on CMOS Variability (VARI). IEEE, 2014. http://dx.doi.org/10.1109/vari.2014.6957081.
Повний текст джерелаHatakeyama, T., K. Fushinobu, and K. Okazaki. "Investigation of Device Interactions Between Two MOSFETs in Si CMOS." In ASME 2008 International Mechanical Engineering Congress and Exposition. ASMEDC, 2008. http://dx.doi.org/10.1115/imece2008-67204.
Повний текст джерела"Silicon CMOS." In 2007 65th Annual Device Research Conference. IEEE, 2007. http://dx.doi.org/10.1109/drc.2007.4373644.
Повний текст джерелаTang, Liang, Salman Latif, and David A. B. Miller. "Plasmonic device in Si CMOS." In LEOS 2008 - 21st Annual Meeting of the IEEE Lasers and Electro-Optics Society (LEOS 2008). IEEE, 2008. http://dx.doi.org/10.1109/leos.2008.4688527.
Повний текст джерелаTrivedi, Fossum, and Vandooren. "Non-classical CMOS device design." In 2003 IEEE International Conference on Robotics and Automation (Cat No 03CH37422) SOI-03). IEEE, 2003. http://dx.doi.org/10.1109/soi.2003.1242935.
Повний текст джерелаSasagawa, Kiyotaka, Makito Haruta, Yasumi Ohta, Hironari Takehara, and Jun Ohta. "Implantable Fluorescent CMOS Imaging Device." In 2020 4th IEEE Electron Devices Technology & Manufacturing Conference (EDTM). IEEE, 2020. http://dx.doi.org/10.1109/edtm47692.2020.9117820.
Повний текст джерелаReddy, Anyam Apuroop Kumar, Syed Azeemuddin, and M. R. Sayeh. "A CMOS proteretic bistable device." In 2016 IEEE Annual India Conference (INDICON). IEEE, 2016. http://dx.doi.org/10.1109/indicon.2016.7839016.
Повний текст джерела"Emerging CMOS devices." In 2016 74th Annual Device Research Conference (DRC). IEEE, 2016. http://dx.doi.org/10.1109/drc.2016.7548398.
Повний текст джерелаЗвіти організацій з теми "CMOS device"
James F. Christian, PhD, and PhD Christopher Stapels. Next-Generation Active Pixel Sensor Device With CMOS APDs. Office of Scientific and Technical Information (OSTI), March 2007. http://dx.doi.org/10.2172/900308.
Повний текст джерелаSmith, J. H., S. Montague, J. J. Sniegowski, and J. R. Murray. Characterization of the embedded micromechanical device approach to the monolithic integration of MEMS with CMOS. Office of Scientific and Technical Information (OSTI), October 1996. http://dx.doi.org/10.2172/380312.
Повний текст джерелаBrotman, Susan. The Evaluation of Device Model Dependence in the Design of a High-Frequency, Analog, CMOS Transconductance-C Filter. Portland State University Library, January 2000. http://dx.doi.org/10.15760/etd.6585.
Повний текст джерелаKoga, Rokutaro, and Wojciech A. Kolasinski. Heavy-Ion-Induced Snapback in CMOS Devices. Fort Belvoir, VA: Defense Technical Information Center, August 1990. http://dx.doi.org/10.21236/ada226765.
Повний текст джерелаPlewa, Matthew I., and Justin Vandenbroucke. Detecting cosmic rays using CMOS sensors in consumer devices. Ames (Iowa): Iowa State University. Library. Digital Press, January 2015. http://dx.doi.org/10.31274/ahac.9757.
Повний текст джерелаKoh, Seong J., and Choong-Un Kim. Fabrication of Single Electron Devices within the Framework of CMOS Technology. Fort Belvoir, VA: Defense Technical Information Center, December 2008. http://dx.doi.org/10.21236/ada491301.
Повний текст джерелаSmith, J. H., S. Montague, J. J. Sniegowski, and P. J. McWhorter. Embedded micromechanical devices for the monolithic integration of MEMS and CMOS. Office of Scientific and Technical Information (OSTI), July 1995. http://dx.doi.org/10.2172/114489.
Повний текст джерелаFonstad, Clifton G. Monolithic Integration of Optoelectronic Devices and Si-CMOS on Gallium Arsenide. Fort Belvoir, VA: Defense Technical Information Center, November 2000. http://dx.doi.org/10.21236/ada391141.
Повний текст джерелаStaple, B. D., H. A. Watts, C. Dyck, A. P. Griego, F. W. Hewlett, and J. H. Smith. SPICE Level 3 and BSIM3v3.1 characterization of monolithic integrated CMOS-MEMS devices. Office of Scientific and Technical Information (OSTI), August 1998. http://dx.doi.org/10.2172/663240.
Повний текст джерелаKoga, R., S. J. Hansel, W. R. Crain, K. B. Crawford, S. D. Pinkerton, J. Quan, and M. Maher. Single Event Upset and Latchup Considerations for CMOS Devices Operated at 3.3 Volts. Fort Belvoir, VA: Defense Technical Information Center, January 1998. http://dx.doi.org/10.21236/ada349539.
Повний текст джерела