Дисертації з теми "Wireline communication"
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Nilsson, Rickard. "Digital communication in wireline and wireless environments." Licentiate thesis, Luleå tekniska universitet, Signaler och system, 1999. http://urn.kb.se/resolve?urn=urn:nbn:se:ltu:diva-17330.
Повний текст джерелаGodkänd; 1999; 20070404 (ysko)
Huang, Deping. "Design Techniques for Timing Circuits in Wireline and Wireless Communication Systems." Diss., The University of Arizona, 2014. http://hdl.handle.net/10150/344107.
Повний текст джерелаLee, Sanghoon. "Foveated video compression and visual communications over wireless and wireline networks /." Digital version accessible at:, 2000. http://wwwlib.umi.com/cr/utexas/main.
Повний текст джерелаKhodayari, Moez Kambiz. "Design of CMOS Distributed Amplifiers for Broadband Wireline and Wireless Communication Applications." Thesis, University of Waterloo, 2006. http://hdl.handle.net/10012/2857.
Повний текст джерелаIn this work, we focus on the design of broadband low-noise amplifiers: the fundamental building blocks of high data rate wireline and wireless telecommunication systems. A well established microwave engineering technique -distributed amplification- with a potential bandwidth up to the cut-off frequency of transistors is employed. However, the implementation of distributed amplifiers in CMOS imposes new challenges, such as gain attenuation because of substrate loss of on-chip inductors, a typical large die area, and a large noise-figure. These problems have been addressed in this dissertation as described below.
On-chip inductors, the essential components of the distributed amplifiers' gate and drain transmission lines, dissipate more and more power in silicon substrates as well as in metal lines as frequency increases, which in turn reduces the gain and deteriorates the input/output matching. Using active negative resistors implemented by a capacitively source degenerated configuration, we have fully compensated the loss of the transmission lines in order to achieve a flat gain of 10 dB over the entire DC-to-44 GHz bandwidth.
We have addressed another drawback of distributed amplifiers, large die area, by utilizing closely-placed RF transmission lines instead of spiral inductors. Because of a more compact implementation of transmission lines, the area of the distributed amplifiers is considerably reduced at the expense of extra design steps required for the modeling of the closely-placed RF transmission lines. A post-layout simulation method is developed to take into account the effect of inductive and capacitive coupling by incorporating a 3D EM simulator into the design process. A 9-dB 27-GHz distributed amplifier has been fabricated in an area as small as 0. 17 mm2 using 180nm TSMC's CMOS process.
For wireless applications (UWB), a very low-noise figure is required for the broadband preamplifier. Conventional distributed amplifiers fail to provide a low noise figure mainly because of the noise injected by the terminating resistor of the gate transmission lines. We have replaced the terminating resistor with a frequency-dependent resistor which trades off the low frequency input matching of the distributed amplifier (not required for UWB) with a better noise performance. Our proposed design provides a gain of 12 dB with an average noise figure of 3. 4 dB over the entire 3-10 GHz band, advancing the state-of-the-art implementation of broadband LNAs.
Stevens, Irena. "Policy implications of municipal investment in Georgia's wireline broadband networks." Thesis, Georgia Institute of Technology, 2013. http://hdl.handle.net/1853/49081.
Повний текст джерелаShankar, Subramaniam. "High-speed, high-performance wireless and wireline applications using silicon-germanium BiCMOS technologies." Diss., Georgia Institute of Technology, 2013. http://hdl.handle.net/1853/48958.
Повний текст джерелаOliveira, Thiago Rodrigues. "The characterization of hybrid PLC-wireless and PLC channels in the frequency band between 1.7 and 100 MHz for data communication." Universidade Federal de Juiz de Fora, 2015. https://repositorio.ufjf.br/jspui/handle/ufjf/940.
Повний текст джерелаRejected by Adriana Oliveira (adriana.oliveira@ufjf.edu.br), reason: Consertar sobrenome orientador on 2016-03-03T14:07:28Z (GMT)
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Essa tese de doutorado apresenta, inicialmente, uma metodologia a ser empregada para a caracterização de redes de energia elétrica para fins de comunicação de dados. Esta metodologia engloba todos os procedimentos e ferramentas de processamento de sinais necessárias para a estimação de características importantes para a avaliação de canais de comunicação de dados. Em seguida, são apresentados resultados da aplicação de tal metodologia em dados provenientes de uma campanha de medição realizada em ambientes internos em residências brasileiras. Algumas características importantes desses canais, tais como ganho médio, banda de coerência, tempo de coerência, o valor quadrático médio do espalhamento de atraso, capacidade do canal e densidade espectral de potência do ruído, são analizadas considerando três bandas de frequência: de 1,7 até 30 MHz, de 1,7 até 50 MHz e de 1,7 até 100 MHz. Comparando os resultados de canais power line communication (PLC) em ambientes residenciais brasileiros com aqueles medidos em outros países, tais como Espanha, Estados Unidos, França e Itália, podemos notar que canais PLC brasileiros apresentam, em geral, menores atenuações, são menos seletivos em frequência e possuem menores espalhamentos de atraso. Por fim, um novo meio de comunicação baseada nas tecnologias PLC e sem fio é apresentada e definida como híbrido PLC-sem fio o qual permite a comunicação física e à distância com a rede de energia elétrica para fins de comunicação de dados. Tal canal de comunicação é avaliado em residências brasileiras e importantes características são extraídas e discutidas. Embora o canal híbrido PLC-sem fio tenha se mostrado mais adverso que o canal PLC para a comunicação de dados, a introdução da mobilidade, de uma forma que é impossível de se obter em sistemas puramente PLC, constitui sua principal vantagem. Essa mobilidade é um importante atrativo que coloca sistemas híbridos em uma posição privilegiada dentre os candidatos para compor a infraestrutura de telecomunicações em redes inteligentes (smart grids), ou para ser usada como uma ferramenta para promover a inclusão digital da população carente de países pobres ou em desenvolvimento.
This work outlines initially a methodology to be applied to the characterization of electric power grids for data communication purposes. This methodology englobes all the procedures and required signal processing tools for a reliable estimation of features that allow the suitability of a media for data communication. Next, PLC (power line communication) channel results provided by the use of such methodology in a data set obtained from a measurement campaing in in-home Brazilian places are presented. The analyzed channel features are the average channel gain, the coherence bandwidth, the coherence time, the root mean squared delay spread, the channel capacity and the noise power spectral density by considering the following frequency bands: from 1.7 up to 30 MHz, from 1.7 up to 50 MHz and from 1.7 up to 100 MHz. Comparisons among the results for in-home Brazilian PLC channels with other provided for other countries such as Spain, United States, France and Italy showed that, in general, in-home Brazilian PLC channels present smaller attenuation, are less frequency selective and showed smaller delay spread than these countries. Finally, a new medium to provide data communication is presented and defined as hybrid PLC-wireless, in which PLC and wireless technologies are combined. Such novel communication channel is characterized in in-home Brazilian places and important channel features are estimated and discussed. Though the hybrid PLC-wireless channel has been shown more adverse than the PLC channel, the introduction of mobility is its main advantage, something that is impossible in traditional PLC technologies. Thus, this mobility is an important issue that puts hybrid PLC-wireless technologies in a privileged position among the candidates to form the communication infrastructure for smart grids, or to be used as a too to solve the digital divide problem that is more accentuated in poor and in developing countries.
Lauder, David Maxwell. "Electromagnetic compatibility in wireline communications." Thesis, University of Hertfordshire, 2007. http://hdl.handle.net/2299/16518.
Повний текст джерелаHossain, Masum. "Low-power Multi-Gb/s Wireline Communication." Thesis, 2011. http://hdl.handle.net/1807/29925.
Повний текст джерелаDou, Qingqi. "I/O test methods in high-speed wireline communication systems." 2008. http://hdl.handle.net/2152/18345.
Повний текст джерелаtext
Su, Chun-Chia, and 蘇俊嘉. "Hybrid Wireline and Wireless Communication System Based on Phase Modulator." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/65e2xn.
Повний текст джерела國立臺北科技大學
光電工程系研究所
102
In the future, access networks are driving the convergence of wireline and wireless networks to offer end users greater choice, convenience and variety in an efficient way. This study proposed a radio-over-fiber (RoF) system based on phase modulation technique, integrating fiber-to-the-home (FTTH) and RoF systems, are promising for multi-service access networks. This scheme can transmit both wireline and wireless signals on a single wavelength over a single fiber, which serves these two applications simultaneously. Experimental results show that the quality of wireline and wireless signals can be achieved user’s requirements. The system is sufficient to meet the standard of future communication network.
Sharma, Deepak. "Linear Network Coding For Wireline And Wireless Networks." Thesis, 2007. http://hdl.handle.net/2005/638.
Повний текст джерелаHung, Szu-Yao, and 洪偲僥. "Design of Fast-Settling, High-Linearity Automatic Gain Control for Broadband Wireline Communication." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/71542441878861562201.
Повний текст джерела國立臺灣大學
電子工程學研究所
101
The wireline communication has spawned a revival of interest in multimedia content distribution due to its high data bandwidth and reliability. Powerline communication (PLC) in digital home employs orthogonal frequency-division multiplexing (OFDM) modulation for high data rates in multi-path signal channels. The receiver estimates the channel’s characteristics during the reception of the preamble by the process of automatic gain control (AGC), which is an essential function in wireline receivers to adjust sensitivity to incoming signal strength. This work focuses on the analysis and design of high-linearity, fast-settling AGC in receiver front-end. Two key AGC building block applications, a high-linearity reconfiguration-based programmable gain amplifier (PGA) and a fast-settling feedforward AGC, are presented. In the PGA, linearity of amplifier is improved by adopting adaptive biasing circuit in a push-pull amplifier. Binary-weighted switching pseudo-exponential approximation technique is utilized for decibel-linear gain tuning. Reconfigurable PGA architecture is also employed to reduce parasitic effect and circuit complexity. In the AGC, a novel feedforward control scheme is proposed to achieve fast loop response requirement of OFDM-based receivers. The analysis and implementation consideration of key building blocks are provided in this work. Fabricated in 90-nm CMOS technology, the experimental results show that the linear characteristic of PGA is suitable for 1024 QAM in OFDM demodulation and 0.1 μs is used for the AGC system convergence while consuming 3.7 mW through 1.2-V supply.
Shen, Kun-Jui, and 沈坤叡. "A 20-32Gb/s Transmitter System for Wireline Communication Testing in CMOS Technology." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/m8469y.
Повний текст джерела國立臺灣大學
電子工程學研究所
105
This thesis presents a wide-rage wireline transmitter system in 40 nm CMOS technology. It can provide the receiver for testing with different standard of wireline communication such as 25 Gb/s、28 Gb/s and 32 Gb/s. It can also generate different types of PRBS data sequence:27-1、215-1、223-1、231-1 and four types of error injection rate to data sequence:10-3, 10-6, 10-9, and 0. With a built-in wide-rage phase-locked Loop, it can regard as a clock source of the system, which can be operated up to 32 Gb/s. This wireline transmitter system includes multiplexers, flip-flops, dividers, feed-forward equalizer and phase-locked loop. It can be triggered full-rate output data sequence by half-rate clock output from phase-locked loop integrated in the chip. Also, the channel loss can be compensated by the driver with feed-forward equalizer while transmitting data sequence. Also, the clock sample the data at the best sampling point under different frequency by the auto phase adjusted circuit. The measurement output data rate is up to 32 Gb/s and the output swing is 700mV in differential when feed-forward equalizer is ON. The whole system consumes 755mW. It can be selected different types of PRBS pattern, error injection and boosting amount of feed-forward equalizer by controlling the field programmable gate array (FPGA). The data sequence and error injection are confirmed in the operating range 20 Gb/s ~ 32 Gb/s under the bit-error-rate tester (BERT). Besides measuring the chip by bonding wire, the whole system is also packaged in QFN (Quad Flat No leads) to make the whole chip more complete.
Ganesan, Abhinav. "Precoding for Interference Management in Wireless and Wireline Networks." Thesis, 2014. http://hdl.handle.net/2005/3190.
Повний текст джерелаVijayvaradharaj, T. M. "Network Coding for Wirless Relaying and Wireline Networks." Thesis, 2014. http://etd.iisc.ernet.in/handle/2005/2892.
Повний текст джерелаJin, Jun-De, and 金俊德. "Microwave CMOS Integrated Amplifiers for Wireless/Wireline Communications." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/17724076327544554783.
Повний текст джерела國立清華大學
電子工程研究所
97
This study proposed new circuit design techniques to achieve high-performance CMOS integrated amplifiers for wireless/line communications at microwave frequencies. The design concepts were demonstrated by one narrowband and one broadband amplifiers, which were both realized in the standard 0.18-μm RF CMOS technology. The measured results presented superior performances compared with other published works using a similar or even more advanced CMOS technology. The designed narrowband amplifier is a 24-GHz balanced amplifier (BA) with a gain up to 45 dB. An effective technique, π–type parallel resonance (PPR), was proposed to boost the high frequency gain of a MOSFET by resonating out the inherent capacitances. The miniaturized lumped-element coupler in the circuit occupies a chip area of only ~ 2 % compared to that of the conventional transmission-line coupler. The BA consumes 123 mW from a supply voltage of 1 V. The proposed CMOS BA presents the highest gain of 45.0 dB with a chip area of 0.97 × 0.63 mm2 (core area: 0.78 × 0.43 mm2) among the published narrowband amplifiers with similar technologies and operation frequencies. The designed broadband amplifier is a 40-Gb/s transimpedance amplifier (TIA). From the measured S-parameters, a transimpedance gain of 51 dBΩ and a 3-dB bandwidth up to 30.5 GHz were observed. A gain-bandwidth product (GBW) enhancement technique, π-type inductor peaking (PIP), is proposed to achieve a bandwidth enhancement ratio (BWER) of 3.31. In addition, the PIP topology used at the input stage decreases the noise current as the operation frequency increases. Under a 1.8 V supply voltage, the TIA consumes 60.1 mW with a chip area of 1.17 × 0.46 mm2. The proposed CMOS TIA presents a GBW per DC power figure-of-merit (GBP/Pdc) of 180.1 GHzΩ/mW.
Kao, Min-Sheng, and 高旻聖. "CMOS Analog Front-end Transceiver IC for Wireline Communications." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/68305604504950596777.
Повний текст джерела國立清華大學
通訊工程研究所
99
This study proposes several circuit design techniques to achieve high performance CMOS transceiver chipset for wire-line communication. The circuit concepts are demonstrated by a 20-Gb/s CMOS 0.13-μm laser/modulator driver design and a 10-Gb/s CMOS 0.18-μm limiting amplifier design. The performance evaluation are as good as the advanced expensive III-V compound technology and the fabricated CMOS circuits are suitable for further integration with SERDES, CDR, and CODEC ICs for wire-line communication due to the small die size and low power consumption. The proposed 20-Gb/s laser/modulator driver is fabricated in 0.13-µm mixed-signal 1.2/2.5V 1P8M CMOS process. This work consists of a shunt-series inductor peaking pre-driver stage and a pre-emphasis output driver stage with source de-generation configuration including inductive local feedback network to enhance the operation bandwidth. The data rate is measured up to 20-Gb/s with 3.5VPP S.E. output amplitude in driving 50-Ω output load when the input amplitude is less than 0.15VPP and the rise/fall time of output waveform is less than 22-ps. The total power consumption is 900-mW with 1.2/4.0V dual supply and the chip die size is 900×800-µm2. The proposed 10-Gb/s current mode logic (CML) limiting amplifier is fabricated in 0.18-µm 1P6M CMOS process. This work consists of input equalizer, CML output buffer and gain stages with active-load inductive peaking, duty cycle correction (DCC) and gain control features. The circuit techniques include active load inductive peaking, source de-generation peaking and active feedback with current buffer in Cherry-Hooper topology to enhance operation bandwidth. The proposed design provides 600-mVpp differential voltage swing in driving 50-Ω output loads, 40-dB input dynamic range, 40-dB voltage gain and 8-mVpp input sensitivity. The total power consumption is 85-mW with 1.8V supply and the chip die size is 700×400-µm2.
Dunwell, Dustin. "Adaptive Receivers for High-speed Wireline Links." Thesis, 2013. http://hdl.handle.net/1807/35810.
Повний текст джерелаLo, Tien-Yu, and 羅天佑. "High Performance CMOS Transconductors and Gm-C Filters for Wireless Communications and Wireline Systems." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/89842446152267168562.
Повний текст джерела國立交通大學
電信工程系所
96
There are growing demands for low-supply circuits and systems. This is especially true for system-on-a-chip application. Switching to use lower power supply voltage, digital circuits do not suffer the degradation of their performances too much. On the other hand, for analog circuits, the circuit performances are strongly affected by the low voltage supply. In addition, the chip area should also be taken into consideration to reduce large costs of advanced multi-function SOC design. Therefore, new design techniques for analog circuits are required to be developed. In this research work, novel transconductors with the applications to wireless and wireline systems are introduced. The transconductor is a basic building block for analog circuits, such as the Gm-C filter, continuous-time delta sigma modulator, voltage controlled oscillator and multiplier. Two transconductors working at high frequency is developed at first. The short channel effects in the nano-scale technology are discussed and eliminated, and the results show the high performance even at high speed operation. A wide tuning range Gm-C filter with a 5th-order Elliptic prototype for very low frequency is discussed. Through the use of switching technology, the filter can operate from the biomedical systems and the audio systems to part of wireless systems. The distortion performance maintained over the tuning range is also shown. Three multi-mode channel section filters for the Zero-IF direct conversion receiver are presented. These filters cover the wireless applications of GSM, bluetooth, cdma2000, wideband CDMA and IEEE 802.11 a/b/g/n Wireless LANs. The specific transconductors with required function are designed. Through the use of a 3th-order Butterworth prototype, the results are shown to meet the specifications of various wireless applications. Two high speed filters with a 4th-order equiripple prototype are presented. The high speed filter can be used for pulse signal systems. One is designed for the hard disk storage systems. A novel automatic tuning circuit is also implemented to account for process and temperature variations. The other is designed for the UWB system. This circuit can work well under a low supply voltage.