Готові списки джерел за темами / Wafer-Scale mapping

Добірка наукової літератури з теми "Wafer-Scale mapping"

Автор: Grafiati

Опубліковано: 22 червня 2024

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Статті в журналах з теми "Wafer-Scale mapping":

Tajima, Michio, E. Higashi, Toshihiko Hayashi, Hiroyuki Kinoshita, and Hiromu Shiomi. "Characterization of SiC Wafers by Photoluminescence Mapping." Materials Science Forum 527-529 (October 2006): 711–16. http://dx.doi.org/10.4028/www.scientific.net/msf.527-529.711.

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The effectiveness of room-temperature photoluminescence (PL) mapping was demonstrated for nondestructive detection of structural defects, such as dislocations, micropipes and stacking faults, in SiC wafers. PL spectra of bulk wafers were dominated by deep-level emissions due to Si vacancies, vanadium and undefined centers like UD-1 at room temperature, while those from epitaxial wafers involved near band-edge emission. We developed a whole-wafer PL intensity mapping system with a capability of zooming in on the area of interest with a spatial resolution as high as 1 μm, and showed that the mapping patterns agree well with the etch-pit patterns originating from the structural defects both on a wafer scale and on a microscopic scale. The intensity contrast around the defects varied depending on the emission band, suggesting differences in their interactions with impurities and point defects.

Mackenzie, David M. A., Kristoffer G. Kalhauge, Patrick R. Whelan, Frederik W. Østergaard, Iwona Pasternak, Wlodek Strupinski, Peter Bøggild, Peter U. Jepsen, and Dirch H. Petersen. "Wafer-scale graphene quality assessment using micro four-point probe mapping." Nanotechnology 31, no. 22 (March 13, 2020): 225709. http://dx.doi.org/10.1088/1361-6528/ab7677.

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Miner, C. J. "Wafer-scale temperature mapping for molecular beam epitaxy and chemical beam epitaxy." Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures 11, no. 3 (May 1993): 998. http://dx.doi.org/10.1116/1.586910.

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Buron, Jonas D., David M. A. Mackenzie, Dirch H. Petersen, Amaia Pesquera, Alba Centeno, Peter Bøggild, Amaia Zurutuza, and Peter U. Jepsen. "Terahertz wafer-scale mobility mapping of graphene on insulating substrates without a gate." Optics Express 23, no. 24 (November 16, 2015): 30721. http://dx.doi.org/10.1364/oe.23.030721.

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Crovetto, Andrea, Patrick Rebsdorf Whelan, Ruizhi Wang, Miriam Galbiati, Stephan Hofmann, and Luca Camilli. "Nondestructive Thickness Mapping of Wafer-Scale Hexagonal Boron Nitride Down to a Monolayer." ACS Applied Materials & Interfaces 10, no. 30 (July 6, 2018): 25804–10. http://dx.doi.org/10.1021/acsami.8b08609.

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Meshot, Eric R., Sei Jin Park, Steven F. Buchsbaum, Melinda L. Jue, Tevye R. Kuykendall, Eric Schaible, Leonardus Bimo Bayu Aji, Sergei O. Kucheyev, Kuang Jen J. Wu, and Francesco Fornasiero. "High-yield growth kinetics and spatial mapping of single-walled carbon nanotube forests at wafer scale." Carbon 159 (April 2020): 236–46. http://dx.doi.org/10.1016/j.carbon.2019.12.023.

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Tian, Mengchuan, Ben Hu, Haifang Yang, Chengchun Tang, Mengfei Wang, Qingguo Gao, Xiong Xiong, et al. "Wafer Scale Mapping and Statistical Analysis of Radio Frequency Characteristics in Highly Uniform CVD Graphene Transistors." Advanced Electronic Materials 5, no. 4 (February 13, 2019): 1800711. http://dx.doi.org/10.1002/aelm.201800711.

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Yao, Yong Zhao, Yukari Ishikawa, Koji Sato, Yoshihiro Sugawara, Katsunori Danno, Hiroshi Suzuki, and Takeshi Bessho. "Large-Area Mapping of Dislocations in 4H-SiC from Carbon-Face (000-1) by Using Vaporized KOH Etching near 1000 °C." Materials Science Forum 740-742 (January 2013): 829–32. http://dx.doi.org/10.4028/www.scientific.net/msf.740-742.829.

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To solve the problem that no preferential chemical etching is available for dislocation revelation from the carbon-face (C-face) of 4H-SiC, a novel etching technique using vaporized KOH has been developed. It was found that this etching technique can reveal the three commonly found dislocation types, i.e., threading screw dislocations (TSDs), threading edge dislocations (TEDs) and basal plane dislocations (BPDs) as large hexagonal, small hexagonal and triangular, respectively. Centimeter-scale dislocation mapping has been obtained, and the pit positions on the C-face were compared with those on the Si-face, to study the dislocation propagation behaviors across the sample thickness. We have found one-to-one correlation for nearly 96% of the TSDs, indicating a dominant proportion of TSDs penetrate the whole wafer thickness. The vaporized KOH etching technique has provided an effective and inexpensive method of making inch-scale mapping of dislocation distribution for the C-face epitaxial and bulky 4H-SiC.

Shih, Po-Chou, Chun-Chin Hsu, and Fang-Chih Tien. "Automatic Reclaimed Wafer Classification Using Deep Learning Neural Networks." Symmetry 12, no. 5 (May 2, 2020): 705. http://dx.doi.org/10.3390/sym12050705.

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Silicon wafer is the most crucial material in the semiconductor manufacturing industry. Owing to limited resources, the reclamation of monitor and dummy wafers for reuse can dramatically lower the cost, and become a competitive edge in this industry. However, defects such as void, scratches, particles, and contamination are found on the surfaces of the reclaimed wafers. Most of the reclaimed wafers with the asymmetric distribution of the defects, known as the “good (G)” reclaimed wafers, can be re-polished if their defects are not irreversible and if their thicknesses are sufficient for re-polishing. Currently, the “no good (NG)” reclaimed wafers must be first screened by experienced human inspectors to determine their re-usability through defect mapping. This screening task is tedious, time-consuming, and unreliable. This study presents a deep-learning-based reclaimed wafers defect classification approach. Three neural networks, multilayer perceptron (MLP), convolutional neural network (CNN) and Residual Network (ResNet), are adopted and compared for classification. These networks analyze the pattern of defect mapping and determine not only the reclaimed wafers are suitable for re-polishing but also where the defect categories belong. The open source TensorFlow library was used to train the MLP, CNN, and ResNet networks using collected wafer images as input data. Based on the experimental results, we found that the system applying CNN networks with a proper design of kernels and structures gave fast and superior performance in identifying defective wafers owing to its deep learning capability, and the ResNet averagely exhibited excellent accuracy, while the large-scale MLP networks also acquired good results with proper network structures.

Lang, Simon, Alexandra Schewski, Ignaz Eisele, Christoph Kutter, and Wilfried Lerch. "(Best Paper Award) Aluminum Josephson Junction Formation on 200mm Wafers Using Different Oxidation Techniques." ECS Meeting Abstracts MA2023-01, no. 29 (August 28, 2023): 1791. http://dx.doi.org/10.1149/ma2023-01291791mtgabs.

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For superconducting quantum circuits with a large number of Qubits, reproducible components are crucial for reducing entanglement decoherence. Particularly for reliable industrial manufacturing on full-scale 200 mm' wafers, a very high uniformity level is required to ensure sufficient coherence times. In the present work the special focus was put on manufacturing Al/AlOx/Al Josephson junctions (JJ), which are the most important component of many quantum circuit. Fully Al-based CMOS-compatible JJ’s were produced using a double dry etch process. After patterning the first Al metallization several oxidation processes have been investigated. Static oxidation has been performed by first removing the native AlOx in a multi-chamber system with Ar milling. The final tunneling oxide was controlled by applying a specific pressure in the chamber under a pure O2 atmosphere. Afterwards, without breaking the vacuum, the second Al metallization has been deposited by sputtering. Oxide thicknesses between 1 and 2.5 nm were achieved. A full mapping of the process homogeneity will be given. On the other hand, a dynamic recipe controlled plasma oxidation process was performed, where the native AlOx was first removed by a H2 plasma followed by a defined reoxidation with an oxygen plasma. The resulting oxides had thicknesses up to 10 nm. The second Al metallization was again deposited by sputtering. Both oxidation processes were carefully studied to understand the initial oxidation process of the aluminum surface. Special attention was devoted to the non-destructive removal of the native AlOx with respect to the Al interface. Because the oxide thicknesses varied between 1 and 10 nm, the transition between direct and Fowler-Nordheim tunneling could be investigated. The process-stability on full scale 200 mm wafers and on chip size could be determined via test structures as well as the resistance variation of the Josephson junctions. Furthermore, the electrical properties of the different oxides could be measured and analyzed on wafer level. These studies provide insight into the structure and composition of the aluminum oxides and the applicability for Qubits.

Більше джерел

Дисертації з теми "Wafer-Scale mapping":

Jrondi, Aiman. "Optimisation de couches minces de nitrures de métaux de transition pour application micro-supercondensateurs." Electronic Thesis or Diss., Université de Lille (2022-....), 2023. https://pepite-depot.univ-lille.fr/ToutIDP/EDSMRE/2023/2023ULILR074.pdf.

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Répondant à la demande croissante de l'Internet des objets pour des solutions énergétiques compactes, notre recherche a optimisé les micro-supercondensateurs en nitrure de vanadium (VN) et de molybdène (Mo2Ny), élaborés par pulvérisation cathodique magnétron en atmosphère réactive, en mettant l'accent sur le rôle crucial de la concentration d'azote dans le plasma. Pour VN, nous obtenons grâce à l'optimisation des paramètres de dépôt, une capacité surfacique exceptionnelle d'environ 1,4 F.cm⁻² (pour un film de 32 µm d'épaisseur), et une stabilité de cyclage sans précédent, résistant à une dégradation de performance même après 150 000 cycles de charge à haut régime de cyclage, avec 25% de différence de capacité entre une vitesse de balayage à 0,2 et 1,6 V.s−1. Cette performance durable s'étendait sur 13 mois de stockage sous air, avec une rétention de capacité impressionnante de 85 % après 50 000 cycles, indiquant un très faible vieillissement des électrodes VN optimisées. Alors que sur le Mo2Ny, l'optimisation des conditions de dépôt à conduit vers un film poreux, ayant une capacité spécifique égale au VN dans l'électrolyte KOH 1M et supérieur dans le H2SO4 0,5M, ce qui le place comme une microélectrode positive potentielle pour un microsupercondensateurs asymétrique. Par ailleurs, Notre recherche souligne également l'importance critique de la cartographie d'homogénéité pour assurer la reproductibilité et l'efficacité à grande échelle, en améliorant le niveau de maturité technologique (Technology Readiness Level TRL) dans les procédés de la microélectronique, préparant le terrain pour une transition réussie de la technologie des MSC du laboratoire à l'industrie
Responding to the growing demand for compact energy solutions in the Internet of Things, our research has optimized micro-supercapacitors using vanadium nitride (VN) and molybdenum nitride (Mo2Ny), developed through magnetron sputtering in a reactive atmosphere, focusing on the crucial role of nitrogen concentration in the plasma. For VN, thanks to the optimization of deposition parameters, we achieve an exceptional surface capacity of approximately 1.4 F.cm⁻² (for a 32 µm thick film) and unprecedented cycling stability, resisting performance degradation even after 150,000 high-rate charging cycles, with a 25% capacity difference between scanning speeds of 0.2 and 1.6 V.s−1. This enduring performance extended over 13 months of storage in air, with an impressive capacity retention of 85% after 50,000 cycles, indicating very low aging of the optimized VN electrodes.In contrast, for Mo2Ny, optimizing deposition conditions led to a porous film, with a specific capacity equal to VN in 1M KOH electrolyte and superior in 0.5M H2SO4, positioning it as a potential positive micro-electrode for asymmetric micro-supercapacitors. Furthermore, our research also underscores the critical importance of homogeneity mapping to ensure reproducibility and large-scale efficiency, enhancing the Technology Readiness Level (TRL) in microelectronics processes, and paving the way for a successful transition of MSC technology from the laboratory to industry

Тези доповідей конференцій з теми "Wafer-Scale mapping":

Lin, Yishuang, Rongjian Liang, Yaguang Li, Hailiang Hu, and Jiang Hu. "Mapping Large Scale Finite Element Computing on to Wafer-Scale Engines." In 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC). IEEE, 2022. http://dx.doi.org/10.1109/asp-dac52403.2022.9712538.

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Rahman, Anis. "T-ray Profile Mapping for Wafer-scale Die Sorting and Yield Improvement." In 3D Image Acquisition and Display: Technology, Perception and Applications. Washington, D.C.: Optica Publishing Group, 2023. http://dx.doi.org/10.1364/3d.2023.dm4a.3.

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Wu, Zon-Ru, Tzu-Chieh Kao, Chia-Wei Kao, Ping-Chien Chang, Wei Lin, and Yung-Jr Hung. "Wafer-scale grating mapping system for rapid pitch and diffraction efficiency measurement." In 2019 24th OptoElectronics and Communications Conference (OECC) and 2019 International Conference on Photonics in Switching and Computing (PSC). IEEE, 2019. http://dx.doi.org/10.23919/ps.2019.8817627.

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"A Software Framework for Mapping Neural Networks to a Wafer-scale Neuromorphic Hardware System." In 6th International Workshop on Artificial Neural Networks and Intelligent Information Processing. SciTePress - Science and and Technology Publications, 2010. http://dx.doi.org/10.5220/0003024200430052.

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James, Michael, Marvin Tom, Patrick Groeneveld, and Vladimir Kibardin. "ISPD 2020 Physical Mapping of Neural Networks on a Wafer-Scale Deep Learning Accelerator." In ISPD '20: International Symposium on Physical Design. New York, NY, USA: ACM, 2020. http://dx.doi.org/10.1145/3372780.3380846.

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Warn, Colin, Andriy Sherehiy, Moath Alqatamin, Brooke Ritz, Ruoshi Zhang, Sri S. Chowdhury, Danming Wei, and Dan O. Popa. "Machine Vision Tracking and Automation of a Microrobot (sAFAM)." In ASME 2022 17th International Manufacturing Science and Engineering Conference. American Society of Mechanical Engineers, 2022. http://dx.doi.org/10.1115/msec2022-85424.

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Abstract In this paper, we propose a method for tracking a microrobot’s three-dimensional position using microscope machine vision. The microrobot, theSolid Articulated Four Axis Microrobot (sAFAM), is being developed to enable the assembly and manipulation of micro and nanoscale objects. In the future, arrays of sAFAMS working together can be integrated into a wafer-scale nanofactory, Prior to use, microrobots in this microfactory need calibration, which can be achieved using the proposed measurement technique. Our approach enables faster and more accurate mapping of microrobot translations and rotations, and orders of magnitude larger datasets can be created by automation. Cameras feeds on a custom microscopy system is fed into a data processing pipeline that enables tracking of the microrobot in real-time. This particular machine vision method was implemented with a help of OpenCV and Python and can be used to track the movement of other micrometer-sized features. Additionally, a script was created to enable automated repeatability tests for each of the six trajectories traversable by the robot. A more precise microrobot workable area was also determined thanks to the significantly larger datasets enabled by the combined automation and machine vision approaches.