Дисертації з теми "Very Large Floating Structures"

Proposed designs for Very Large Floating Structures motivate us to understand water-wave propagation through arrays of hundreds, or possibly thousands, of floating structures. The water-wave problems we study are each formulated under the usual conditions of linear wave theory. We study the frequency-domain problem of water-wave propagation through a periodically arranged array of structures, which are solved using a variety of methods. In the first instance we solve the problem for a periodically arranged infinite array using the method of matched asymptotic expansions for both shallow and deep water; the structures are assumed to be small relative to the wavelength and the array periodicity, and may be fixed or float freely. We then solve the same infinite array problem using a numerical approach, namely the Rayleigh-Ritz method, for fixed cylinders in water of finite depth and deep water. No limiting assumptions on the size of the structures relative to other length scales need to be made using this method. Whilst we aren t afforded the luxury of explicit approximations to the solutions, we are able to compute diagrams that can be used to aid an investigation into negative refraction. Finally we solve the water-wave problem for a so-called strip array (that is, an array that extends to infinity in one horizontal direction, but is finite in the other), which allows us to consider the transmission and reflection properties of a water-wave incident on the structures. The problem is solved using the method of multiple scales, under the assumption that the evolution of waves in a horizontal direction occurs on a slower scale than the other time scales that are present, and the method of matched asymptotic expansions using the same assumptions as for the infinite array case.

This thesis develops a mixed mode function – boundary element method (BEM) to analyze the dynamics of an integrated airplane – floating structure – water interaction system subject to airplane landing impacts. The airplane and the floating structure are treated as two solid substructures of which the motions are represented by their respective modal functions. The landing gear system of the airplane is modelled with a few linear spring – damper units connecting the airplane and the floating structure. The water is assumed to be inviscid and incompressible and the fluid motion is irrotational. Under a linear potential theory, the motion of the fluid is governed by the Laplace equation and the related boundary conditions. A linearised composite free surface boundary condition and an undisturbed far field (infinity) radiation condition are considered. The Green function, or kernel, of BEM formulation is a fundamental solution of the Laplace equation assuming an infinite fluid domain. The motion of the floating structure and the surrounding fluid are coupled through the wetted surface interface conditions. The coupled equations of the airplane, the floating structure and the surrounding fluid are solved using a step by step time integration procedure based on the Newmark assumptions. A FORTRAN program MMFBEP is written to implement the proposed numerical method. A few examples are completed to validate the mathematical model and the developed computer code. In comparing the available numerical and experimental results reported in the literature, sound agreements are reached. It is hoped that the developed method and computer code may be further improved and modified to provide an engineering tool for the dynamic design of Very Large Floating Structures (VLFS).

Thesis: Ph. D., Massachusetts Institute of Technology, Department of Aeronautics and Astronautics, 2015.
This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Cataloged from student-submitted PDF version of thesis.
Includes bibliographical references (pages 207-221).
Although advances in computing have increased the limits of three-dimensional computational solid mechanics, structural elements remain essential in the practical design of very large thin structures such as aircraft fuselages, ship hulls, automobiles, submarines, and pressure vessels. In many applications, fracture is a critical design concern, and thus the ability to numerically predict crack propagation in shells is a highly desirable goal. There are relatively few tools devoted to computational shell fracture, and of the existing approaches, there are two main defects: First, the existing methods are not scalable, in the sense of parallel computing, and consequently simulation of large structures remains out of reach. Second, while the existing approaches treat in-plane tensile failure, fracture due to transverse shearing has largely been ignored. In this thesis, a new computational framework for simulating deformation and fracture in large shell structures is presented that is well-suited to parallel computation. The scalability of the framework derives from the combination of a discontinuous Galerkin (DG) finite element method with an interface element-based cohesive zone representation of fracture. This representation of fracture permits arbitrary crack propagation, branching, and merging, without on-the-fly mesh topological changes. Furthermore, in parallel computing, this propagation algorithm is indifferent to processor boundaries. The adoption of a shear-flexible shell theory is identified as a necessary condition for modeling transverse shear failure, and the proposed method is formulated accordingly. Locking is always an issue that emerges in numerical analysis of shear-flexible shells; here, the inherent flexibility afforded by DG methods in the choice of approximation spaces is exploited to prevent locking naturally, without recourse to mixed methods or reduced integration. Hence, the DG discretization elegantly solves both the problems of scalability and locking simultaneously. A stress resultant-based cohesive zone theory is proposed that considers transverse shear, as well as bending and in-plane membrane forces. The theory is quite general, and the specification of particular constitutive relations, in the form of resultant traction-separation laws, is independent of the discretization scheme. Thus, the proposed framework should be extensible and useful for a variety of applications. A detailed description of the implementation strategy is provided, and numerical examples are presented which demonstrate the ability of the framework to capture all of the relevant modes of fracture in thin bodies. Finally, a numerical example of explosive decompression in a commercial airliner is shown as evidence that the proposed framework can successfully perform shell fracture simulations of unprecedented size.
by Brandon Louis Talamini.
Ph. D.

Large-scale reconfigurable and programmable analog devices provide a new option for prototyping and synthesizing analog circuits for analog signal processing and beyond. Field-programmable analog arrays (FPAAs) built upon floating gate transistor technologies provide the analog reconfigurability and programmability density required for large-scale devices on a single integrated circuit (IC). A wide variety of synthesized circuits, such as OTA followers, band-pass filters, and capacitively coupled summation/difference circuits, were measured to demonstrate the flexibility of FPAAs. Three generations of devices were designed and tested to verify the viability of such floating gate based large-scale FPAAs. Various architectures and circuit topologies were also designed and tested to explore the trade-offs present in reconfigurable analog systems. In addition, large-scale FPAAs have been incorporated into class laboratory exercises, which provide students with a much broader range of circuit and IC design experiences than have been previously possible. By combining reconfigurable analog technologies with an equivalent large-scale digital device, such as a field-programmable gate array (FPGA), an extremely powerful and flexible mixed signal development system can be produced that will enable all of the benefits possible through cooperative analog/digital signal processing (CADSP).

Floating-gate transistors similar to those used in FLASH and EEPROM can be used to build reconfigurable analog arrays. The charge on the floating gate can be modified to pass or block a signal in a cross-bar switch matrix, or it can be finely tuned to eliminate a threshold difference across a chip or set a bias. By using such a compact and versatile reconfigurable analog memory element, the number of analog circuit components included on an integrated circuit that is field-programmable is significantly higher. As a result, large-scale FPAAs can be built with the same impact on analog design that FPGAs have had on digital design. In my research, I investigate the areas floating-gate transistors can be used to impact FPAA design and implementation. An FPAA can be broken up into two basic components, elements of connection and elements of computation. With respect to connection, I show that a floating-gate switch can be used in a cross-bar matrix in place of a transmission gate resulting in less parasitic capacitance and a more linear resistance for the same size transistor. I illuminate the programming issues relating to injecting a floating-gate for use as a switch, including the drain selection circuitry and rogue injection due to gate induced drain leakage. With respect to computation, I explain how a Multiple-Input Translinear Element, or MITE, can be augmented to fit in an FPAA framework. I also discuss two different MITE implementations compatible with CMOS technology, a subthreshold MOS design and a BJT MITE that uses a lateral BJT. Beyond FPAA components, I present two alternative FPAA systems. The first is a general purpose reconfigurable analog system that uses standard analog design components that have been augmented with floating-gates. The second FPAA is built upon MITE circuits, and is focused on supporting direct system synthesis. I conclude with a discussion of a future large-scale MITE FPAA.

碩士
逢甲大學
土木工程學系
106
Wind power generation is one of the well-known clean energy source. It is one of the focuses of many countries in the world, and there are many factors that must be considered in the design and assembly of wind turbines, such as aerodynamics, oceanography and the motion of the floating structures, etc. The purpose of current study is to use the connection of floating modules with the offshore wind turbines to maintain the stability of overall floating structures on the sea surface. Review of the previous literatures, a new method by a combination of “Nonlinear network dynamics of flexibility connected multi-modules very large floating structures” and “Spar-type offshore wind turbines” has been develop to perform the current study.

The increasing population density and the industrial expansion significantly affect the availability of land. In this context, the high modularity of Very Large Floating Structures (VLFSs) may indeed represent a promising alternative for multipurpose use. Furthermore, the interest for the sea as a source of renewable marine energy, particularly for wave energy, has tremendously increased in the last decade and years. Among the large diversity of Wave Energy Converters (WECs), the Oscillating Water Column (OWC) is one of the most promising concept. Moreover, when an OWC is incorporated in a VLFS, its efficiency in terms of wave energy absorption is not only increased, but also it has additionally the benefit of attenuating the heave motion of the floating structure. Hence, there is a growing interest in the development of an innovative VLFS equipped with OWC devices. In this scope, the mitigating effect of the OWC on the heave motion of the VLFS can be combined with an increased efficiency of the OWC, thus better contributing to supply energy for the facilities located on the floating system. The main goal of this PhD research is the investigation of a VLFS-OWC System conceived for a hypothetical installation in a Mediterranean area, characterized by a moderate wave climate. For this purpose, small-scale experiments have been carried out in the wave-current flume of the Maritime Engineering Laboratory (LABIMA) of Florence University. The laboratory tests focused on the effect of: (i) the OWC design parameters (i.e., OWC geometry); (ii) the incident wave conditions (i.e., regular and irregular wave trains); (iii) the damping induced by a non-linear air turbine (i.e., a self-rectifying impulse turbine) idealised by vents with different diameters in the OWC chamber roof; (iv) the length and the heave motion of the VLFS on the performance of the OWC, including the attenuating effect of the incorporated OWC on the heave motion of the VLFS-OWC system. The design of the fixed OWC, VLFS and VLFS-OWC models as well as the testing programme and laboratory procedures, are based on an extensive literature review of the available numerical and physical models on OWC devices and VLFS technologies. The main findings of this study may be summarized as follows: - the most dominant parameters affecting the performance of a fixed OWC are the chamber width (in wave propagation direction), the front wall draught and the damping induced by the air turbine; - the additional parameters affecting the efficiency of an OWC integrated in a VLFS are the length of the structure and the heave motion; - formulae are developed for predicting the heave motion of the VLFS-OWC system respectively, for regular waves and irregular waves; - formulae are developed for improving the prediction of the performance of a fixed OWC for a floating OWC (integrated in a VLFS) respectively, for regular irregular waves. These findings have contributed to improve the understanding of the functioning of the OWC device and the relative importance of the aforementioned parameters affecting the device under moderate wave climate.

An understanding of the problems associated with a very large light weight structure orbiting in space is of utmost importance at present. A knowledge of how the structure behaves under the influence of external disturbances in space should be available for any design and deployment of a structure in space. The life, efficiency, and function of the space structure are dependent on this knowledge. A mathematical formulation has been developed for an axially flexible structure executing a planar motion in a general orbit in space in order to determine dynamic and thermal effects in the structure due to various disturbances in a space environment. The characteristic dimension of the structure is very large (of the order of a few kilometers). We have studied the influences of the differential gravitational forces, the radiation heating, and the radiation pressure forces. Effects of these factors have been studied on the structure's axial deformation, its attitude motion and its orbit simultaneously. Results are obtained for various initial conditions and physical parameter values. It is observed that the differential gravitational forces do not have any appreciable effects on the structure's axial length and its attitude motion. Thermal effects are significant in producing appreciable structural deformation, and they also affect the attitude motion of the structure considerably. The radiation pressure forces are very significant in changing attitude motion of the space structure, but it causes negligible effects in producing longitudinal deformation of the structure. All of the above factors have insignificant effects on the orbit of the structure chosen in this study. Of all the three external disturbances, the radiation pressure forces are found to be strongest in affecting the orbit of the structure.

Layered multiconductor coupled slot and strip-slot structures are characterized by introducing the full-wave modal analysis as well as the quasi-TEM spectral domain technique. In the modal analysis, the electric and magnetic fields are constructed in terms of modal fields in different regions. Application of the boundary conditions at interfaces for the tangential components of the electric and magnetic fields results in the dyadic Green's function, which interrelates the tangential currents and electric fields at the boundaries of the layered structure. The slot fields and strip currents are expanded in terms of a set of known basis functions with unknown coefficients. Use of the Galerkin method leads to a set of algebraic equations. The non-trivial solutions for the propagation constants are found by setting the determinant of the algebraic equations equal to zero. All the other normal mode parameters including the modal impedances, the field and current eigenvectors are then computed by using the solutions of the propagation constants. In the quasi-TEM analysis, the Laplace equation is transformed to an ordinary differential equation in the spectral domain, the solution of which together with the boundary conditions yields the Green's function which interrelates the potential and the charge distribution at the interfaces of the layered structure. The charge distribution is expanded in terms of known functions with unknown coefficients which are subsequently evaluated by applying the Galerkin method. Once the charge distribution is found, the quasi-TEM characteristics of the coupled strip-slot structures are readily calculated. Different impedance definitions proposed in the literature for multiple coupled line structures are discussed. The only useful impedance definition in the design of microwave and millimeter-wave circuits is the one that results in a symmetric impedance matrix for a coupled line structure in a lossless, isotropic, and linear medium. The normal mode impedance definition as based on the reciprocity is used to systematically study the impedance characteristics of various coupled slot structures for the first time, which together with the propagation characteristics are used to compute equivalent circuit models for ideal coupled line structures. The applications of the coupled slot and strip-slot structures are illustrated through design examples of enhanced couplers and power dividers consisting of coupled line multiports. Time domain simulation of coupled multiconductor structures with slotted ground planes is also presented to exemplify the applications of the techniques developed in this thesis to layered interconnects and packaging structures in high-speed circuits. Some novel techniques to reduce the crosstalk noise in those structures are proposed with theoretical examples and experimental results.
Graduation date: 1994

Bibliography: leaves 188-203.
xxii, 203 leaves : ill. ; 30 cm.
Title page, contents and abstract only. The complete thesis in print form is available from the University Library.
In this thesis insect vision principles are applied to the main mechanism for motion detection. Advanced VLSI technologies are employed for designing smart micro-sensors in which the imager and processor are integrated into one monolithic device.
Thesis (Ph.D.)--University of Adelaide, Dept. of Electrical and Electronic Engineering, 1996

Bibliography: leaves 188-203.
xxii, 203 leaves : ill. ; 30 cm.
In this thesis insect vision principles are applied to the main mechanism for motion detection. Advanced VLSI technologies are employed for designing smart micro-sensors in which the imager and processor are integrated into one monolithic device.
Thesis (Ph.D.)--University of Adelaide, Dept. of Electrical and Electronic Engineering, 1996

Οι μονάδες επεξεργασίας δεδομένων αποτελούν τις βασικές δομικές μονάδες όλων των μικροεπεξεργαστών. Κάποια από τα κυκλώματα αυτής της κατηγορίας υλοποιούν τις βασικές αριθμητικές πράξεις πάνω σε δεδομένα τόσο σταθερής όσο και κινητής υποδιαστολής, ενώ κάποια άλλα αναλαμβάνουν την αναδιοργάνωση των δεδομένων αυτών για την επιτάχυνση του υπολογισμού. Σε επεξεργαστές ειδικού σκοπού, όπως οι επεξεργαστές πολυμέσων και γραφικών, οι μονάδες επεξεργασίας δεδομένων καταλαμβάνουν περισσότερο από το 30% του ολοκληρωμένου και η αποτελεσματική σχεδίαση τους έχει άμεσο αντίκτυπο στην απόδοση ολόκληρου του συστήματος. Στο μέλλον, αναμένεται πως ακόμα και οι επεξεργαστές γενικού σκοπού, θα είναι εξοπλισμένοι από εξειδικευμένους επιταχυντές, οι οποίοι θα εκτελούν απ’ ευθείας σε υλικό σύνθετους αλγορίθμους με μεγάλες υπολογιστικές απαιτήσεις. Η βάση όλων των προτεινόμενων λύσεων σ’ αυτή τη διατριβή είναι η αναλυτική εύρεση ενός εγγενώς απλούστερου αλγορίθμου, ο οποίος θα επιτρέπει την αποτελεσματική υλοποίηση των αντίστοιχων κυκλωμάτων ανεξάρτητα από την τεχνολογία που θα χρησιμοποιηθεί και από τους επιπλέον περιορισμούς που τυχόν θα επιβληθούν στο μέλλον κατά την κατασκευή των κυκλωμάτων αυτών. Η ανάλυση και τα πειραματικά αποτελέσματα που συλλέξαμε βασίζονται τόσο σε υλοποιήσεις σε επίπεδο τρανζίστορ, που είναι η κύρια μέχρι τώρα πρακτική σχεδίασης των μικροεπεξεργαστών υψηλών επιδόσεων, όσο και σε πλήρως αυτοματοποιημένες υλοποιήσεις. Φυσικά, στη δεύτερη περίπτωση η απόδοση των κυκλωμάτων επιβαρύνεται, τόσο σε καθυστέρηση όσο και σε ενέργεια, εξαιτίας των περιορισμών των αυτοματοποιημένων εργαλείων και την αναγκαστική χρήση των προσχεδιασμένων βιβλιοθηκών βασικών πυλών. Η μελέτη που πραγματοποιήσαμε στοχεύει στην πλήρη εξερεύνηση του χώρου λύσεων των κυκλωμάτων αυτών. Η ανάλυση της συμπεριφοράς τους πραγματοποιήθηκε χρησιμοποιώντας τις βέλτιστες καμπύλες της ενέργειας ως προς την καθυστέρηση, οι οποίες αποτελούν τον πιο έγκυρο τρόπο περιγραφής της απόδοσης ενός κυκλώματος. Τα κυκλώματα που παρουσιάζονται ανήκουν σε τρεις βασικές κατηγορίες. Στην πρώτη ανήκουν οι αθροιστές παράλληλου προθέματος, που χρησιμοποιούν τα κρατούμενα του Ling για την υλοποίηση της δυαδικής πρόσθεσης. Τα κρατούμενα που προτάθηκαν από τον Ling αποτελούν απλοποιημένες μορφές των κλασικών σχέσεων πρόβλεψης κρατουμένου και χρησιμοποιούνται αυτή τη στιγμή στην πλειοψηφία των εμπορικών επεξεργαστών. Το νέο κύκλωμα, που προτείναμε, αποτελεί ουσιαστικά τη γενίκευση των σχέσεων αυτών, επιτρέποντας την υλοποίηση τους με απλοποιημένες δομές παράλληλου προθέματος, με αποτέλεσμα τη μείωση τόσο της καθυστέρησης όσο και της απαιτούμενης ενέργειας. Η νέα τεχνική οδηγεί σε γρηγορότερα κυκλώματα ανεξάρτητα από τη λογική οικογένεια που θα χρησιμοποιηθεί (στατική ή δυναμική CMOS λογική) και το δένδρο παράλληλου προθέματος που θα επιλεγεί. Η δεύτερη κατηγορία αναφέρεται σε κυκλώματα αναδιάταξης των δεδομένων που είναι αποθηκευμένα μέσα στους καταχωρητές του επεξεργαστή. Η αποδοτική αναδιάταξη των δεδομένων καταλήγει να είναι σε πολλούς αλγορίθμους (κρυπτογραφία, ψηφιακή επεξεργασία σήματος, πολυμέσα) τόσο αναγκαία όσο και η γρήγορη υλοποίηση των βασικών αριθμητικών πράξεων, αλλά και η ταχεία επικοινωνία με τη μνήμη. H προσπάθεια μας εστιάστηκε στην αποδοτική υλοποίηση μιας γενικής εντολής αναδιάταξης δεδομένων, στοχεύοντας σε όσο το δυνατόν ταχύτερες υλοποιήσεις. Όλες οι εκδοχές που προτείναμε στηρίζονται σε μια νέα μορφή δικτύων ταξινόμησης, η οποία μας επιτρέπει να παρέχουμε λύσεις που είναι σημαντικά πιο αποδοτικές σε σχέση με τις ήδη υπάρχουσες. Τα κυκλώματα που προτείνουμε κατασκευάζονται με τη χρήση ενός μόνο κελιού υπολογισμού (διαφορετικό για κάθε δίκτυο ταξινόμησης) και διατηρούν μια πλήρως κανονική δομή. Το στοιχείο αυτό, συμβάλλει, πέρα από τη βελτίωση της απόδοσης, στην αποτελεσματικότερη χωροθέτηση του κυκλώματος και στη μείωση των αρνητικών επιδράσεων των γραμμών διασύνδεσης. Η τελευταία κατηγορία κυκλωμάτων αναφέρεται σε κυκλώματα που χρησιμοποιούνται για την υλοποίηση της πρόσθεσης αριθμών κινητής υποδιαστολής. Τα κυκλώματα που προτείνουμε χρησιμοποιούνται στα πιο κρίσιμα στάδια, από πλευράς καθυστέρησης, του υπολογισμού του αθροίσματος και αφορούν στην πρόσθεση των μεγεθών και στην κανονικοποίηση του αποτελέσματος. Αρχικά, περιγράφουμε μια εναλλακτική προσέγγιση για την υλοποίηση των αθροιστών μεγέθους των αριθμών κινητής υποδιαστολής. Οι νέες μονάδες εκμεταλλεύονται την αναπαράσταση συμπληρώματος ως προς ένα και τις γρήγορες μονάδες υπολογισμού του κρατουμένου, που βασίζονται στην τεχνική παράλληλου προθέματος. Προτείνουμε μια ενοποιημένη μεθοδολογία για το πως μπορούμε να παράγουμε δομές παράλληλου προθέματος ανεξάρτητα από το μέγεθος της λέξης εισόδου, ενώ καταφέρνουμε να ενώσουμε για πρώτη φορά τις απλοποιημένες σχέσεις κρατουμένου του Ling με την πρόσθεση αριθμών που ακολουθούν την αναπαράσταση συμπληρώματος ως προς ένα. Στη συνέχεια, περιγράφεται ένας νέος απλός τρόπος για την υλοποίηση της πρόβλεψης και της μέτρησης των προπορευόμενων μηδενικών που εμφανίζονται στα αποτελέσματα των πράξεων αριθμών κινητής υποδιαστολής. Με τη χρήση των νέων κυκλωμάτων η κανονικοποίηση του αποτελέσματος μπορεί να πραγματοποιηθεί σε λιγότερο χρόνο και με σημαντικά μικρότερη ενέργεια.
Data processing units (or simply datapath) constitute a major part of all microprocessors. They take over the execution of all arithmetic operations either of fixed point or floating-point data, while they are also responsible for the execution of the needed data rearrangements in order to speed up the computation. In application-specific processors used for media and graphics applications, datapath circuits occupy more than one third of the processor’s core area and their efficient design directly affects the energy-delay behavior of the whole circuit. In the near future, it is expected that even general-purpose processors will be equipped we specialized accelerators that will execute directly in hardware complex algorithms with large computational demands. The basis of all circuits presented in this thesis is the derivation of an inherently simpler algorithm that would allow their efficient implementation irrespective the technology used and the constraints that would be imposed in the future, concerning the reliable and more predictable circuit fabrication in very deep submicron technologies. Our analysis relies on full-custom transistor-level designs that is the most common technique employed in high-performance microprocessor design. The performance of some of the presented circuits has also been investigated using an automated design flow. It is expected that, in these cases, the performance of the presented circuits will be aggravated due to the limitations imposed by the design automation tools and the available standard cell library. In this study, we aim at fully exploring the design space of our circuits. For this reason, we derived an optimal energy-delay curve for each one of the examined circuits in order to analyze its behavior. An energy-delay curve is the most reliable metric for presenting the performance of a circuit and allows the designer to perform a fair comparison among various design alternatives and circuit topologies. The new circuits presented in this thesis belong to three categories. In the first class, we find the parallel prefix adders that adopt the carries proposed by Ling. These carries are a simplified form of the classic carry lookahead equations and they are used at the moment in the majority of commercial high-speed microprocessors. The newly proposed circuits are based on a transformation of the Ling carries that leads to more efficient parallel prefix structures, which are better suited for Ling-carry computation. This new technique offers faster implementations irrespective the logic family used (either static or dynamic CMOS) and the prefix structure selected for the implementation. The second class refers to circuits that rearrange the data stored inside one or more of the processor’s registers. Efficient data rearrangement ends up being, in many cases, such as cryptography, digital signal processing, and multimedia applications, as essential as the fast implementation of basic arithmetic operations and the high bandwidth processor-memory communication. Our effort has focused on the efficient implementation of one of the most versatile permutation instruction, aiming to the reduction of the delay of the corresponding circuit. The design of the proposed permutation units is put under a common framework and their functionality resembles that of sorting networks. All the presented variants are designed using a single processing element (different for each sorting network) and have a very regular structure. This fact significantly contributes to the delay reduction because of the regular placement of the circuits’ cells that also alleviates the interconnect delay overhead. The last class of circuits is used for the implementation of high-speed floating-point units. The proposed circuits participate in two of the most time critical parts of any floating-point adder that is the significand (or fraction) adder and the result normalization unit. At first, we describe an alternative implementation of the significant adder that employs the one’s complement representation in order to reduce the delay of the circuit. The proposed parallel-prefix structures are derived using a general design methodology that leads to efficient designs irrespective the wordlength of the input operands. Also, we managed for the first time to produce simplified parallel-prefix carry computation units for the case of one’s complement addition that rely on the definition of Ling carries. Secondly, we describe a simple and practical algorithm for counting the number of leading zeros that may appear in the result of floating-point addition. New circuits are also presented that simplify the design of the corresponding leading zero anticipation logic. Using the proposed structures, normalization can be performed with less delay and significantly reduced power dissipation compared to already known implementations.