Статті в журналах з теми "VERILOG IMPLEMENTATION"
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Koti, Mr Manjunath, and Dr Basavaraj I. Neelgar. "CAN Tx Frame Implementation using Verilog." Journal of University of Shanghai for Science and Technology 23, no. 07 (July 29, 2021): 1303–13. http://dx.doi.org/10.51201/jusst/21/07311.
Повний текст джерелаParamahamsa, Prof Mr YRK. "Implementation of Zigbee Transmitter using Verilog." International Journal for Research in Applied Science and Engineering Technology V, no. III (March 28, 2017): 1010–17. http://dx.doi.org/10.22214/ijraset.2017.3185.
Повний текст джерелаShet, Ganesh Gopal, Jamuna V, Shravani S, Nayana H G, and Pramod Kumar S. "Implementation of AES Algorithm using Verilog." JNNCE Journal of Engineering and Management 4, no. 1 (November 30, 2020): 17. http://dx.doi.org/10.37314/jjem.2020.040103.
Повний текст джерелаKrishna, T. Rama, T. Krishna Murthy, N. Vilasrao Sarode, P. Srilakshmi, and V. Geetha Sri. "Verilog HDL using LTE Implementation MAP Algorithm." International Journal of Innovative Research in Computer Science and Technology 10, no. 2 (March 30, 2022): 611–14. http://dx.doi.org/10.55524/ijircst.2022.10.2.115.
Повний текст джерелаZheng, Li Kun, Ya Li Chen, and Zhe Ying Li. "Design and Implementation of USB Transceiver with Verilog." Applied Mechanics and Materials 462-463 (November 2013): 604–8. http://dx.doi.org/10.4028/www.scientific.net/amm.462-463.604.
Повний текст джерелаPerali, Sri Phanindra, Nithin Krishna Madadi, and Rohith Reddy. "RTL Implementation of AMBA AHB Protocol using Verilog." International Journal for Research in Applied Science and Engineering Technology 11, no. 4 (April 30, 2023): 4056–63. http://dx.doi.org/10.22214/ijraset.2023.51179.
Повний текст джерелаJ, Padmini, and V. Nanammal. "FPGA Implementation of Digital Modulation Schemes Using Verilog HDL." International Journal for Research in Applied Science and Engineering Technology 10, no. 9 (September 30, 2022): 560–67. http://dx.doi.org/10.22214/ijraset.2022.46596.
Повний текст джерелаSreekanth, P. "Verilog Implementation of Image Compression Using Discrete Wavelet Transform." CVR Journal of Science & Technology 9, no. 1 (December 1, 2015): 21–25. http://dx.doi.org/10.32377/cvrjst0905.
Повний текст джерелаBalakrishna, J. "Design and Implementation of RFID Controller using Verilog HDL." International Journal for Research in Applied Science and Engineering Technology 9, no. VI (June 30, 2021): 4335–42. http://dx.doi.org/10.22214/ijraset.2021.35942.
Повний текст джерелаPari, Kumar. "Implementation of reduced memory Viterbi Decoder using Verilog HDL." IOSR Journal of Electronics and Communication Engineering 8, no. 4 (2013): 73–79. http://dx.doi.org/10.9790/2834-0847379.
Повний текст джерелаKong, Lingxi, Qirui Niu, and Pai Yang. "Design And Implementation of UART Based on Verilog HDL." Highlights in Science, Engineering and Technology 38 (March 16, 2023): 949–55. http://dx.doi.org/10.54097/hset.v38i.5981.
Повний текст джерелаB R, Vishwas, and Dr Sowmya K B. "Design and Implementation of Advanced Extensible Interface using Verilog." International Journal for Research in Applied Science and Engineering Technology 11, no. 8 (August 31, 2023): 1709–14. http://dx.doi.org/10.22214/ijraset.2023.55446.
Повний текст джерелаYang, Hui Jing, Hao Fan, and Huai Guo Dong. "Design and Implementation of a RISC Processor on FPGA." Advanced Materials Research 981 (July 2014): 58–61. http://dx.doi.org/10.4028/www.scientific.net/amr.981.58.
Повний текст джерелаKangralkar, Sonali, and Rajashri Khanai. "Design and Implementation of 8 point FFT using Verilog HDL." International Journal of Computer Applications 177, no. 11 (October 17, 2019): 4–6. http://dx.doi.org/10.5120/ijca2019919440.
Повний текст джерелаGhelani, Harsh H., Nilesh L. Jha, Rohan Naik, and Pragya Gupta. "FPGA Implementation of Configurable Linear Feedback Shift Register using Verilog." International Journal of Computer Sciences and Engineering 6, no. 4 (April 30, 2018): 143–46. http://dx.doi.org/10.26438/ijcse/v6i4.143146.
Повний текст джерелаKumarN, Naveen, Rohith S, and H. Venkatesh Kumar. "FPGA Implementation of OFDM Transceiver using Verilog - Hardware Description Language." International Journal of Computer Applications 102, no. 6 (September 18, 2014): 8–13. http://dx.doi.org/10.5120/17817-8752.
Повний текст джерелаpani, M. Chakra, J. S. S. Ramaraju, and Ch N. L. Sujatha. "Implementation of Cordic Algorithm for FPGA Based Computers Using Verilog." International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering 03, no. 08 (August 20, 2014): 11487–96. http://dx.doi.org/10.15662/ijareeie.2014.0308082.
Повний текст джерелаRziga, Faten Ouaja, Khaoula Mbarek, Sami Ghedira, and Kamel Besbes. "An efficient Verilog-A memristor model implementation: simulation and application." Journal of Computational Electronics 18, no. 3 (June 7, 2019): 1055–64. http://dx.doi.org/10.1007/s10825-019-01357-9.
Повний текст джерелаPadmaSree, L., Bekkam Satheesh, and N. Dhanalakshmi. "FPGA Implementation of Interrupt Controller (8259) by using Verilog HDL." International Journal of Computer Applications 48, no. 6 (June 30, 2012): 12–19. http://dx.doi.org/10.5120/7350-0045.
Повний текст джерелаRavindran, Ajith. "Workshop on Introduction to Verilog Modeling and FPGA Implementation [Chapters]." IEEE Solid-State Circuits Magazine 15, no. 3 (2023): 111–12. http://dx.doi.org/10.1109/mssc.2023.3285330.
Повний текст джерелаWisniewski, Remigiusz. "Design of Petri Net-Based Cyber-Physical Systems Oriented on the Implementation in Field Programmable Gate Arrays." Energies 14, no. 21 (October 28, 2021): 7054. http://dx.doi.org/10.3390/en14217054.
Повний текст джерелаNoorbasha, Fazal, K. Hari Kishore, P. Phani Sarad, A. Renuka, SK Meera Mohiddin, K. Jagadeesh Babu, B. V S. Phanindra, and M. Manasa. "A VLSI implementation of train collision avoidance system using Verilog HDL." International Journal of Engineering & Technology 7, no. 2.8 (March 19, 2018): 386. http://dx.doi.org/10.14419/ijet.v7i2.8.10468.
Повний текст джерелаQiu, Mo, Simin Yu, Yuqiong Wen, Jinhu Lü, Jianbin He, and Zhuosheng Lin. "Design and FPGA Implementation of a Universal Chaotic Signal Generator Based on the Verilog HDL Fixed-Point Algorithm and State Machine Control." International Journal of Bifurcation and Chaos 27, no. 03 (March 2017): 1750040. http://dx.doi.org/10.1142/s0218127417500407.
Повний текст джерелаMoubark, Asraf Mohamed, Mohd Alauddin Mohd Ali, Hilmi Sanusi, and Sawal Md Ali. "FPGA Implementation of Low Power Digital QPSK Modulator Using Verilog HDL." Journal of Applied Sciences 13, no. 3 (January 15, 2013): 385–92. http://dx.doi.org/10.3923/jas.2013.385.392.
Повний текст джерелаRizvi, Navaid Zafar, Rajat Arora, and Niraj Agrawal. "Implementation and Verification of Synchronous FIFO using System Verilog Verification Methodology." Journal of Communications Technology, Electronics and Computer Science 2 (November 21, 2015): 18. http://dx.doi.org/10.22385/jctecs.v2i0.19.
Повний текст джерелаSamsudin, Nooraisyah N., Dr Suhaila Isaak, and Dr Norlina Paraman. "Implementation of Optimized Low Pass Filter for ECG filtering using Verilog." Journal of Physics: Conference Series 2312, no. 1 (August 1, 2022): 012049. http://dx.doi.org/10.1088/1742-6596/2312/1/012049.
Повний текст джерелаKumari, U. Ratna, and T. K. Rasagna. "Implementation of Pipelined Data Encryption Standard for Security Enhancement through Verilog." International Journal of Computer Applications and Technology 1, no. 1 (July 10, 2012): 4–8. http://dx.doi.org/10.7753/2012.1002.
Повний текст джерелаTrivedi, Hardik, Rohit Kumar, Ronak Tank, Sundaresan C., and Madhushankara M. "Implementation of USB 3. 0 SuperSpeed Physical Layer using Verilog HDL." International Journal of Computer Applications 95, no. 24 (June 18, 2014): 1–5. http://dx.doi.org/10.5120/16739-6571.
Повний текст джерелаAswathy Krishnan, Nisha G. R,. "VIP Implementation for Mil-Std Manchester Encoder- Decoder Using System Verilog." International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering 04, no. 07 (July 20, 2015): 6010–25. http://dx.doi.org/10.15662/ijareeie.2015.0407027.
Повний текст джерелаSajjad, Redwan N., Ujwal Radhakrishna, and Dimitri A. Antoniadis. "A tunnel FET compact model including non-idealities with verilog implementation." Solid-State Electronics 150 (December 2018): 16–22. http://dx.doi.org/10.1016/j.sse.2018.09.001.
Повний текст джерелаKumar, Manish, Priyanka Singh, and Shesha Singh. "A VLSI Implementation of Four-Phase Lift Controller Using Verilog HDL." IOP Conference Series: Materials Science and Engineering 225 (August 2017): 012137. http://dx.doi.org/10.1088/1757-899x/225/1/012137.
Повний текст джерелаYuan, Jun, Quan Yuan Feng, and Dan Wang. "Design of High-Precision FIR Filter Based on Verilog HDL." Advanced Materials Research 433-440 (January 2012): 5198–202. http://dx.doi.org/10.4028/www.scientific.net/amr.433-440.5198.
Повний текст джерелаZhao, Lin Hui, and Zhi Yuan Liu. "Vehicle State and Friction Force Estimation Based on FPGA." Applied Mechanics and Materials 336-338 (July 2013): 999–1002. http://dx.doi.org/10.4028/www.scientific.net/amm.336-338.999.
Повний текст джерелаTanawade, Neeta, and Sagun Sudhansu. "FPGA Implementation of Digital Modulation Techniques BPSK and QPSK using HDL Verilog." International Journal of Computer Applications 165, no. 12 (May 17, 2017): 44–50. http://dx.doi.org/10.5120/ijca2017914106.
Повний текст джерелаTeja, K. Babu Ravi. "Design and Implementation of Neighborhood Processing Operations on FPGA using Verilog HDL." IOSR journal of VLSI and Signal Processing 4, no. 1 (2014): 75–80. http://dx.doi.org/10.9790/4200-04127580.
Повний текст джерелаVenkataRao, P., and K. R. K. Sastry K.R.K.Sastry. "Implementation of Complex Matrix Inversion using Gauss-Jordan Elimination Method in Verilog." International Journal of Computer Applications 122, no. 3 (July 18, 2015): 6–9. http://dx.doi.org/10.5120/21678-4768.
Повний текст джерелаM. Rane, Sonali, Mrs Trupti Wagh, and Dr Mrs P. Malathi. "An Implementation of Double precision Floating point Adder & Subtractor Using Verilog." IOSR Journal of Electrical and Electronics Engineering 9, no. 4 (2014): 01–05. http://dx.doi.org/10.9790/1676-09430105.
Повний текст джерелаPremalatha, G., J. Mohana, S. Suvitha, and J. Manikandan. "Implementation of VLSI Based Efficient Lossless EEG Compression Architecture using Verilog HDL." Journal of Physics: Conference Series 1964, no. 6 (July 1, 2021): 062048. http://dx.doi.org/10.1088/1742-6596/1964/6/062048.
Повний текст джерела., NARAHARI BHARGAVI, and B. NAGA RAJESH . "VLSI IMPLEMENTATION OF HIGH SPEED SINGLE PRECESSION FLOATING POINT UNIT USING VERILOG." International Journal of Engineering Technology and Management Sciences 6, no. 1 (January 28, 2022): 16–23. http://dx.doi.org/10.46647/ijetms.2022.v06i01.003.
Повний текст джерелаNoorbasha, Fazal, K. Hari Kishore, T. Naveen, A. Sai Anusha, Y. Manisha, K. Revathi, and M. Manasa. "Implementation of modified Feistel block cipher for OTP generation using Verilog HDL." International Journal of Engineering & Technology 7, no. 2.8 (March 19, 2018): 392. http://dx.doi.org/10.14419/ijet.v7i2.8.10678.
Повний текст джерелаSanivarapu, Rambabu, Mallikarjuna Rao Y., Venkataiah C., Linga Murthy M.K., Laith H. Alzubaidi, and Vyeshikha. "Design and Implementation of POSIT Based Adder and Multiplier in Verilog HDL." E3S Web of Conferences 391 (2023): 01184. http://dx.doi.org/10.1051/e3sconf/202339101184.
Повний текст джерелаM S, Harish M. S., and Jayadevappa D. "Design & Simulation Of 64-Bit Hybrid Processor Instruction Set Using Verilog." International Journal of Engineering & Technology 7, no. 4.36 (December 9, 2018): 373. http://dx.doi.org/10.14419/ijet.v7i4.36.23809.
Повний текст джерелаM S, Harish M. S., and Jayadevappa D. "Design & Simulation Of 64-Bit Hybrid Processor Instruction Set Using Verilog." International Journal of Engineering & Technology 7, no. 4.36 (December 9, 2018): 373. http://dx.doi.org/10.14419/ijet.v7i4.36.23810.
Повний текст джерелаShaik, Samdhani, and P. Balanagu. "Functional Verification Architecture Implementation for Power Optimized FIR Filter." International Journal of Engineering & Technology 7, no. 2.20 (April 18, 2018): 287. http://dx.doi.org/10.14419/ijet.v7i2.20.14780.
Повний текст джерелаAgarwal, Aman, Arjun J. Anil, Rahul Nair, and K. Sivasankaran. "ASIC Implementation of DMA Controller." International Journal of Electrical and Electronics Research 4, no. 1 (March 31, 2016): 1–4. http://dx.doi.org/10.37391/ijeer.040101.
Повний текст джерелаQian, Xiang Ping, Wei Ming Qiao, Zhong Zu Zhou, Xi Meng Chen, and Lan Jing. "A Digital Regulator for FPGA Implementation." Advanced Materials Research 433-440 (January 2012): 4547–54. http://dx.doi.org/10.4028/www.scientific.net/amr.433-440.4547.
Повний текст джерелаK N, Hemalatha, Aishwarya Kamakodi, A. Soppia, A. Poornima, and Sangeetha B G. "Design And Implementation Of 64-Bit Ripple Carry Adder And Ripple Borrow Subtractor Using Reversible Logic Gates." International Journal of Advanced Networking and Applications 13, no. 06 (2022): 5215–19. http://dx.doi.org/10.35444/ijana.2022.13607.
Повний текст джерелаIbrahimy, Muhammad Ibn. "FPGA Implementation of Multiplier for Floating-Point Numbers Based on IEEE 754-2008 Standard." Journal of Communications Technology, Electronics and Computer Science 1 (October 22, 2015): 1. http://dx.doi.org/10.22385/jctecs.v1i0.2.
Повний текст джерелаAzhari, Zul Imran, Samsul Setumin, Emilia Noorsal, and Mohd Hanapiah Abdullah. "Digital image enhancement by brightness and contrast manipulation using Verilog hardware description language." International Journal of Electrical and Computer Engineering (IJECE) 13, no. 2 (April 1, 2023): 1346. http://dx.doi.org/10.11591/ijece.v13i2.pp1346-1357.
Повний текст джерелаSomashekhar, Vikas Maheshwari, and R. P. Singh. "FPGA Implementation of Fault Tolerant Adder using Verilog for High Speed VLSI Architectures." International Journal of Engineering and Advanced Technology 9, no. 4 (April 30, 2020): 549–51. http://dx.doi.org/10.35940/ijeat.d7062.049420.
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