Статті в журналах з теми "VEDIC MULTIPLIERS"
Оформте джерело за APA, MLA, Chicago, Harvard та іншими стилями
Ознайомтеся з топ-50 статей у журналах для дослідження на тему "VEDIC MULTIPLIERS".
Біля кожної праці в переліку літератури доступна кнопка «Додати до бібліографії». Скористайтеся нею – і ми автоматично оформимо бібліографічне посилання на обрану працю в потрібному вам стилі цитування: APA, MLA, «Гарвард», «Чикаго», «Ванкувер» тощо.
Також ви можете завантажити повний текст наукової публікації у форматі «.pdf» та прочитати онлайн анотацію до роботи, якщо відповідні параметри наявні в метаданих.
Переглядайте статті в журналах для різних дисциплін та оформлюйте правильно вашу бібліографію.
Eshack, Ansiya, and S. Krishnakumar. "Pipelined vedic multiplier with manifold adder complexity levels." International Journal of Electrical and Computer Engineering (IJECE) 10, no. 3 (June 1, 2020): 2951. http://dx.doi.org/10.11591/ijece.v10i3.pp2951-2958.
Повний текст джерелаKhubnani, Rashi, Tarunika Sharma, and Chitirala Subramanyam. "Applications of Vedic multiplier - A Review." Journal of Physics: Conference Series 2225, no. 1 (March 1, 2022): 012003. http://dx.doi.org/10.1088/1742-6596/2225/1/012003.
Повний текст джерелаRashno, Meysam, Majid Haghparast, and Mohammad Mosleh. "A new design of a low-power reversible Vedic multiplier." International Journal of Quantum Information 18, no. 03 (April 2020): 2050002. http://dx.doi.org/10.1142/s0219749920500021.
Повний текст джерелаBhairannawar, Satish s., Raja K B, Venugopal K R, and L. M. Patnaik. "EFFICIENT FPGA BASED MATRIX MULTIPLICATION USING MUX AND VEDIC MULTIPLIER." INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY 12, no. 5 (January 30, 2014): 3452–63. http://dx.doi.org/10.24297/ijct.v12i5.2915.
Повний текст джерелаNandha Kumar, P. "Design of Accuracy Based Fixed-Width Booth Multipliers Using Data Scaling Technology." Asian Journal of Electrical Sciences 11, no. 2 (December 15, 2022): 24–30. http://dx.doi.org/10.51983/ajes-2022.11.2.3524.
Повний текст джерелаCVS, Chaitanya, Sundaresan C, P. R. Venkateswaran, Keerthana Prasad, and V. Siva Ramakrishna. "Design of High-Speed Multiplier Architecture Based on Vedic Mathematics." International Journal of Engineering & Technology 7, no. 2.4 (March 10, 2018): 105. http://dx.doi.org/10.14419/ijet.v7i2.4.11228.
Повний текст джерелаKuruvilla, Siya Susan, Stephani Sunil, Abisha Susan Alichan, and Abraham K. Thomas. "Comparison of Vedic Multiplier Implementation Using Gate Diffusion Input and Modified Gate Diffusion Input Techniques." Journal of Signal Processing 8, no. 2 (June 22, 2022): 1–5. http://dx.doi.org/10.46610/josp.2022.v08i02.001.
Повний текст джерелаCVS, Chaitanya, Sundaresan C, and P. R Venkateswaran. "ASIC design of low power-delay product carry pre-computation based multiplier." Indonesian Journal of Electrical Engineering and Computer Science 13, no. 2 (February 1, 2019): 845. http://dx.doi.org/10.11591/ijeecs.v13.i2.pp845-852.
Повний текст джерелаGanjikunta, Ganesh Kumar, Sibghatullah I. Khan, and M. Mahaboob Basha. "A High-Performance Signed-Unsigned Multiplier Using Vedic Mathematics." Journal of Low Power Electronics 15, no. 3 (September 1, 2019): 302–8. http://dx.doi.org/10.1166/jolpe.2019.1616.
Повний текст джерелаProf. Parvaneh Basaligheh. "Design and Implementation of High Speed Vedic Multiplier in SPARTAN 3 FPGA Device." International Journal of New Practices in Management and Engineering 6, no. 01 (March 31, 2017): 14–19. http://dx.doi.org/10.17762/ijnpme.v6i01.51.
Повний текст джерелаProf. Sharayu Waghmare. "Vedic Multiplier Implementation for High Speed Factorial Computation." International Journal of New Practices in Management and Engineering 1, no. 04 (December 31, 2012): 01–06. http://dx.doi.org/10.17762/ijnpme.v1i04.8.
Повний текст джерелаC, Pradeepa S., Gowri G. Bennur, Hruthika G, Adithya M, and Acharya Vinay Vasudeva. "Design and VLSI Implementation of Vedic Multiplier using 45nm Technology." International Journal for Research in Applied Science and Engineering Technology 11, no. 5 (May 31, 2023): 964–68. http://dx.doi.org/10.22214/ijraset.2023.51676.
Повний текст джерелаJoshi, Shubhangi M. "Modified Vedic Multipliers: A Review." International Journal of Advanced Research in Computer Science and Software Engineering 7, no. 5 (May 30, 2017): 421–26. http://dx.doi.org/10.23956/ijarcsse/sv7i5/0255.
Повний текст джерелаSafoev, Nuriddin, and Jun-Cheol Jeon. "Design and Evaluation of Cell Interaction Based Vedic Multiplier Using Quantum-Dot Cellular Automata." Electronics 9, no. 6 (June 23, 2020): 1036. http://dx.doi.org/10.3390/electronics9061036.
Повний текст джерелаParadhasaradhi, Damarla, Bharinala Haridhar, A. V. Sreekanth Reddy, Dudipalli Sri Charan, and Atyam Lekhaz. "Implementation of Fast Convolution using Robust Vedic Multiplier of Radix-2." International Journal of Engineering & Technology 7, no. 2.7 (March 18, 2018): 626. http://dx.doi.org/10.14419/ijet.v7i2.7.10895.
Повний текст джерелаEt. al., Srilakshmi Kaza,. "Performance Analysis of Adiabatic Vedic Multipliers." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, no. 5 (April 11, 2021): 1429–35. http://dx.doi.org/10.17762/turcomat.v12i5.2039.
Повний текст джерелаPradhan, Manoranjan, and Rutuparna Panda. "Speed Comparison of 16x16 Vedic Multipliers." International Journal of Computer Applications 21, no. 6 (May 31, 2011): "12"—"19." http://dx.doi.org/10.5120/2516-3417.
Повний текст джерелаEshack, Ansiya, and S. Krishnakumar. "Reversible logic in pipelined low power vedic multiplier." Indonesian Journal of Electrical Engineering and Computer Science 16, no. 3 (December 1, 2019): 1265. http://dx.doi.org/10.11591/ijeecs.v16.i3.pp1265-1272.
Повний текст джерелаSharma, Tarunika, Rashi Khubnani, and Chitiralla Subramanyam. "Study of mathematics through indian veda’s : A review." Journal of Physics: Conference Series 2332, no. 1 (September 1, 2022): 012006. http://dx.doi.org/10.1088/1742-6596/2332/1/012006.
Повний текст джерелаGowreesrinivas, K. V., Sabbavarapu Srinivas, and Punniakodi Samundiswary. "FPGA Implementation of a Resource Efficient Vedic Multiplier using SPST Adders." Engineering, Technology & Applied Science Research 13, no. 3 (June 2, 2023): 10698–702. http://dx.doi.org/10.48084/etasr.5797.
Повний текст джерелаG., Suresh. "Approximate Compressors based Inexact Vedic Dadda Multipliers." HELIX 8, no. 1 (January 1, 2018): 2683–90. http://dx.doi.org/10.29042/2018-2683-2690.
Повний текст джерелаHari Kishore, K., Fazal Noorbasha, Katta Sandeep, D. N. V. Bhupesh, SK Khadar Imran, and K. Sowmya. "Linear convolution using UT Vedic multiplier." International Journal of Engineering & Technology 7, no. 2.8 (March 19, 2018): 409. http://dx.doi.org/10.14419/ijet.v7i2.8.10471.
Повний текст джерелаDeokate, Rajesh. "A Review on IEEE-754 Standard Floating Point Multiplier using Vedic Mathematics." International Journal for Research in Applied Science and Engineering Technology 9, no. VI (June 20, 2021): 1300–1303. http://dx.doi.org/10.22214/ijraset.2021.35242.
Повний текст джерелаMukkara, Lakshmi kiran, and K. Venkata Ramanaiah. "Neuronal Logic gates Realization using CSD algorithm." International Journal of Reconfigurable and Embedded Systems (IJRES) 8, no. 2 (July 1, 2019): 145. http://dx.doi.org/10.11591/ijres.v8.i2.pp145-150.
Повний текст джерелаGaur, F. Nidhi, S. Anu Mehra, and T. Pradeep Kumar. "Power and Area Efficient Vedic Multipliers Using Modified CSLA Architectures for DSP." Journal of Advanced Research in Dynamical and Control Systems 11, no. 10 (October 31, 2019): 44–51. http://dx.doi.org/10.5373/jardcs/v11i10/20193004.
Повний текст джерелаMOHANA KANNAN, LOGANATHAN, and DHANASKODI DEEPA. "LOW POWER VERY LARGE SCALE INTEGRATION (VLSI) DESIGN OF FINITE IMPULSE RESPONSE (FIR) FILTER FOR BIOMEDICAL IMAGING APPLICATION." DYNA 96, no. 5 (September 1, 2021): 505–11. http://dx.doi.org/10.6036/10214.
Повний текст джерелаPoornima, Y., and M. Kamalanathan. "Design of Low Power Vedic Multiplier Based Reconfigurable Fir Filter for DSP Applications." International Journal of Advance Research and Innovation 7, no. 2 (2019): 57–60. http://dx.doi.org/10.51976/ijari.721908.
Повний текст джерелаSreelakshmi, G., Kaleem Fatima, and B. K. Madhavi. "Efficient Realization of Vinculum Vedic BCD Multipliers for High Speed Applications." Circuits and Systems 09, no. 06 (2018): 87–99. http://dx.doi.org/10.4236/cs.2018.96009.
Повний текст джерелаP. VINAY, MALLIK, and HEMACHANDRA G. "Design of 2D-DCT and Quantization Using Dadda and Vedic Multipliers." i-manager's Journal on Digital Signal Processing 4, no. 3 (2016): 21. http://dx.doi.org/10.26634/jdp.4.3.8144.
Повний текст джерелаAnjana, S., C. Pradeep, and Philip Samuel. "Synthesize of High Speed Floating-point Multipliers Based on Vedic Mathematics." Procedia Computer Science 46 (2015): 1294–302. http://dx.doi.org/10.1016/j.procs.2015.01.054.
Повний текст джерелаSavadi, Anuradha, Raju Yanamshetti, and Shewta Biradar. "Design and Implementation of 64 Bit IIR Filters Using Vedic Multipliers." Procedia Computer Science 85 (2016): 790–97. http://dx.doi.org/10.1016/j.procs.2016.05.267.
Повний текст джерелаMehra, Anu, Vinay Verma, Rana Majumdar, Nidhi Gaur, Alok Kumar, Chanda Pandey, and Ansh Awasthi. "Comparative analysis of different Vedic algorithms for 8 × 8 binary multipliers." International Journal of Industrial and Systems Engineering 33, no. 2 (2019): 129. http://dx.doi.org/10.1504/ijise.2019.10024258.
Повний текст джерелаMehra, Anu, Vinay Verma, Rana Majumdar, Nidhi Gaur, Alok Kumar, Ansh Awasthi, and Chanda Pandey. "Comparative analysis of different Vedic algorithms for 8 × 8 binary multipliers." International Journal of Industrial and Systems Engineering 33, no. 2 (2019): 129. http://dx.doi.org/10.1504/ijise.2019.102466.
Повний текст джерелаS., Nagaraj. "Design and Analysis of 8-bit Array, Carry Save Array, Braun, Wallace Tree and Vedic Multipliers." International Journal of Psychosocial Rehabilitation 24, no. 3 (March 30, 2020): 2687–97. http://dx.doi.org/10.37200/ijpr/v24i3/pr2020305.
Повний текст джерелаBhargavi, Sandugari. "Design and Implementation of Area Efficient BIST Based Vedic and Wallace Tree Multipliers on FPGA." International Journal for Research in Applied Science and Engineering Technology 7, no. 4 (April 30, 2019): 3650–55. http://dx.doi.org/10.22214/ijraset.2019.4612.
Повний текст джерелаFatima, Nashrah, Taha Tanveer, and Brahmi Shrman. "Implementation for Minimization of Computation Time of Partial Products for Designing Multipliers using Tabulated Vedic Mathematics." International Journal of Computer Applications 128, no. 10 (October 15, 2015): 1–5. http://dx.doi.org/10.5120/ijca2015906638.
Повний текст джерелаNaveen, R. "Design and Analysis of Low Power Full Adders and 4*4 Vedic Multipliers Based on Urdhva Triyagbhyam." Asian Journal of Research in Social Sciences and Humanities 6, no. 7 (2016): 950. http://dx.doi.org/10.5958/2249-7315.2016.00479.2.
Повний текст джерелаSM, Vijaya, and Suresh K. "An Efficient Design Approach of ROI Based DWT Using Vedic and Wallace Tree Multiplier on FPGA Platform." International Journal of Electrical and Computer Engineering (IJECE) 9, no. 4 (August 1, 2019): 2433. http://dx.doi.org/10.11591/ijece.v9i4.pp2433-2442.
Повний текст джерелаSaraswathi, N., Lokesh Modi, and Aatish Nair. "Complex Number Vedic Multiplier and its Implementation in a Filter." International Journal of Engineering & Technology 7, no. 2.24 (April 25, 2018): 336. http://dx.doi.org/10.14419/ijet.v7i2.24.12078.
Повний текст джерелаJhamb, Mansi, and Manoj Kumar. "Optimized vedic multiplier using low power 13T hybrid full adder." Journal of Information and Optimization Sciences 44, no. 4 (2023): 675–87. http://dx.doi.org/10.47974/jios-1222.
Повний текст джерелаSharma, Vaishali. "Design, Implementation & Performance of Vedic Multiplier Based on Look Ahead Carry Adder for Different Bit Lengths." International Journal for Research in Applied Science and Engineering Technology 10, no. 1 (January 31, 2022): 24–30. http://dx.doi.org/10.22214/ijraset.2022.39759.
Повний текст джерелаKunchigik, Vaijyanath, Linganagouda Kulkarni, and Subhash Kulkarni. "Pipelined Vedic-Array Multiplier Architecture." International Journal of Image, Graphics and Signal Processing 6, no. 6 (May 8, 2014): 58–64. http://dx.doi.org/10.5815/ijigsp.2014.06.08.
Повний текст джерелаKivi Sona, M., and V. Somasundaram. "Vedic Multiplier Implementation in VLSI." Materials Today: Proceedings 24 (2020): 2219–30. http://dx.doi.org/10.1016/j.matpr.2020.03.748.
Повний текст джерелаPrabhu, E., H. Mangalam, and P. R. Gokul. "A Delay Efficient Vedic Multiplier." Proceedings of the National Academy of Sciences, India Section A: Physical Sciences 89, no. 2 (February 9, 2018): 257–68. http://dx.doi.org/10.1007/s40010-017-0464-4.
Повний текст джерелаKumar, M. Siva, Sanath Kumar Tulasi, N. Srinivasulu, Vijaya Lakshmi Bandi, and K. Hari Kishore. "Bit wise and delay of vedic multiplier." International Journal of Engineering & Technology 7, no. 1.5 (December 31, 2017): 26. http://dx.doi.org/10.14419/ijet.v7i1.5.9117.
Повний текст джерелаYadav, Jatin, Anupam Kumar, Shaik Shareef, Sandeep Bansal, and Navjot Rathour. "Comparative Analysis of Vedic Multiplier using Various Adder Architectures." Journal of Physics: Conference Series 2327, no. 1 (August 1, 2022): 012022. http://dx.doi.org/10.1088/1742-6596/2327/1/012022.
Повний текст джерелаBhavani, M., M. Siva Kumar, and K. Srinivas Rao. "Delay Comparison for 16x16 Vedic Multiplier Using RCA and CLA." International Journal of Electrical and Computer Engineering (IJECE) 6, no. 3 (June 1, 2016): 1205. http://dx.doi.org/10.11591/ijece.v6i3.9457.
Повний текст джерелаBhavani, M., M. Siva Kumar, and K. Srinivas Rao. "Delay Comparison for 16x16 Vedic Multiplier Using RCA and CLA." International Journal of Electrical and Computer Engineering (IJECE) 6, no. 3 (June 1, 2016): 1205. http://dx.doi.org/10.11591/ijece.v6i3.pp1205-1212.
Повний текст джерелаPrasad, M. V. Tejendra. "Development and Realization of a 4x4 Vedic Multiplier Utilizing Cadence Platform." Journal of VLSI Design and Signal Processing 9, no. 2 (August 4, 2023): 39–51. http://dx.doi.org/10.46610/jovdsp.2023.v09i02.004.
Повний текст джерелаManikrao, Kaustubh, and Mahesh Shrikant. "Analysis of Array Multiplier and Vedic Multiplier using Xilinx." Communications on Applied Electronics 5, no. 1 (May 24, 2016): 13–16. http://dx.doi.org/10.5120/cae2016652140.
Повний текст джерела