Статті в журналах з теми "VEDIC MULTIPLIER"
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Eshack, Ansiya, and S. Krishnakumar. "Pipelined vedic multiplier with manifold adder complexity levels." International Journal of Electrical and Computer Engineering (IJECE) 10, no. 3 (June 1, 2020): 2951. http://dx.doi.org/10.11591/ijece.v10i3.pp2951-2958.
Повний текст джерелаKhubnani, Rashi, Tarunika Sharma, and Chitirala Subramanyam. "Applications of Vedic multiplier - A Review." Journal of Physics: Conference Series 2225, no. 1 (March 1, 2022): 012003. http://dx.doi.org/10.1088/1742-6596/2225/1/012003.
Повний текст джерелаRashno, Meysam, Majid Haghparast, and Mohammad Mosleh. "A new design of a low-power reversible Vedic multiplier." International Journal of Quantum Information 18, no. 03 (April 2020): 2050002. http://dx.doi.org/10.1142/s0219749920500021.
Повний текст джерелаKuruvilla, Siya Susan, Stephani Sunil, Abisha Susan Alichan, and Abraham K. Thomas. "Comparison of Vedic Multiplier Implementation Using Gate Diffusion Input and Modified Gate Diffusion Input Techniques." Journal of Signal Processing 8, no. 2 (June 22, 2022): 1–5. http://dx.doi.org/10.46610/josp.2022.v08i02.001.
Повний текст джерелаGanjikunta, Ganesh Kumar, Sibghatullah I. Khan, and M. Mahaboob Basha. "A High-Performance Signed-Unsigned Multiplier Using Vedic Mathematics." Journal of Low Power Electronics 15, no. 3 (September 1, 2019): 302–8. http://dx.doi.org/10.1166/jolpe.2019.1616.
Повний текст джерелаSafoev, Nuriddin, and Jun-Cheol Jeon. "Design and Evaluation of Cell Interaction Based Vedic Multiplier Using Quantum-Dot Cellular Automata." Electronics 9, no. 6 (June 23, 2020): 1036. http://dx.doi.org/10.3390/electronics9061036.
Повний текст джерелаCVS, Chaitanya, Sundaresan C, P. R. Venkateswaran, Keerthana Prasad, and V. Siva Ramakrishna. "Design of High-Speed Multiplier Architecture Based on Vedic Mathematics." International Journal of Engineering & Technology 7, no. 2.4 (March 10, 2018): 105. http://dx.doi.org/10.14419/ijet.v7i2.4.11228.
Повний текст джерелаC, Pradeepa S., Gowri G. Bennur, Hruthika G, Adithya M, and Acharya Vinay Vasudeva. "Design and VLSI Implementation of Vedic Multiplier using 45nm Technology." International Journal for Research in Applied Science and Engineering Technology 11, no. 5 (May 31, 2023): 964–68. http://dx.doi.org/10.22214/ijraset.2023.51676.
Повний текст джерелаBhairannawar, Satish s., Raja K B, Venugopal K R, and L. M. Patnaik. "EFFICIENT FPGA BASED MATRIX MULTIPLICATION USING MUX AND VEDIC MULTIPLIER." INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY 12, no. 5 (January 30, 2014): 3452–63. http://dx.doi.org/10.24297/ijct.v12i5.2915.
Повний текст джерелаNandha Kumar, P. "Design of Accuracy Based Fixed-Width Booth Multipliers Using Data Scaling Technology." Asian Journal of Electrical Sciences 11, no. 2 (December 15, 2022): 24–30. http://dx.doi.org/10.51983/ajes-2022.11.2.3524.
Повний текст джерелаSaraswathi, N., Lokesh Modi, and Aatish Nair. "Complex Number Vedic Multiplier and its Implementation in a Filter." International Journal of Engineering & Technology 7, no. 2.24 (April 25, 2018): 336. http://dx.doi.org/10.14419/ijet.v7i2.24.12078.
Повний текст джерелаProf. Sharayu Waghmare. "Vedic Multiplier Implementation for High Speed Factorial Computation." International Journal of New Practices in Management and Engineering 1, no. 04 (December 31, 2012): 01–06. http://dx.doi.org/10.17762/ijnpme.v1i04.8.
Повний текст джерелаSM, Vijaya, and Suresh K. "An Efficient Design Approach of ROI Based DWT Using Vedic and Wallace Tree Multiplier on FPGA Platform." International Journal of Electrical and Computer Engineering (IJECE) 9, no. 4 (August 1, 2019): 2433. http://dx.doi.org/10.11591/ijece.v9i4.pp2433-2442.
Повний текст джерелаProf. Parvaneh Basaligheh. "Design and Implementation of High Speed Vedic Multiplier in SPARTAN 3 FPGA Device." International Journal of New Practices in Management and Engineering 6, no. 01 (March 31, 2017): 14–19. http://dx.doi.org/10.17762/ijnpme.v6i01.51.
Повний текст джерелаJhamb, Mansi, and Manoj Kumar. "Optimized vedic multiplier using low power 13T hybrid full adder." Journal of Information and Optimization Sciences 44, no. 4 (2023): 675–87. http://dx.doi.org/10.47974/jios-1222.
Повний текст джерелаCVS, Chaitanya, Sundaresan C, and P. R Venkateswaran. "ASIC design of low power-delay product carry pre-computation based multiplier." Indonesian Journal of Electrical Engineering and Computer Science 13, no. 2 (February 1, 2019): 845. http://dx.doi.org/10.11591/ijeecs.v13.i2.pp845-852.
Повний текст джерелаGowreesrinivas, K. V., Sabbavarapu Srinivas, and Punniakodi Samundiswary. "FPGA Implementation of a Resource Efficient Vedic Multiplier using SPST Adders." Engineering, Technology & Applied Science Research 13, no. 3 (June 2, 2023): 10698–702. http://dx.doi.org/10.48084/etasr.5797.
Повний текст джерелаParadhasaradhi, Damarla, Bharinala Haridhar, A. V. Sreekanth Reddy, Dudipalli Sri Charan, and Atyam Lekhaz. "Implementation of Fast Convolution using Robust Vedic Multiplier of Radix-2." International Journal of Engineering & Technology 7, no. 2.7 (March 18, 2018): 626. http://dx.doi.org/10.14419/ijet.v7i2.7.10895.
Повний текст джерелаSharma, Vaishali. "Design, Implementation & Performance of Vedic Multiplier Based on Look Ahead Carry Adder for Different Bit Lengths." International Journal for Research in Applied Science and Engineering Technology 10, no. 1 (January 31, 2022): 24–30. http://dx.doi.org/10.22214/ijraset.2022.39759.
Повний текст джерелаKunchigik, Vaijyanath, Linganagouda Kulkarni, and Subhash Kulkarni. "Pipelined Vedic-Array Multiplier Architecture." International Journal of Image, Graphics and Signal Processing 6, no. 6 (May 8, 2014): 58–64. http://dx.doi.org/10.5815/ijigsp.2014.06.08.
Повний текст джерелаKivi Sona, M., and V. Somasundaram. "Vedic Multiplier Implementation in VLSI." Materials Today: Proceedings 24 (2020): 2219–30. http://dx.doi.org/10.1016/j.matpr.2020.03.748.
Повний текст джерелаPrabhu, E., H. Mangalam, and P. R. Gokul. "A Delay Efficient Vedic Multiplier." Proceedings of the National Academy of Sciences, India Section A: Physical Sciences 89, no. 2 (February 9, 2018): 257–68. http://dx.doi.org/10.1007/s40010-017-0464-4.
Повний текст джерелаKumar, M. Siva, Sanath Kumar Tulasi, N. Srinivasulu, Vijaya Lakshmi Bandi, and K. Hari Kishore. "Bit wise and delay of vedic multiplier." International Journal of Engineering & Technology 7, no. 1.5 (December 31, 2017): 26. http://dx.doi.org/10.14419/ijet.v7i1.5.9117.
Повний текст джерелаManikrao, Kaustubh, and Mahesh Shrikant. "Analysis of Array Multiplier and Vedic Multiplier using Xilinx." Communications on Applied Electronics 5, no. 1 (May 24, 2016): 13–16. http://dx.doi.org/10.5120/cae2016652140.
Повний текст джерелаEshack, Ansiya, and S. Krishnakumar. "Reversible logic in pipelined low power vedic multiplier." Indonesian Journal of Electrical Engineering and Computer Science 16, no. 3 (December 1, 2019): 1265. http://dx.doi.org/10.11591/ijeecs.v16.i3.pp1265-1272.
Повний текст джерелаYadav, Jatin, Anupam Kumar, Shaik Shareef, Sandeep Bansal, and Navjot Rathour. "Comparative Analysis of Vedic Multiplier using Various Adder Architectures." Journal of Physics: Conference Series 2327, no. 1 (August 1, 2022): 012022. http://dx.doi.org/10.1088/1742-6596/2327/1/012022.
Повний текст джерелаBhavani, M., M. Siva Kumar, and K. Srinivas Rao. "Delay Comparison for 16x16 Vedic Multiplier Using RCA and CLA." International Journal of Electrical and Computer Engineering (IJECE) 6, no. 3 (June 1, 2016): 1205. http://dx.doi.org/10.11591/ijece.v6i3.9457.
Повний текст джерелаBhavani, M., M. Siva Kumar, and K. Srinivas Rao. "Delay Comparison for 16x16 Vedic Multiplier Using RCA and CLA." International Journal of Electrical and Computer Engineering (IJECE) 6, no. 3 (June 1, 2016): 1205. http://dx.doi.org/10.11591/ijece.v6i3.pp1205-1212.
Повний текст джерелаPrasad, M. V. Tejendra. "Development and Realization of a 4x4 Vedic Multiplier Utilizing Cadence Platform." Journal of VLSI Design and Signal Processing 9, no. 2 (August 4, 2023): 39–51. http://dx.doi.org/10.46610/jovdsp.2023.v09i02.004.
Повний текст джерела., Uttara Bhatt. "HIGH SPEED MULTIPLIER USING VEDIC MATHEMATICS." International Journal of Research in Engineering and Technology 03, no. 01 (January 25, 2014): 548–52. http://dx.doi.org/10.15623/ijret.2014.0301092.
Повний текст джерелаHari Kishore, K., Fazal Noorbasha, Katta Sandeep, D. N. V. Bhupesh, SK Khadar Imran, and K. Sowmya. "Linear convolution using UT Vedic multiplier." International Journal of Engineering & Technology 7, no. 2.8 (March 19, 2018): 409. http://dx.doi.org/10.14419/ijet.v7i2.8.10471.
Повний текст джерелаRamalakshmanna, Y., V. Yaswanth Varma, Phani Sai Kumar, and T. Nalini Prasad. "Modified Vedic Multiplier Using CSLA Adders." Journal of Computational and Theoretical Nanoscience 16, no. 4 (April 1, 2019): 1255–69. http://dx.doi.org/10.1166/jctn.2019.8028.
Повний текст джерелаSharma, Nitesh Kumar, Deepesh Kumar Gautam, and M. R. Khan. "Vedic Mathematics Implementation in Multiplier Units." Journal of Computer and Mathematical Sciences 10, no. 5 (May 30, 2019): 997–1003. http://dx.doi.org/10.29055/jcms/1083.
Повний текст джерелаNivasA, Sree, and Kayalvizhi N. "Implementation of Power Efficient Vedic Multiplier." International Journal of Computer Applications 43, no. 16 (April 30, 2012): 21–24. http://dx.doi.org/10.5120/6188-8673.
Повний текст джерелаVikas, Om, Deepak Gupta, Aneesh Bhasin, and Sonu Arora. "Vedic Multiplier with Fast Carry Optimization." IETE Journal of Research 51, no. 4 (July 2005): 327–31. http://dx.doi.org/10.1080/03772063.2005.11416411.
Повний текст джерелаAriafar, Zahra, and Mohammad Mosleh. "Effective Designs of Reversible Vedic Multiplier." International Journal of Theoretical Physics 58, no. 8 (May 24, 2019): 2556–74. http://dx.doi.org/10.1007/s10773-019-04145-0.
Повний текст джерелаEt. al., Srilakshmi Kaza,. "Performance Analysis of Adiabatic Vedic Multipliers." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, no. 5 (April 11, 2021): 1429–35. http://dx.doi.org/10.17762/turcomat.v12i5.2039.
Повний текст джерелаSharma, Sandesh, and Vangmayee Sharda. "Design and Analysis of 8-bit Vedic Multiplier in 90nm Technology using GDI Technique." International Journal of Engineering & Technology 7, no. 3.12 (July 20, 2018): 759. http://dx.doi.org/10.14419/ijet.v7i3.12.16496.
Повний текст джерелаKanda, Guard, and Kwangki Ryoo. "Vedic Multiplier-based International Data Encryption Algorithm Crypto-Core for Efficient Hardware Multiphase Encryption Design." Webology 19, no. 1 (January 20, 2022): 4581–96. http://dx.doi.org/10.14704/web/v19i1/web19304.
Повний текст джерелаDeokate, Rajesh. "A Review on IEEE-754 Standard Floating Point Multiplier using Vedic Mathematics." International Journal for Research in Applied Science and Engineering Technology 9, no. VI (June 20, 2021): 1300–1303. http://dx.doi.org/10.22214/ijraset.2021.35242.
Повний текст джерелаKunchigi, Vaijyanath, Linganagouda Kulkarni, and Subhash Kulkarni. "Simulation of Vedic Multiplier in DCT Applications." International Journal of Computer Applications 63, no. 16 (February 15, 2013): 27–32. http://dx.doi.org/10.5120/10552-5744.
Повний текст джерелаM C, Pradeep, and Dr Ramesh S. "Optimized high performance multiplier using Vedic mathematics." IOSR journal of VLSI and Signal Processing 4, no. 5 (2014): 06–11. http://dx.doi.org/10.9790/4200-04510611.
Повний текст джерелаNittala, Vijay Bhaskar, Anisha Bomma, and M. Ramana Reddy. "Energy Efficient Approximate 8-bit Vedic Multiplier." International Journal for Research in Applied Science and Engineering Technology 10, no. 9 (September 30, 2022): 1453–65. http://dx.doi.org/10.22214/ijraset.2022.46861.
Повний текст джерелаRashno, Meysam, Majid Haghparast, and Mohammad Mosleh. "Designing of Parity Preserving Reversible Vedic Multiplier." International Journal of Theoretical Physics 60, no. 8 (July 13, 2021): 3024–40. http://dx.doi.org/10.1007/s10773-021-04903-z.
Повний текст джерелаSuryavanshi, Ravindra, and Sweta Khare. "An Efficient High-Performance Vedic Multiplier: Review." INTERNATIONAL JOURNAL OF ADVANCED ENGINEERING AND MANAGEMENT 2, no. 3 (March 1, 2017): 60. http://dx.doi.org/10.24999/ijoaem/02030017.
Повний текст джерелаNarendra, K., and Sagara Pandu. "Low Power Area-Efficient Adiabatic Vedic Multiplier." International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering 03, no. 08 (August 20, 2014): 11027–32. http://dx.doi.org/10.15662/ijareeie.2014.0308018.
Повний текст джерелаSahu, Satya Ranjan, Bandan Kumar Bhoi, and Manoranjan Pradhan. "Fast signed multiplier using Vedic Nikhilam algorithm." IET Circuits, Devices & Systems 14, no. 8 (November 1, 2020): 1160–66. http://dx.doi.org/10.1049/iet-cds.2019.0537.
Повний текст джерелаVadiraj, G., K. Shivanand, B. Sampat, and G. Subramanya Nayak. "Implementation of High Speed Vedic Multiplier Using Vertical and Crosswise Algorithm." International Journal of Reconfigurable and Embedded Systems (IJRES) 6, no. 1 (May 28, 2018): 36. http://dx.doi.org/10.11591/ijres.v6.i1.pp36-40.
Повний текст джерелаKumar V G, Kiran, and Shantharama Rai C,. "Low Power High Speed Arithmetic Circuits." International Journal of Recent Technology and Engineering (IJRTE) 8, no. 2 (July 30, 2019): 807–13. http://dx.doi.org/10.35940/ijrte.a1064.078219.
Повний текст джерелаMOHANA KANNAN, LOGANATHAN, and DHANASKODI DEEPA. "LOW POWER VERY LARGE SCALE INTEGRATION (VLSI) DESIGN OF FINITE IMPULSE RESPONSE (FIR) FILTER FOR BIOMEDICAL IMAGING APPLICATION." DYNA 96, no. 5 (September 1, 2021): 505–11. http://dx.doi.org/10.6036/10214.
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