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Статті в журналах з теми "VEDIC MULTIPLIER"
Eshack, Ansiya, and S. Krishnakumar. "Pipelined vedic multiplier with manifold adder complexity levels." International Journal of Electrical and Computer Engineering (IJECE) 10, no. 3 (June 1, 2020): 2951. http://dx.doi.org/10.11591/ijece.v10i3.pp2951-2958.
Повний текст джерелаKhubnani, Rashi, Tarunika Sharma, and Chitirala Subramanyam. "Applications of Vedic multiplier - A Review." Journal of Physics: Conference Series 2225, no. 1 (March 1, 2022): 012003. http://dx.doi.org/10.1088/1742-6596/2225/1/012003.
Повний текст джерелаRashno, Meysam, Majid Haghparast, and Mohammad Mosleh. "A new design of a low-power reversible Vedic multiplier." International Journal of Quantum Information 18, no. 03 (April 2020): 2050002. http://dx.doi.org/10.1142/s0219749920500021.
Повний текст джерелаKuruvilla, Siya Susan, Stephani Sunil, Abisha Susan Alichan, and Abraham K. Thomas. "Comparison of Vedic Multiplier Implementation Using Gate Diffusion Input and Modified Gate Diffusion Input Techniques." Journal of Signal Processing 8, no. 2 (June 22, 2022): 1–5. http://dx.doi.org/10.46610/josp.2022.v08i02.001.
Повний текст джерелаGanjikunta, Ganesh Kumar, Sibghatullah I. Khan, and M. Mahaboob Basha. "A High-Performance Signed-Unsigned Multiplier Using Vedic Mathematics." Journal of Low Power Electronics 15, no. 3 (September 1, 2019): 302–8. http://dx.doi.org/10.1166/jolpe.2019.1616.
Повний текст джерелаSafoev, Nuriddin, and Jun-Cheol Jeon. "Design and Evaluation of Cell Interaction Based Vedic Multiplier Using Quantum-Dot Cellular Automata." Electronics 9, no. 6 (June 23, 2020): 1036. http://dx.doi.org/10.3390/electronics9061036.
Повний текст джерелаCVS, Chaitanya, Sundaresan C, P. R. Venkateswaran, Keerthana Prasad, and V. Siva Ramakrishna. "Design of High-Speed Multiplier Architecture Based on Vedic Mathematics." International Journal of Engineering & Technology 7, no. 2.4 (March 10, 2018): 105. http://dx.doi.org/10.14419/ijet.v7i2.4.11228.
Повний текст джерелаC, Pradeepa S., Gowri G. Bennur, Hruthika G, Adithya M, and Acharya Vinay Vasudeva. "Design and VLSI Implementation of Vedic Multiplier using 45nm Technology." International Journal for Research in Applied Science and Engineering Technology 11, no. 5 (May 31, 2023): 964–68. http://dx.doi.org/10.22214/ijraset.2023.51676.
Повний текст джерелаBhairannawar, Satish s., Raja K B, Venugopal K R, and L. M. Patnaik. "EFFICIENT FPGA BASED MATRIX MULTIPLICATION USING MUX AND VEDIC MULTIPLIER." INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY 12, no. 5 (January 30, 2014): 3452–63. http://dx.doi.org/10.24297/ijct.v12i5.2915.
Повний текст джерелаNandha Kumar, P. "Design of Accuracy Based Fixed-Width Booth Multipliers Using Data Scaling Technology." Asian Journal of Electrical Sciences 11, no. 2 (December 15, 2022): 24–30. http://dx.doi.org/10.51983/ajes-2022.11.2.3524.
Повний текст джерелаДисертації з теми "VEDIC MULTIPLIER"
ANTONY, SAJI M. "DESIGN OF ENERGY EFFICIENT TRANSCEIVER BLOCKS FOR WIRELESS SENSOR NODES." Thesis, DELHI TECHNOLOGICAL UNIVERSITY, 2020. http://dspace.dtu.ac.in:8080/jspui/handle/repository/18771.
Повний текст джерелаZanchi, Chiara. "Multiple preverbs in ancient Indo-European languages: a comparative study on Vedic, Homeric Greek, Old Church Slavic and Old Irish." Doctoral thesis, Università degli studi di Bergamo, 2018. http://hdl.handle.net/10446/104992.
Повний текст джерелаZANCHI, CHIARA. "Multiple preverbs in ancient Indo-European languages: a comparative study on Vedic, Homeric Greek, Old Church Slavic and Old Irish." Doctoral thesis, Università degli studi di Pavia, 2018. https://hdl.handle.net/11571/1466705.
Повний текст джерелаJiang, CunHao, and 蔣存皓. "An Efficient Vedic Multiplier Design." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/65n6nm.
Повний текст джерела國立臺北科技大學
電子工程系研究所
105
Multiplier is one of core operations of the digital signal processing and microprocessor. the multiplier in the digital circuit needs to increase the speed, decrease the area and consume less memory. So an efficient multiplier is very important in nowadays. This paper is about designing traditional Vedic multiplier through the Urdhva-Tiryagbhyam sutra. Changing the adder from the traditional Vedic multiplier which designed with the sutra, it can become two kinds of efficient Vedic multipliers. After designing 4-bit, 8-bit, 16-bit, 32-bit traditional Vedic multiplier and two kinds of efficient Vedic multipliers, their time delay and areas are analyzed through the Quartus II. According to the results of the experiment, time delay of the original efficient Vedic multiplier decreases 5.88% but the area increases 37.298%. Besides, time delay of the resolved efficient Vedic multiplier decreases 7.4% but the area increases 21.6%. If the multiplier needs to be faster on work afterwards, 4-bit and 16-bit original efficient Vedic multiplier and 8-bit, 32-bit and 64-bit resolved efficient Vedic multiplier are suggested. If the multiplier needs to be smaller, traditional Vedic multiplier is suggested. If both delay time and chip area cost are considered comprehensively, 8-bit or 64-bit resolved efficient Vedic multiplier are suggested.
RUHELA, DIKSHA. "DESIGN AND IMPLEMENTATION OF EFFICIENT REVERSIBLE MULTIPLIER USING VEDIC MATHEMATICS TOOL." Thesis, 2016. http://dspace.dtu.ac.in:8080/jspui/handle/repository/14759.
Повний текст джерелаKUMAR, SHIVAM. "DESIGN AND IMPLEMENTATION OF EFFICIENT MATRIX MULTIPLICATION USING VARIOUS ARCHITECTURE." Thesis, 2023. http://dspace.dtu.ac.in:8080/jspui/handle/repository/19896.
Повний текст джерелаКниги з теми "VEDIC MULTIPLIER"
Design of a High Speed Multiplier (Ancient Vedic Mathematics Approach) . Innovative Research Publications, 2013.
Знайти повний текст джерелаGeslani, Marko. Rites of the God-King. Oxford University Press, 2018. http://dx.doi.org/10.1093/oso/9780190862886.001.0001.
Повний текст джерелаЧастини книг з теми "VEDIC MULTIPLIER"
Sudhamsu Preetham, J. V. R., Perli Nethra, D. Chandrasekhar, Mathangi Akhila, N. Arun Vignesh, and Asisa Kumar Panigrahy. "Vedic Multiplier for High-Speed Applications." In Communication, Software and Networks, 349–56. Singapore: Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-19-4990-6_31.
Повний текст джерелаPavan Kumar, N., and K. Shashi Raj. "Delay Analysis of Hybrid Vedic Multiplier." In Advances in Intelligent Systems and Computing, 91–103. Singapore: Springer Singapore, 2022. http://dx.doi.org/10.1007/978-981-16-7330-6_8.
Повний текст джерелаUdaya Kumar, N., K. Bala Sindhuri, U. Subbalakshmi, and P. Kiranmayi. "Performance Evaluation of Vedic Multiplier Using Multiplexer-Based Adders." In Lecture Notes in Electrical Engineering, 349–56. Singapore: Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-13-1906-8_36.
Повний текст джерелаLachireddy, Dhanunjay, and S. R. Ramesh. "Power and Delay Efficient ALU Using Vedic Multiplier." In Lecture Notes in Electrical Engineering, 703–11. Singapore: Springer Singapore, 2020. http://dx.doi.org/10.1007/978-981-15-5558-9_61.
Повний текст джерелаKumari, Sabita, and Kanchan Sharma. "Implementation of Nobel Vedic Multiplier Using Arithmetic Adder." In Data Intelligence and Cognitive Informatics, 209–16. Singapore: Springer Singapore, 2022. http://dx.doi.org/10.1007/978-981-16-6460-1_15.
Повний текст джерелаAwade, Anirudh, Prachi Jain, S. Hemavathy, and V. S. Kanchana Bhaaskaran. "Design of Vedic Multiplier Using Reversible Logic Gates." In Lecture Notes in Electrical Engineering, 435–48. Singapore: Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-15-9019-1_38.
Повний текст джерелаSrimani, Supriyo, Diptendu Kumar Kundu, Saradindu Panda, and B. Maji. "Implementation of High Performance Vedic Multiplier and Design of DSP Operations Using Vedic Sutra." In Computational Advancement in Communication Circuits and Systems, 443–49. New Delhi: Springer India, 2015. http://dx.doi.org/10.1007/978-81-322-2274-3_49.
Повний текст джерелаThakare, Laxman P., A. Y. Deshmukh, and Gopichand D. Khandale. "VHDL Implementation of Complex Number Multiplier Using Vedic Mathematics." In Proceedings of International Conference on Soft Computing Techniques and Engineering Application, 403–10. New Delhi: Springer India, 2013. http://dx.doi.org/10.1007/978-81-322-1695-7_46.
Повний текст джерелаKhan, Angshuman, and Rupayan Das. "Novel Approach of Multiplier Design Using Ancient Vedic Mathematics." In Advances in Intelligent Systems and Computing, 265–72. New Delhi: Springer India, 2015. http://dx.doi.org/10.1007/978-81-322-2247-7_28.
Повний текст джерелаGiridaran, S., Prithvik Adithya Ravindran, G. Duruvan Raj, and M. Janarthanan. "Design of Low Power Vedic Multiplier Using Adiabatic Techniques." In Cognitive Informatics and Soft Computing, 403–15. Singapore: Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-16-8763-1_33.
Повний текст джерелаТези доповідей конференцій з теми "VEDIC MULTIPLIER"
Kahar, Dravik KishorBhai, and Harsh Mehta. "High speed vedic multiplier used vedic mathematics." In 2017 International Conference on Intelligent Computing and Control Systems (ICICCS). IEEE, 2017. http://dx.doi.org/10.1109/iccons.2017.8250742.
Повний текст джерелаG, Shanthi K., Sandhiya G, Abinaya K, Akula Sangeetha, Aruna T, and Aswini R. "Performance Analysis of Vedic Multiplier and Modified Vedic Multiplier in Direct Digital Synthesizer." In 2022 3rd International Conference on Electronics and Sustainable Communication Systems (ICESC). IEEE, 2022. http://dx.doi.org/10.1109/icesc54411.2022.9885340.
Повний текст джерелаN., Noorja, and Sujithamol S. "Convolution Using Modified Vedic Multiplier." In Proceedings of the Advances in Technology, Engineering and Computing A Multinational Colloquium - 2017. Singapore: Research Publishing Services, 2017. http://dx.doi.org/10.3850/978-981-11-0744-3_c66.
Повний текст джерелаKodali, Ravi Kishore, C. Sivakumar, Vishal Jain, and Lakshmi Boppana. "Low-power modified Vedic multiplier." In 2015 International Conference on Control Communication & Computing India (ICCC). IEEE, 2015. http://dx.doi.org/10.1109/iccc.2015.7432939.
Повний текст джерелаPranav, K., and P. Pramod. "Pipelined convolution using Vedic multiplier." In 2015 IEEE Recent Advances in Intelligent Computational Systems (RAICS). IEEE, 2015. http://dx.doi.org/10.1109/raics.2015.7488384.
Повний текст джерелаRam, G. Challa, Y. Rama Lakshmanna, D. Sudha Rani, and K. Bala Sindhuri. "Area efficient modified vedic multiplier." In 2016 International Conference on Circuit, Power and Computing Technologies (ICCPCT). IEEE, 2016. http://dx.doi.org/10.1109/iccpct.2016.7530294.
Повний текст джерелаPatel, Chiranjit R., Vivek Urankar, Vivek B. A, and V. Keshav Bharadwaj. "Vedic Multiplier in 45nm Technology." In 2020 Fourth International Conference on Computing Methodologies and Communication (ICCMC). IEEE, 2020. http://dx.doi.org/10.1109/iccmc48092.2020.iccmc-0004.
Повний текст джерелаHarish Babu N, Satish Reddy N, Bhumarapu Devendra, and Jayakrishanan P. "Pipelined architecture for vedic multiplier." In 2014 International Conference on Advances in Electrical Engineering (ICAEE). IEEE, 2014. http://dx.doi.org/10.1109/icaee.2014.6838437.
Повний текст джерелаPichhode, Khushboo, Mukesh D. Patil, Divya Shah, and B. Chaurasiya Rohit. "FPGA implementation of efficient vedic multiplier." In 2015 International Conference on Information Processing (ICIP). IEEE, 2015. http://dx.doi.org/10.1109/infop.2015.7489448.
Повний текст джерелаBansal, Malti, and Jasmeet Singh. "Comparative Analysis of 4-bit CMOS Vedic Multiplier and GDI Vedic Multiplier using 18nm FinFET Technology." In 2020 International Conference on Smart Electronics and Communication (ICOSEC). IEEE, 2020. http://dx.doi.org/10.1109/icosec49089.2020.9215317.
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