Дисертації з теми "Ultra Low Power CMOS RF"
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Kraimia, Hassen. "Ultra-Low Power RFIC Solutions for Wireless Sensor Networks." Phd thesis, Université Sciences et Technologies - Bordeaux I, 2013. http://tel.archives-ouvertes.fr/tel-01066815.
Lin, Kuan-Yu. "The design of low power ultra-wideband RF CMOS wireless systems for sensor networks." Thesis, McGill University, 2008. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=22014.
Le marché sans fil continu à développer vers une bande passante plus large, une réduction de la consommation d'énergie électrique et du coût. La technologie ultra large bande (UWB) est prometteuse dans le domaine de la communication des capteurs des réseaux sans fil. Toutefois, il faut noter que l'architecture et les conceptions de circuit du système de communication sans fil d'UWB peuvent être très différentes des systèmes à bande étroite traditionnels. Cette thèse traite de la conception UWB radio fréquence (RF) des émetteurs récepteurs d'entrée et du système de récupération et de gestion d'énergie pour les capteurs des réseaux sans fil à faible consommation d'énergie électrique. Un CMOS amplificateur à faible bruit (AFB), à large bande et à faible consommation d'énergie électrique est démontré. Pour obtenir une bonne amplification, l'impédance d'entrée du circuit désirée et minimiser la consommation d'énergie électricité, l'AFB propose l'exploitation des transformateurs RF, de la réutilisation du courant électrique, et des techniques de couplage pour amplifier la transconductance des transistors. Pour réaliser une conception compacte à coût réduit sans l'utilisation des composants externe, l'AFB utilise des transformateurs spéciaux composés de fil de liaison de haute qualité sur un paquet d'un circuit intégré. Le prototype AFB fabriqué dans une technologie CMOS de 0.18 µm consomme 698.5 µW avec une tension de 1.5 V. La conception de deux émetteurs CMOS d'impulsion à large bande et à faible consommation d'énergie électrique est décrite. Le but est de proposer une solution simple pour réduire la consommation d'énergie électricité et des topologies réglables des émetteurs à plein-bande et à sous-bande pour la technologie UWB. Le premier émetteur utilise un oscillateur, un commutateur NMOS, et un filtre passif pour produire un signal UWB de 3.1-10.6 GHz à plein-bande. Le deuxième émetteur mu
Gebreyohannes, Fikre Tsigabu. "Design of Ultra-Low Power Wake-Up Receiver in 130nm CMOS Technology." Thesis, Linköpings universitet, Elektroniksystem, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-78797.
This is a master's thesis work by a communication electronics student in a German company called IMST GmbH.
Chandernagor, Lucie. "Etude, conception et réalisation d’un récepteur d’activation RF ultra basse consommation pour l’internet des objets." Thesis, Limoges, 2016. http://www.theses.fr/2016LIMO0126/document.
Wireless technologies are now widespread due to the easiness of use they provide. Consequently, the number of radio devices increases. Despite of the efforts to reduce radio circuits power consumption as they are more and more numerous, now they must achieve ultra-low power consumption. Today, radio devices are made more efficient to reduce their power consumption especially for the receiving part. Indeed, for asynchronous communication, a lot of energy is wasted by the receiver waiting for a transmission. In order to avoid this waste, new standards have been created such as Zigbee and Bluetooth Low Energy. Due to periodic operation with ultra-low duty cycle, they provide ultra-low power consumption. Another solution to drastically reduce the power consumption has emerged, wake-up receiver. Wake-up receivers are based in simple architecture to provide ultra-low power consumption, they are only in charge to wait for a frame and when it occurs, wake-up the main receiver put in standby mode before that. The proposed wake-up receiver has been designed in NXP CMOS technology 160 μm. It provides a-54 dBm sensitivity, consuming 35 μA which allows a 70m range considering a 10 dBm emitter at 433,92 MHz. This wake-up receiver operates with ASK modulation, compared to others it provides a smart patented calibration system to get the necessary reference voltage for demodulation. This mechanism provide DC offset robustness and does not drain any current while the wake-up receiver is operating. To wake up the main receiver a 24 bits programmable Manchester code is required. This code at 25 kbps is programmable by the use of an SPI interface
Guigue, Sébastien. "Développement, intégration et prototypage d'un noeud-capteur autonome à récupération d’énergie pour réseaux de capteurs sans fil." Electronic Thesis or Diss., Bordeaux, 2024. http://www.theses.fr/2024BORD0082.
There has been an upsurge in the number of connected devices in the IoT(Internetof Things) context. The multiplication of Wireless Sensor Networks (WSNs) lead toan increase of the number of batteries and of waste generated. In a context of green electronics, the development of self-sustained circuits supplied with energy harvesting has to be managed.Chapter I will give an overview of wireless sensor networks, including a brief history these systems, the different fields of application, the challenges and some possible solutions to overcome these issues.Chapter II will present the design of a custom Microcontroller Unit (MCU) which runs the WSN with a minimum power consumption. The architecture of the microcontroller,the instruction set, the interfacing and all the design choices will be presented.Chapter III describes the design of a Wake-Up Radio (WuRx), an always-on circuit which switches on the WSN when a request is sent. The choice for the architecture of each block Will be explained, while detailing the different aspects of each block.The blocks areas follows : An envelope detector for data reception ;A comparator for data demodulation ; An oscillator to provide a clock for the system ; A correlator to compare the received message with a reference,; A current source to provide temperature robustness.Chapter IV provides an analysis of the entire wireless sensor node. An estimation of the node autonomy is presented and a comparison with a node designed with market components is presented. Perspectives of improvement for future works will also be presented
Kraemer, Michael M. "Design of a low-power 60 GHz transceiver front-end and behavioral modeling and implementation of its key building blocks in 65 nm CMOS." Thesis, Toulouse, INSA, 2010. http://www.theses.fr/2010ISAT0027/document.
Worldwide regulations for short range communication devices allow the unlicensed use of several Gigahertz of bandwidth in the frequency band around 60GHz. This 60GHz band is ideally suited for applications like very high data rate, energy-autonomous wireless sensor networks or Gbit/s multimedia links with low power constraints. Not long ago, radio interfaces that operate in the millimeter-wave frequency range could only be realized using expensive compound semiconductor technologies. Today, the latest sub-micron CMOS technologies can be used to design 60GHz radio frequency integrated circuits (RFICs)at very low cost in mass production. This thesis is part of an effort to realize a low power System in Package (SiP) including both the radio interface (with baseband and RF circuitry) and an antenna array to directly transmit and receive a 60GHz signal. The first part of this thesis deals with the design of the low power RF transceiver front-end for the radio interface. The key building blocks of this RF front-end (amplifiers, mixers and a voltage controlled oscillator (VCO)) are designed, realized and measured using the 65nm CMOS technology of ST Microelectronics. Full custom active and passive devices are developed for the use within these building blocks. An important step towards the full integration of the RF transceiver front-end is the assembly of these building blocks to form basic transmitter and receiver chips. Circuits with small chip size and low power consumption compared to the state of the art have been accomplished.The second part of this thesis concerns the development of behavioral models for the designed building blocks. These system level models are necessary to simulate the behavior of the entire SiP, which becomes too complex when using detailed circuit level models. In particular, a novel technique to model the transient, steady state and phase noise behavior of the VCO in the hardware description language VHDL-AMS is proposed and implemented. The model uses a state space description to describe the dynamic behavior of the VCO. Its nonlinearity is approximated by artificial neural networks. A drastic reduction of simulation time with respect to the circuit level model has been achieved, while at the same time maintaining a very high level of accuracy
Coulot, Thomas. "Stratégie d'alimentation pour les SoCs RF très faible consommation." Phd thesis, Université de Grenoble, 2013. http://tel.archives-ouvertes.fr/tel-00951423.
Kraemer, Michael. "Design of a low-power 60 GHz transceiver front-end and behavioral modeling and implementation of its key building blocks in 65 nm CMOS." Phd thesis, INSA de Toulouse, 2010. http://tel.archives-ouvertes.fr/tel-00554674.
Inanlou, Farzad Michael-David. "Innovative transceiver approaches for low-power near-field and far-field applications." Diss., Georgia Institute of Technology, 2014. http://hdl.handle.net/1853/52245.
Sirigiri, Vijay Krishna. "Ultra-Low Power Ultra-Fast Hybrid CNEMS-CMOS FPGAs." Case Western Reserve University School of Graduate Studies / OhioLINK, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=case1291259866.
Verma, Naveen. "Ultra-low-power SRAM design in high variability advanced CMOS." Thesis, Massachusetts Institute of Technology, 2009. http://hdl.handle.net/1721.1/53305.
Cataloged from PDF version of thesis.
Includes bibliographical references (p. 163-181).
Embedded SRAMs are a critical component in modern digital systems, and their role is preferentially increasing. As a result, SRAMs strongly impact the overall power, performance, and area, and, in order to manage these severely constrained trade-offs, they must be specially designed for target applications. Highly energy-constrained systems (e.g. implantable biomedical devices, multimedia handsets, etc.) are an important class of applications driving ultra-low-power SRAMs. This thesis analyzes the energy of an SRAM sub-array. Since supply- and threshold-voltage have a strong effect, targets for these are established in order to optimize energy. Despite the heavy emphasis on leakage-energy, analysis of a high-density 256x256 sub-array in 45nm LP CMOS points to two necessary optimizations: (1) aggressive supply-voltage reduction (in addition to Vt elevation), and (2) performance enhancement. Important SRAM metrics, including read/write/hold-margin and read-current, are also investigated to identify trade-offs of these optimizations. Based on the need to lower supply-voltage, a 0.35V 256kb SRAM is demonstrated in 65nm LP CMOS. It uses an 8T bit-cell with peripheral circuit-assists to improve write-margin and bit-line leakage. Additionally, redundancy, to manage the increasing impact of variability in the periphery, is proposed to improve the area-offset trade-off of sense-amplifiers, demonstrating promise for highly advanced technology nodes. Based on the need to improve performance, which is limited by density constraints, a 64kb SRAM, using an offset-compensating sense-amplifier, is demonstrated in 45nm LP CMOS with high-density 0.25[mu]m2 bit-cells.
(cont.) The sense-amplifier is regenerative, but non -strobed, overcoming timing uncertainties limiting performance, and it is single-ended, for compatibility with 8T cells. Compared to a conventional strobed sense-amplifier, it achieves 34% improvement in worst-case access-time and 4x improvement in the standard deviation of the access-time.
by Naveen Verma.
Ph.D.
Bargagli-Stoffi, Agnese [Verfasser]. "Ultra low-voltage, low-power amplifiers in deep submicrometer CMOS / Agnese Bargagli-Stoffi." Aachen : Shaker, 2006. http://d-nb.info/116651336X/34.
Sadat, Md Anwar. "LOW POWER CMOS CIRCUIT DESIGN AND RELIABILITY ANALYSIS FOR WIRELESS ME." Doctoral diss., University of Central Florida, 2004. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/3390.
Ph.D.
Department of Electrical and Computer Engineering
Engineering and Computer Science
Electrical Engineering
Tsui, Hau Yiu. "A 5 GHz integrated low-power CMOS RF front-end IC design /." View abstract or full-text, 2004. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202004%20TSUI.
Ordóñez, Hurtado Andrés Fernando. "Design methodology of a modular CMOS ultra-low power self-biased current source." reponame:Repositório Institucional da UFSC, 2017. https://repositorio.ufsc.br/xmlui/handle/123456789/178587.
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Neste documento é desenvolvida uma metodologia de projeto de uma fonte de corrente auto polarizada de ultra baixo consumo de potência em tecnologia CMOS. É descrita uma topologia modular implementada com dois MOSFETs auto cascodados (SCMs) e um amplificador operacional. A metodologia proposta está baseada no conceito de ni´veis de inversão e o espaço de projeto do circuito é descrito principalmente em termos das especificações do amplificador operacional e do espelho de corrente PMOS. O circuito foi projetado usando uma tecnologia padrão CMOS de 130 nm. Os resultados das simulações são apresentados neste documento para validar a metodologia de projeto e o desempenho da fonte de corrente, mostrando que o circuito proposto pode operar com uma tensão de alimentação menor de 1 V e com menos de 1%/V na regulação de linha.
Abstract : In this document a design procedure of a CMOS ultra-low-power self-biased current source is developed. A modular topology using two self-cascode MOSFETs (SCMs), a current mirror and an operational amplifier is implemented. The described methodology is based on the concept of inversion level, and the design space of the current source is described mainly in terms of the specifications of the operational amplifier and the PMOS current mirror. The circuit was designed in a 130 nm standard CMOS technology. Simulation results are provided to validate the design methodology and the performance of the current source, showing that the proposed circuit can operate at a supply voltage less than 1 V with less than 1%/V of line regulation.
Dornelas, Helga Uchoa. "Low power SAR analog-to-digital converter for internet-of-things RF receivers." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2018. http://hdl.handle.net/10183/186015.
Caicedo, Jhon Alexander Gomez. "CMOS low-power threshold voltage monitors circuits and applications." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2016. http://hdl.handle.net/10183/144080.
A threshold voltage (VT0) monitor is a circuit that ideally delivers the estimated VT0 value as a voltage at its output, for a given temperature range, without external biases, parametric setups, curve fitting or any subsequent calculation. It can be used in temperature sensors, voltage and current references, radiation dosimeters and other applications since the MOSFET VT0 dependence on the operation conditions is a very well modeled aspect. Also, it can be used for fabrication process monitoring and process variability compensation, since VT0 is a key parameter for the transistor behavior and modeling. In this thesis, we present three novel circuit topologies, two of them being NMOS VT0 monitors and the last one being a PMOS VT0 monitor. The three structures are resistorless self-biased circuit topologies that present high power supply rejection, low line sensitivity, and allow the direct extraction of the threshold voltage for wide temperature and power supply voltage ranges, with small error. Its design methodology is based on the Unified Current Control Model (UICM), a MOSFET model that is continuous from weak to strong inversion and from triode to saturation regions. The circuits occupy small silicon area, consume just tens of nanoWatts, and can be implemented in any standard digital CMOS process, since they only use MOS transistors (does not need any resistor). The VT0 monitors are used in different applications in order to prove their functionality, and behavior as part of a system. The applications vary from a reference voltage, that presents performance comparable with state-of-the-art works, to a configuration that allows to obtain a lower process variability, in the output of a self-biased circuit that generates a complementary to the absolute temperature (CTAT) voltage. In addition, exploiting the ability to operate as an specific current (ISQ) generator, that the VT0 monitors presented here offer, we introduced a new self-biased circuit that produces a CTAT voltage and is less sensitive to process variations, and can be used in band-gap voltage references.
Marsden, Kevin Matthew. "A Study of a Versatile Low Power CMOS Pulse Generator for Ultra Wideband Radios." Thesis, Virginia Tech, 2003. http://hdl.handle.net/10919/9754.
Master of Science
Muppalla, Ashwin K. "Ultra low power multi-gigabit digital CMOS modem technology for millimeter wave wireless systems." Thesis, Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/41084.
Paidimarri, Arun. "Architecture for ultra-low power multi-channel transmitters for Body Area Networks using RF resonators." Thesis, Massachusetts Institute of Technology, 2011. http://hdl.handle.net/1721.1/66473.
Cataloged from PDF version of thesis.
Includes bibliographical references (p. 99-103).
Body Area Networks (BANs) are gaining prominence for their use in medical and sports monitoring. This thesis develops the specifications of a ultra-low power 2.4GHz transmitter for use in a Body Area Networks, taking advantage of the asymmetric energy constraints on the sensor node and the basestation. The specifications include low transmit output powers, around -10dBm, low startup time, simple modulation schemes of OOK, FSK and BPSK and high datarates of 1Mbps. An architecture that is suited for the unique requirements of transmitters in these BANs is developed. RF Resonators, and in particular Film Bulk Acoustic Wave Resonators (FBARs) are explored as carrier frequency generators since they provide stable frequencies without the need for PLLs. The frequency of oscillation is directly modulated to generate FSK. Since these oscillators have low tuning range, the architecture uses multiple resonators to define the center frequencies of the multiple channels. A scalable scheme that uses a resonant buffer is developed to multiplex the oscillators' outputs to the Power Amplifier (PA). The buffer is also capable of generating BPSK signals. Finally a PA optimized for efficiently delivering the low output powers required in BANs is developed. A tunable matching network in the PA also enables pulse-shaping for spectrally efficient modulation. A prototype transmitter supporting 3 FBAR-oscillator channels in the 2.4GHz ISM band was designed in a 65nm CMOS process. It operates from a 0.7V supply for the RF portion and 1V for the digital section. The transmitter achieves 1Mbps FSK, up to 10Mbps for OOK and BPSK without pulse shaping and 1Mbps for OOK and BPSK with pulse shaping. The power amplifier has an efficiency of up to 43% and outputs between -15dBm and -7.5dBm onto a 50Q antenna. Overall, the transmitter achieves an efficiency of upto 26% and energy per bit of 483pJ/bit at 1Mbps.
by Arun Paidimarri.
S.M.
Rafeei, Lalleh. "Fast Approximation Framework for Timing and Power Analysis of Ultra-Low-Voltage Circuits." Thesis, Virginia Tech, 2012. http://hdl.handle.net/10919/31678.
Master of Science
Johansson, Mattias, and Jonas Ehrs. "Low-Power Low-Noise IQ Modulator Designs in 90nm CMOS for GSM/EDGE/WCDMA/LTE." Thesis, Linköping University, Department of Electrical Engineering, 2010. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-54552.
The current consumption of the IQ modulator is a significant part of the totalcurrent consumption of a mobile transmitter platform and reducing it is of greatinterest. Also, as the WCDMA/LTE standards specifies full duplex transmissionsand Tx and Rx are most often using the same antenna, it is crucial to have asolution with low noise generation. Two new proposals have been studied with theaim to reduce the current consumption and noise contribution of the IQ modulator.
A current mode envelope tracking IQM is the first of the studied designs. Thisimplementation lowers the bias currents in the circuit in relation to the amplitudeof the baseband input signals, meaning that a low input amplitude results in alowering of the current consumption. It proves to be very efficient for basebandsignals with a high peak-to-average ratio. Simulations and calculations have shownthat an average current reduction of 56 % can be achieved for an arbitrary LTEbaseband signal.
The second is an entirely new passive mixer design where the baseband voltagesare sequentially copied to the RF node, removing the need for V-to-I conversion inthe mixer which reduces current consumption and noise. Results from simulationshas proven that this design is fully capable of improving both current consumptionas well as the noise levels. With an output power of 4.0 dBm, the power consumptionwas 43.3 mW, including clock generating circuits. This, combined with thefact that the design is small and simple, means that there is definitely a possibilityto replace the present IQM design with a passive mixer.
Roy, Sajib, and Md Murad Kabir Nipun. "Understanding Sub-threshold source coupled logic for ultra-low power application." Thesis, Linköpings universitet, Elektroniksystem, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-69404.
Zhang, Dai. "Design and Evaluation of an Ultra-Low Power Successive Approximation ADC." Thesis, Linköping University, Department of Electrical Engineering, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-18219.
Analog-to-digital converters (ADC) targeted for use in medical implant devices serve an important role as the interface between analog signal and digital processing system. Usually, low power consumption is required for a long battery lifetime. In such application which requires low power consumption and moderate speed and resolution, one of the most prevalently used ADC architectures is the successive approximation register (SAR) ADC.This thesis presents a design of an ultra-low power 9-bit SAR ADC in 0.13μm CMOS technology. Based on a literature review of SAR ADC design, the proposed SAR ADC combines a capacitive DAC with S/H circuit, uses a binary-weighted capacitor array for the DAC and utilizes a dynamic latch comparator. Evaluation results show that at a supply voltage of 1.2V and an output rate of 1kS/s, the SAR ADC performs a total power consumption of 103nW and a signal-to-noise-and-distortion ratio of 54.4dB. Proper performance is achieved down to a supply voltage of 0.45V, with a power consumption of 16nW.
Værnes, Magne. "Trade-offs between Performance and Robustness for Ultra Low Power/Low Energy Subthreshold D flip-flops in 65nm CMOS." Thesis, Norges teknisk-naturvitenskapelige universitet, Institutt for elektronikk og telekommunikasjon, 2013. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-22704.
Liendo, sanchez Andreina. "Study of adaptation mechanisms of the wireless sensor nodes to the context for ultra-low power consumption." Thesis, Université Grenoble Alpes (ComUE), 2018. http://www.theses.fr/2018GREAT095/document.
The Internet of Things (IoT) is announced as the next big technological revolution where billions of devices will interconnect using Internet technologies and let users interact with the physical world, allowing Smart Home, Smart Cities, smart everything. Wireless Sensor Network (WSN) are crucial for turning the vision of IoT into a reality, but for this to come true, many of these devices need to be autonomous in energy. Hence, one major challenge is to provide multi-year lifetime while powered on batteries or using harvested energy. Bluetooth Low Energy (BLE) has shown higher energy efficiency and robustness than other well known WSN protocols, making it a strong candidate for implementation in IoT scenarios. Additionally, BLE is present in almost every smartphone, turning it into perfect ubiquitous remote control for smart homes, buildings or cities. Nevertheless, BLE performance improvement for typical IoT use cases, where battery lifetime should reach many years, is still necessary.In this work we evaluated BLE performance in terms of latency and energy consumption based on analytical models in order to optimize its performance and obtain its maximum level of energy efficiency without modification of the specification in a first place. For this purpose, we proposed a scenarios classification as well as modes of operation for each scenario. Energy efficiency is achieved for each mode of operation by optimizing the parameters that are assigned to the BLE nodes during the neighbor discovery phase. This optimization of the parameters was made based on an energy model extracted from the state of the art. The model, in turn, has been optimized to obtain latency and energy consumption regardless of the behavior of the nodes at different levels: application and communication. Since a node can be the central device at one level, while it can be the peripheral device at the other level at the same time, which affects the final performance of the nodes.In addition, a novel battery lifetime estimation model was presented to show the actual impact that energy consumption optimization have on nodes lifetime in a fast (in terms of simulation time) and realistic way (by taking into account empirical data). Performance results were obtained in our Matlab based simulator based on OOP paradigm, through the use of several IoT test cases. In addition, the latency model used for our investigation was experimentally validated as well as the proposed parameter optimization, showing a high accuracy.After obtaining the best performance possible of BLE without modification of the specification, we evaluated the protocol performance when implementing the concept of Wake-Up radio, which is an ultra low power receiver in charge on sensing the communication channel, waiting for a signal addressed to the node and then wake the main radio up. Thus, the main radio which consumes higher energy, can remain in sleep mode for long periods of time and switch to an active mode only for packet reception, therefore saving considerable amount of energy. We demonstrated that BLE lifetime can be significantly increased by implementing a Wake-Up radio and we propose a modification of the protocol in order to render this protocol compatible with an operating mode which includes a Wake-Up radio. For this, we studied the Wake-Up radio state of the art and evaluated BLE devices lifetime when a selected Wake-Up radio is implemented at the master side
Vauché, Rémy. "Conception de générateurs d'impulsions ultra-large bande en technologie CMOS." Thesis, Aix-Marseille 1, 2011. http://www.theses.fr/2011AIX10098.
The information theory developed by Claude Shannon (1916 - 2001) highlights the fact that in order to increase the capacity of a transmission channel, it is preferable to extend the bandwidth used rather than the transmission power. This finding is the starting point of many papers on Ultra-Wideband (UWB) which led to the creation in the United States of UWB band since 2002 where no modulation is privileged. Two years later, many works on Impulsionnal Radio UWB (IR-UWB) communications began at IM2NP including the design of low noise amplifier, power detector, but also pulse generators which is the key element of IR-UWB emitters. These form basis of works presented in the manuscript that took place from 2008 to 2011. The discontinuous nature of communications impulse was first implied the introduction of new figures of merit for measuring performances of pulse generators. Then it deals with design techniques for sizing structures operating at frequencies involved, but also to reduce consumption and especially static leakage to reduce enough power consumption for embedded systems. Finally three architectures of pulse generators are developed, each one responding to different constraints in terms of frequency, consumption and range
Safari, Naeim. "Design of a DC/DC buck converter for ultra-low power applications in 65nm CMOS Process." Thesis, Linköpings universitet, Elektroniska komponenter, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-80395.
Hiremath, Vinayashree. "DESIGN OF ULTRA HIGH SPEED FLASH ADC, LOW POWER FOLDING AND INTERPOLATING ADC IN CMOS 90nm TECHNOLOGY." Wright State University / OhioLINK, 2010. http://rave.ohiolink.edu/etdc/view?acc_num=wright1291391500.
Sen, Shreyas. "Design of process and environment adaptive ultra-low power wireless circuits and systems." Diss., Georgia Institute of Technology, 2011. http://hdl.handle.net/1853/45755.
Camponeschi, Matteo. "Analysis and design of CMOS and bipolar SiGe:C integrated circuits for low power RF receivers and radar applications." Doctoral thesis, Università degli studi di Padova, 2010. http://hdl.handle.net/11577/3427529.
Questa tesi di dottorato propone l'analisi e la progettazione di due circuiti integrati a radio-frequenza. Nella prima parte del lavoro viene sviluppato il front-end di un ricevitore wireless a basso consumo di potenza per Wireless Sensor Networks. Il circuito, che comprende un amplificatore a basso rumore, oscillatori locali e mixer, costituisce un sistema di ricezione completo implementato in un singolo stadio per ridurre il consumo di potenza. L'architettura proposta, basata sulla tecnica del riutilizzo della corrente di polarizzazione, viene motivata e descritta in dettaglio; segue un'accurata analisi tempo-variante dell'architettura per l'ottimizzazione del circuito proposto; il ricevitore a 2.4GHz è stato infine realizzato con una tecnologia CMOS digitale a 90nm con top metal ottimizzato per la realizzazione di induttori integrati con alto fattore di qualità. Le misure effettute sui campioni confermano la correttezza della nostra analisi e la validità dell'architettura proposta. Nella seconda parte di questa tesi di dottorato viene sviluppato un upconverter per un Frequency-Modulated Continuous-Wave radar in banda X. L'obiettivo del progetto è quello di realizzare un upconverter a banda larga, con uno spettro in uscita libero da toni spuri e con minimo phase noise. L'architettura proposta comprende due mixer con relative interfacce in banda base, un amplificatore a radiofrequenza e tutta la circuiteria per la generazione dei segnali in quadratura per pilotare i mixer a partire da un oscillatore locale esterno di riferimento. Vengono analizzati vari meccanismi di generazione di toni spuri all'uscita, con particolare enfasi sui problemi legati alla reiezione dell'immagine, ai mismatches ed alle nonlinearità generate nell'interfaccia in banda base. Due versioni del modulatore sono state progettate e confrontate: a) una versione realizzata in una tecnologia CMOS a 65nm digitale basata su un mixer passivo a corrente di polarizzazione nulla per minimizzare la generazione di rumore flicker e b) una versione realizzata in una tecnologia bipolare SiGe:C a 0.35μm basata su un mixer di Gilbert attivo
El, Ghouli Salim. "UTBB FDSOI mosfet dynamic behavior study and modeling for ultra-low power RF and mm-Wave IC Design." Thesis, Strasbourg, 2018. http://www.theses.fr/2018STRAD015/document.
This research work has been motivated primarily by the significant advantages brought about by the UTBB FDSOI technology to the Low power Analog and RF applications. The main goal is to study the dynamic behavior of the UTBB FDSOI MOSFET in light of the recent technology advances and to propose predictive models and useful recommendations for RF IC design with particular emphasis on Moderate Inversion regime. After a brief review of progress in MOSFET architectures introduced in the semiconductor industry, a state-of-the-art UTBB FDSOI MOSFET modeling status is compiled. The main physical effects involved in the double gate transistor with a 7 nm thick film are reviewed, particularly the back gate impact, using measurements and TCAD. For better insight into the Weak Inversion and Moderate Inversion operations, both the low frequency gm/ID FoM and the proposed high frequency ym/ID FoM are studied and also used in an efficient first-cut analog design. Finally, a high frequency NQS model is developed and compared to DC and S-parameters measurements. The results show excellent agreement across all modes of operation including very low bias conditions and up to 110 GHz
Papotto, Giuseppe. "Batteryless RF transceiver for wireless sensor networks." Doctoral thesis, Università di Catania, 2012. http://hdl.handle.net/10761/1082.
Ben, Amor Inès. "Gestion dynamique de la consommation de récepteurs RF : intégration de fronts-end RF ultra faible consommation." Thesis, Aix-Marseille, 2016. http://www.theses.fr/2016AIXM4323.
The emergence of the Internet of Things (IoT), sensors networks and new networks to objects requires the development of a new ecosystem. Nowadays, it upsets many sectors of our society. It solicits design of low power radio transceivers as reducing energy consumption presents a major constraint in the case of these applications in order to obtain greater autonomy. In this context, the purpose of the thesis is to provide techniques allowing reducing the power consumption of radio frequency receivers while seeking to minimize the impact of these technologies on the performance of the achieved receiver. In order to realize a demonstrator consists of a transmitter and receiver for video transmission, two UWB receivers with dynamic power management have been made in 0.13µm HCMOS9 technology from STMicroelectronics. First, a study of dynamic power management techniques on analog radio frequency circuits was proposed. This study was conducted on different circuits that seem to be the most used in design of analog circuits at high frequencies. The proposed technique allows to turn on and off the circuit between two pulses received to reduce their consumption. The application of this technique also requires a reduction of the latency caused by the ignition and the extinction radio frequency functions. In this case, a model to minimize the impact of the encapsulating effect has been proposed. Secondly, the first receiver was performed for 6-10GHz frequency band and implements dynamic power management using the technique of "Power Gating"
Iwaki, Takao. "Ultra-low power single crystal silicon SOI-CMOS micro-hotplate with novel temperature-modulation principle for chemical sensing." Thesis, University of Warwick, 2007. http://wrap.warwick.ac.uk/89582/.
Szilàgyi, Làszlò, Guido Belfiore, Ronny Henker, and Frank Ellinger. "20–25 Gbit/s low-power inductor-less single-chip optical receiver and transmitter frontend in 28 nm digital CMOS." Cambridge University Press, 2017. https://tud.qucosa.de/id/qucosa%3A70657.
Hu, Xin. "RF CMOS Tunable Gilbert Mixer with Wide Tuning Frequency and Controllable Bandwidth: Design Sythesis and Verification." Wright State University / OhioLINK, 2017. http://rave.ohiolink.edu/etdc/view?acc_num=wright149572725296626.
Mattia, Neto Oscar Elisio. "NanoWatt resistorless CMOS voltage references for Sub-1 V applications." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2014. http://hdl.handle.net/10183/107131.
Integrated voltage references have always been a fundamental block of any electronic system, and an important research topic that has been extensively studied in the past 50 years. A voltage reference is a circuit that provides a stable voltage with low sensitivity to variations in temperature, supply, load, process characteristics and packaging stresses. They are usually implemented through the weighted sum of two independent physical phenomena with opposite temperature dependencies. Usually the thermal voltage, related to the Boltzmann’s constant and the electron charge, provides a positive temperature dependence, while the silicon bandgap voltage or a MOSFET’s threshold voltage provide the complementary term. An auxiliary biasing block is sometimes necessary to provide the necessary currents for the circuit to work, and additional blocks implement the weighted sum. The scaling of process technologies is the main driving factor for low voltage operation, while the emergence of portable battery-operated, implantable biomedical and energy harvesting devices mandate that every circuit consume as little power as possible. Therefore, sub-1 V supplies and nanoWatt power have become key characteristics for these kind of circuits, but there are several challenges when designing high accuracy voltage references in modern CMOS technologies under these conditions. The traditional topologies are not suitable because they provide a reference voltage above 1 V, and to achieve such power consumption levels would require G resistances, that occupy a huge silicon area. Recent advances have achieved these levels of power consumption but with limited accuracy, expensive calibration procedures and large silicon area.
yasami, saeed. "Design and Evaluation of an Ultra-Low PowerLow Noise Amplifier LNA." Thesis, Linköping University, Department of Electrical Engineering, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-50923.
This master thesis deals with the study of ultra low power Low Noise Amplifier (LNA) for use inmedical implant device. Usually, low power consumption is required for a long battery lifetime andlonger operation. The target technology is 90nm CMOS process.First basic principle of LNA is discussed. Then based on a literature review of LNA design, theproposed LNA is presented in sub-threshold region which reduce power consumption through scalingthe supply voltage and through scaling current.The circuit implementation and simulations is presented to testify the performance of LNA .Besides thepower consumption simulated under the typical supply voltage (1V), it is also measured under someother low supply voltages (down to 0.5V) to investigate the minimum power consumption and theminimum noise figure. Evaluation results show that at a supply voltage of 1V the LNA performs a totalpower consumption of 20mW and a noise of 1dB. Proper performance is achieved with a current ofdown to 200uA and supply voltage of down to 0.45V, and a total power consumption of 200uW
Alena, Đugova. "Nova konfiguracija širokopojasnog nisko-šumnog pojačavača u CMOS tehnologiji." Phd thesis, Univerzitet u Novom Sadu, Fakultet tehničkih nauka u Novom Sadu, 2016. https://www.cris.uns.ac.rs/record.jsf?recordId=100329&source=NDLTD&language=en.
In the transceiver chain the low noise amplifier (LNA) is placed in the frontendof the receiver after the antenna. The LNA needs to isolate and amplifyreceived weak signal at a specific frequency above the noise level of thereceiver. In the scope of this doctoral dissertation methods for designingultra-wideband (UWB) LNA in CMOS technology are presented anddescribed. Nine new LNA configurations were proposed. Based on theobtained results, simple LNA configuration, obtained by merging casodefeedback topology and current-reuse technique, was realized and fabricatedin 0.18 μm UMC CMOS technology. The LNA is designed for the frequencyband from 3.1 to 5 GHz. In addition, the method for measurement LNAparameters is described and the proposed LNA was characterized.
Ben, Amor Inès. "Gestion dynamique de la consommation de récepteurs RF : intégration de fronts-end RF ultra faible consommation." Electronic Thesis or Diss., Aix-Marseille, 2016. http://www.theses.fr/2016AIXM4323.
The emergence of the Internet of Things (IoT), sensors networks and new networks to objects requires the development of a new ecosystem. Nowadays, it upsets many sectors of our society. It solicits design of low power radio transceivers as reducing energy consumption presents a major constraint in the case of these applications in order to obtain greater autonomy. In this context, the purpose of the thesis is to provide techniques allowing reducing the power consumption of radio frequency receivers while seeking to minimize the impact of these technologies on the performance of the achieved receiver. In order to realize a demonstrator consists of a transmitter and receiver for video transmission, two UWB receivers with dynamic power management have been made in 0.13µm HCMOS9 technology from STMicroelectronics. First, a study of dynamic power management techniques on analog radio frequency circuits was proposed. This study was conducted on different circuits that seem to be the most used in design of analog circuits at high frequencies. The proposed technique allows to turn on and off the circuit between two pulses received to reduce their consumption. The application of this technique also requires a reduction of the latency caused by the ignition and the extinction radio frequency functions. In this case, a model to minimize the impact of the encapsulating effect has been proposed. Secondly, the first receiver was performed for 6-10GHz frequency band and implements dynamic power management using the technique of "Power Gating"
Hedayati, Raheleh. "A Study of Successive Approximation Registers and Implementation of an Ultra-Low Power 10-bit SAR ADC in 65nm CMOS Technology." Thesis, Linköpings universitet, Elektroniska komponenter, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-72767.
Ippolito, Calogero. "A CMOS Frequency Synthesizer for Wireless Sensor Network transceivers." Doctoral thesis, Università di Catania, 2012. http://hdl.handle.net/10761/1080.
Brandano, Davide. "Design of Frequency divider with voltage vontrolled oscillator for 60 GHz low power phase-locked loops in 65 nm RF CMOS." Doctoral thesis, Universitat Politècnica de Catalunya, 2012. http://hdl.handle.net/10803/81303.
Lee, Hyung-Jin. "Digital CMOS Design for Ultra Wideband Communication Systems: from Circuit-Level Low Noise Amplifier Implementation to a System-Level Architecture." Diss., Virginia Tech, 2006. http://hdl.handle.net/10919/26195.
Ph. D.
Liu, Yidong. "CMOS RF cituits sic] variability and reliability resilient design, modeling, and simulation." Doctoral diss., University of Central Florida, 2011. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/4969.
ID: 029809399; System requirements: World Wide Web browser and PDF reader.; Mode of access: World Wide Web.; Thesis (Ph.D.)--University of Central Florida, 2011.; Includes bibliographical references (p. 90-105).
Ph.D.
Doctorate
Electrical Engineering and Computer Science
Engineering and Computer Science
Khan, Abbas. "Optimization through Co-Simulation of Antenna, Bandpass Filter and Low-Noise Amplifier at 6-9 GHz." Thesis, Linköpings universitet, Fysik och elektroteknik, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-110575.
Zhang, Tao [Verfasser], Georg [Akademischer Betreuer] Böck, and Stefan [Akademischer Betreuer] Heinen. "Low power CMOS RF-transceiver circuits for K-band wireless localization systems / Tao Zhang. Gutachter: Georg Böck ; Stefan Heinen. Betreuer: Georg Böck." Berlin : Technische Universität Berlin, 2014. http://d-nb.info/1067387412/34.
Liu, Jing. "Développement de cellules élémentaires radiofréquences faible consommation en technologie FDSOI pour des applications liées à l'internet des objets." Thesis, Université Grenoble Alpes (ComUE), 2019. http://www.theses.fr/2019GREAT057.
Wireless applications are almost by definition battery powered devices. Power consumption is therefore a major concern for the LNA design. There are always compromises to satisfy the low noise factor, reasonable gain, high linearity, low power and low cost.The objective of this work is to design a low noise amplifier LNA in 28 nm FDSOI technology provided by STMicroelectronics by implementing the design method of gm/ID and the RFPG (RF power gating) technique. The main part of this design is to achieve LNAs with very low power consumption without degrading performance.At first, the LNA design is based on the gm/ID methodology and the characteristics of the 28nm FDSOI technology. For such technologies, recent works show that good trade-offs between performances and consumption can be obtained in moderate or weak inversion region. In this work we present a complete method to size capacitive feedback LNAs. This topology is chosen for its compactness since only one inductor is used (in the input matching network). The presented design flow allows reaching some given performances (Noise Figure NF and voltage gain Glna) with the minimum power consumption while having a design constraint on the value of the inductor to better control the cost of the LNA. This low-power LNA conception is based on a gm/ID approach which is suitable for RF design in advanced technologies such as FDSOI. This method allows the sizing of all the components to reach a given NF and voltage gain while maximizing the gm/ID to minimize the power consumption. In addition, even if the linearity is not considered as a design constraint, this method leads to good IIP3 performances because it tends to reduce the input quality factor which causes high non-linearity. Moreover, this proposed method makes it possible to have a low input inductance value for adaptation. This inductance can also be replaced by bonding.In a second step, a LNA with the RFPG technique is presented. Based on a first LNA, a RFPG LNA is designated in very low consumption by turning on and off the LNA quickly. The principle of RFPG consists on power gating RF blocs such as LNA or Mixer during the symbol time. This approach is based on the observation that, in the case of a good propagation channel, it is not necessary to collect all the energy of the symbol. With this technique, it is possible to adapt the performance of the receiver to the quality of the channel and thus to adapt the power consumption.With the gm/ID method, the RFPG technique on advanced FDSOI technology, LNA consumption can be greatly reduced in keeping good performance.Mots-clés: Low noise amplifier; capacitive feedback; low power; gm/ID; RFPG (RF power gating); 28nm FDSOI
Funke, Dominic A. [Verfasser], Jürgen [Gutachter] Oehm, and Nils [Gutachter] Pohl. "Ultra-Low-Power Schaltungen für Mikrosysteme in CMOS-Technologie / Dominic A. Funke ; Gutachter: Jürgen Oehm, Nils Pohl ; Fakultät für Elektrotechnik und Informationstechnik." Bochum : Ruhr-Universität Bochum, 2019. http://d-nb.info/1199613959/34.