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Готові списки джерел за темами / Ultra Low Power CMOS RF

Добірка наукової літератури з теми "Ultra Low Power CMOS RF"

Автор: Grafiati

Опубліковано: 7 липня 2024

Оновлено: 7 липня 2024

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Статті в журналах з теми "Ultra Low Power CMOS RF":

1

Jin, Jie, Xianming Wu, and Zhijun Li. "Ultra low power mixer with out-of-band RF energy harvesting for wireless sensor networks applications." Engineering review 40, no. 1 (January 27, 2020): 1–6. http://dx.doi.org/10.30765/er.40.1.01.

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An ultra low power mixer with out-of-band radio frequency (RF) energy harvesting suitable for the wireless sensors network (WSN) application is proposed in this paper. The presented mixer is able to harvest the out-of-band RF energy and keep it working in ultra low power condition and extend the battery life of the WSN. The mixer is designed and simulated with Global Foundries ’ 0.18 μ m CMOS RF process, and it operates at 2.4GHz industrial, scientific, and medical (ISM) band. The Cadence IC Design Tools post-layout simulation results demonstrate that the proposed mixer consumes 248 μ W from a 1V supply voltage. Furthermore, the power consumption can be reduced to 120.8 μ W by the out-of-band RF energy harvesting rectifier.

2

La Rosa, Roberto, Danilo Demarchi, Sandro Carrara, and Catherine Dehollain. "High-Efficiency Reconfigurable CMOS RF-to-DC Converter System for Ultra-Low-Power Wireless Sensor Nodes with Efficient MPPT Circuitry." Chips 3, no. 1 (March 12, 2024): 49–68. http://dx.doi.org/10.3390/chips3010003.

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This paper presents a novel CMOS RF-to-DC converter for ultra-low-power wireless sensor nodes powered by RF wireless power transfer. The proposed converter achieves 10% higher power conversion efficiency than a conventional rectifier, with only a 1% increase in power consumption. The system employs a reconfigurable Dickson topology, operates on the unlicensed 868 MHz ISM band, and includes a built-in power-efficient MPPT system architecture. Experimental measurements show a maximum power conversion efficiency of 55% in the power range from −22 dBm to 0 dBm, with a power sensitivity of −22 dBm for a DC output voltage of 2.4 V. The proposed converter offers a promising solution for efficient wireless power transfer and energy harvesting in ultra-low-power wireless sensor nodes.

3

Tan, Gim Heng, Roslina Mohd Sidek, Harikrishnan Ramiah, Wei Keat Chong, and De Xing Lioe. "Ultra-Low-Voltage CMOS-Based Current Bleeding Mixer with High LO-RF Isolation." Scientific World Journal 2014 (2014): 1–5. http://dx.doi.org/10.1155/2014/163414.

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This journal presents an ultra-low-voltage current bleeding mixer with high LO-RF port-to-port isolation, implemented on 0.13 μm standard CMOS technology for ZigBee application. The architecture compliments a modified current bleeding topology, consisting of NMOS-based current bleeding transistor, PMOS-based switching stage, and integrated inductors achieving low-voltage operation and high LO-RF isolation. The mixer exhibits a conversion gain of 7.5 dB at the radio frequency (RF) of 2.4 GHz, an input third-order intercept point (IIP3) of 1 dBm, and a LO-RF isolation measured to 60 dB. The DC power consumption is 572 µW at supply voltage of 0.45 V, while consuming a chip area of 0.97 × 0.88 mm2.

4

Haddad, Fayrouz, Wenceslas Rahajandraibe, and Imen Ghorbel. "RF CMOS Oscillators Design for autonomous Connected Objects." E3S Web of Conferences 88 (2019): 05001. http://dx.doi.org/10.1051/e3sconf/20198805001.

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Voltage controlled oscillator (VCO) is an integral part of IoT wireless transceiver components. In this paper, VCOs operating around 2.4 GHz have been designed in CMOS technology. The relation between their components and specifications is studied for their performance optimization. Ultra-low power, less than 270 µW, has been obtained, while performing a frequency tuning range of about 10% between 2.1 and 2.4 GHz. Investigations on phase noise performance have been also achieved.

5

Taris, Thierry, Jennifer Desevedavy, Frederic Hameau, Patrick Audebert, and Dominique Morche. "Inductorless Multi-Mode RF-CMOS Low Noise Amplifier Dedicated to Ultra Low Power Applications." IEEE Access 9 (2021): 83431–40. http://dx.doi.org/10.1109/access.2021.3085990.

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6

Fenni, S. ,., F. Haddad, A. ,. Slimane, R. ,. Touhami, and W. Rahajandraibe. "Design of Monolithic RF CMOS Sub-mW Self-Oscillating-Mixers." WSEAS TRANSACTIONS ON CIRCUITS AND SYSTEMS 22 (April 21, 2023): 23–27. http://dx.doi.org/10.37394/23201.2023.22.4.

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In this paper, different topologies of RF self-oscillating mixers (SOM), stacking the voltage controlled oscillator (VCO) and the mixer on top of each other, are assessed. Their design considerations to address sub-mW operation suitable to ultra-low power applications are presented. Two configurations of SOM circuits are implemented in 130nm CMOS technology. The obtained results are presented and performances in terms of gain, noise, linearity, area, power consumption and stability over process and mismatch are compared and discussed.

7

Huang, Shuigen, Min Lin, Zongkun Zhou, and Xiaoyun Li. "An ultra-low-power 2.4 GHz RF receiver in CMOS 55 nm process." IEICE Electronics Express 15, no. 5 (2018): 20180016. http://dx.doi.org/10.1587/elex.15.20180016.

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8

Murad, S. A. Z., Muhammad M. Ramli, A. Azizan, M. N. M. Yasin, and I. S. Ishak. "Ultra-Low Power CMOS RF Mixer for Wireless Sensor Networks Application: A Review." MATEC Web of Conferences 97 (2017): 01037. http://dx.doi.org/10.1051/matecconf/20179701037.

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9

Jayamon, Ashik C., Ankur Mukherjee, Sai Chandra Teja R., and Ashudeb Dutta. "High-efficiency CMOS charge pump for ultra-low power RF energy harvesting applications." Integration 96 (May 2024): 102161. http://dx.doi.org/10.1016/j.vlsi.2024.102161.

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10

Akhter, Muhammad Ovais, and Najam Muhammad Amin. "Design and Optimization of 2.1 mW ULP Doherty Power Amplifier with Interstage Capacitances Using 65 nm CMOS Technology." Mathematical Problems in Engineering 2021 (November 19, 2021): 1–12. http://dx.doi.org/10.1155/2021/3364016.

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This research proposed the design and calculations of ultra-low power (ULP) Doherty power amplifier (PA) using 65 nm CMOS technology. Both the main and the peaking amplifiers are designed and optimized using equivalent lumped parameters and power combiner models. The operation has been performed in RF-nMOS subthreshold or triode region to achieve ultra-low power (ULP) and to improve the linearity of the overall power amplifier (PA). The novel design consumes a DC power of 2.1 mW, power-added efficiency (PAE) of 29.8%, operating at 2.4 GHz band, and output referred 1 dB compression point at 4.1dBm. The simulation results show a very good capability of drive current, high gain, and very low input and output insertion losses.

Більше джерел

Дисертації з теми "Ultra Low Power CMOS RF":

1

Kraimia, Hassen. "Ultra-Low Power RFIC Solutions for Wireless Sensor Networks." Phd thesis, Université Sciences et Technologies - Bordeaux I, 2013. http://tel.archives-ouvertes.fr/tel-01066815.

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Since their emergence, Wireless Sensor Networks (WSN) have been growing continually becoming a key player in many applications such as military tracking, remote monitoring, bio-sensing and home automation. These networks are based on IEEE 802.15.4 standard which is dedicated to low rate wireless personal area networks (LR-WPANs) in the unlicensed radio band (868MHz/915MHz/2.4GHz). Low power consumption, low cost of implementation and high level of integration are the main challenges of these systems. As radio frequency transceiver is one of the most power hungry block in wireless sensor node, power consumption of radio frequency front-end (RFFE) must be reduced. To deal with, several approaches are possible, either at circuit level by investigating operating modes of transistors and merging functionalities or at system level by searching novel demodulation architecture. This thesis explores the specific requirements and challenges for the design of ultra-low power radio frequency integrated circuits (RFICs), leading to the design of a compact demodulator implemented in 65 nm CMOS technology and compatible with all modulation schemes.

2

Lin, Kuan-Yu. "The design of low power ultra-wideband RF CMOS wireless systems for sensor networks." Thesis, McGill University, 2008. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=22014.

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The wireless market is continuing its rapid development towards higher bandwidth, lower power, and lower cost. Recently, wireless sensor networks (WSN) have emerged and captivated the interest of many researchers and the industry. A promising wireless communication technology for wireless sensor networks is the ultra-wideband (UWB) technology. The architecture and circuit designs of UWB wireless communication systems can be very different from traditional narrowband systems. This thesis focuses on the design of UWB radio frequency (RF) front-end transceivers, power scavenging and power management systems for low power wireless sensor networks. A sub-miliWatt ultra-wideband CMOS common gate (CG) low-noise amplifier (LNA) is demonstrated in this work. To achieve good gain, wideband input impedance matching, and low power consumption, the proposed LNA exploits the combination of RF transformers, current reuse, and back-gate coupling techniques to boost the transconductance of the gain transistors. To realize a compact low cost design with no discrete components, the LNA utilizes special high quality bonding wire transformers on an IC package. The LNA prototype, fabricated in a 0.18 µm CMOS process, consumes 698.5 µW from a 1.5 V supply. The design of two low power CMOS ultra-wideband (UWB) pulse-based transmitters is also reported in this thesis. The goal is to propose simple, low power, and tunable topologies for full-band and sub-band UWB transmitters. The first transmitter utilizes a gated ring oscillator, an NMOS switch, and a passive pulse shaping filter to generate a 3.1 - 10.6 GHz full-band UWB signal. The second transmitter multiplies a carrier and a triangular signal to up-convert and to generate a low side-band UWB signal for sub-band applications. We propose the use of two NMOS switches in series to perform this multiplication while consuming minimum power. Control voltages incorporated in both designs are used to adjust the shapes of the pulses to comp
Le marché sans fil continu à développer vers une bande passante plus large, une réduction de la consommation d'énergie électrique et du coût. La technologie ultra large bande (UWB) est prometteuse dans le domaine de la communication des capteurs des réseaux sans fil. Toutefois, il faut noter que l'architecture et les conceptions de circuit du système de communication sans fil d'UWB peuvent être très différentes des systèmes à bande étroite traditionnels. Cette thèse traite de la conception UWB radio fréquence (RF) des émetteurs récepteurs d'entrée et du système de récupération et de gestion d'énergie pour les capteurs des réseaux sans fil à faible consommation d'énergie électrique. Un CMOS amplificateur à faible bruit (AFB), à large bande et à faible consommation d'énergie électrique est démontré. Pour obtenir une bonne amplification, l'impédance d'entrée du circuit désirée et minimiser la consommation d'énergie électricité, l'AFB propose l'exploitation des transformateurs RF, de la réutilisation du courant électrique, et des techniques de couplage pour amplifier la transconductance des transistors. Pour réaliser une conception compacte à coût réduit sans l'utilisation des composants externe, l'AFB utilise des transformateurs spéciaux composés de fil de liaison de haute qualité sur un paquet d'un circuit intégré. Le prototype AFB fabriqué dans une technologie CMOS de 0.18 µm consomme 698.5 µW avec une tension de 1.5 V. La conception de deux émetteurs CMOS d'impulsion à large bande et à faible consommation d'énergie électrique est décrite. Le but est de proposer une solution simple pour réduire la consommation d'énergie électricité et des topologies réglables des émetteurs à plein-bande et à sous-bande pour la technologie UWB. Le premier émetteur utilise un oscillateur, un commutateur NMOS, et un filtre passif pour produire un signal UWB de 3.1-10.6 GHz à plein-bande. Le deuxième émetteur mu

3

Gebreyohannes, Fikre Tsigabu. "Design of Ultra-Low Power Wake-Up Receiver in 130nm CMOS Technology." Thesis, Linköpings universitet, Elektroniksystem, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-78797.

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Wireless Sensor Networks have found diverse applications from health to agriculture and industry. They have a potential to profound social changes, however, there are also some challenges that have to be addressed. One of the problems is the limited power source available to energize a sensor node. Longevity of a node is tied to its low power design. One of the areas where great power savings could be made is in nodal communication. Different schemes have been proposed targeting low power communication and short network latency. One of them is the introduction of ultra-low power wake-up receiver for monitoring the channel. Although it is a recent proposal, there has been many works published. In this thesis work, the focus is study and comparison of architectures for a wake-up receiver. As part of this study, an envelope detector based wake-up receiver is designed in 130nm CMOS Technology. It has been implemented in schematic and layout levels. It operates in the 2.4GHz ISM band and consumes a power consumption of 69µA at 1.2V supply voltage. A sensitivity of -52dBm is simulated while receiving 100kb/s OOK modulated wake-up signals.
This is a master's thesis work by a communication electronics student in a German company called IMST GmbH.

4

Chandernagor, Lucie. "Etude, conception et réalisation d’un récepteur d’activation RF ultra basse consommation pour l’internet des objets." Thesis, Limoges, 2016. http://www.theses.fr/2016LIMO0126/document.

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Grâce au confort d’utilisation qu’elles procurent, les technologies sans fil se retrouvent aujourd’hui dans un vaste panel d’applications. Ainsi le nombre d’éléments de transmission/réception radio se multiplie. Aujourd’hui pour réduire les consommations des éléments radio, il faut les rendre davantage efficaces notamment pour la partie réception. En effet, pour les communications asynchrones, les récepteurs consomment inutilement de l’énergie à attendre qu’une transmission soit faite. Dans l’objectif de réduire ce gaspillage d’énergie, des nouveaux standards ont vu le jour tel que le Zigbee et le Bluetooth Low Energy. Les performances en consommation procurées par ces deux standards résident sur leur fonction périodique à très faible rapport cyclique. Une nouvelle solution émergente pour réduire drastiquement la consommation des récepteurs en les rendant plus efficaces est l’utilisation de récepteur d’activation. Les récepteurs d’activation ou récepteur de réveil sont des récepteurs simples ce qui leur permet d’atteindre une ultra basse consommation uniquement en charge de guetter l’arrivée d’une trame et de réveiller le récepteur principal, placé en veille au préalable, pour traitement de cette dernière. Le récepteur d’activation proposé ici a été réalisé dans la technologie CMOS 160 nm de NXP. Il offre une sensibilité de -54 dBm, pour une consommation moyenne de 35 μA, prodiguant une portée de 70m à 433,92 MHz pour une puissance de 10 dBm émis. Ce récepteur ASK se distingue des autres récepteurs d’activation par le système de calibration breveté avec ajustement automatique la tension de référence requise pour la démodulation. Ce système rend le circuit robuste au problème d’offset DC et ne consomme aucun courant lorsque le circuit est en écoute. Le récepteur d’activation reconnaît un code de Manchester de 24 bits à 25 kbps, programmable grâce à une interface SPI
Wireless technologies are now widespread due to the easiness of use they provide. Consequently, the number of radio devices increases. Despite of the efforts to reduce radio circuits power consumption as they are more and more numerous, now they must achieve ultra-low power consumption. Today, radio devices are made more efficient to reduce their power consumption especially for the receiving part. Indeed, for asynchronous communication, a lot of energy is wasted by the receiver waiting for a transmission. In order to avoid this waste, new standards have been created such as Zigbee and Bluetooth Low Energy. Due to periodic operation with ultra-low duty cycle, they provide ultra-low power consumption. Another solution to drastically reduce the power consumption has emerged, wake-up receiver. Wake-up receivers are based in simple architecture to provide ultra-low power consumption, they are only in charge to wait for a frame and when it occurs, wake-up the main receiver put in standby mode before that. The proposed wake-up receiver has been designed in NXP CMOS technology 160 μm. It provides a-54 dBm sensitivity, consuming 35 μA which allows a 70m range considering a 10 dBm emitter at 433,92 MHz. This wake-up receiver operates with ASK modulation, compared to others it provides a smart patented calibration system to get the necessary reference voltage for demodulation. This mechanism provide DC offset robustness and does not drain any current while the wake-up receiver is operating. To wake up the main receiver a 24 bits programmable Manchester code is required. This code at 25 kbps is programmable by the use of an SPI interface

5

Guigue, Sébastien. "Développement, intégration et prototypage d'un noeud-capteur autonome à récupération d’énergie pour réseaux de capteurs sans fil." Electronic Thesis or Diss., Bordeaux, 2024. http://www.theses.fr/2024BORD0082.

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Il y a eu une recrudescence du nombre de dispositifs connectés dans le contexte de l’Internet des objets. La multiplication des réseaux de capteurs sans fil a conduit à une augmentation du nombre de batteries et de déchets générés. Dans un contexte d’électronique verte, le développement de circuits autonomes alimentés par la récupération d’énergie doit être géré. Le premier chapitre donnera un aperçu des réseaux de capteurs sans fil, y compris une brève histoire de ces systèmes, les différents domaines d’application, les défis et quelques solutions possibles pour surmonter ces problèmes. Le second chapitre présentera la conception d’un microcontrôleur sur mesure pour l’application qui contrôle le noeud capteur avec une consommation minimale d’énergie. L’architecture du microcontrôleur, le jeu d’instructions, l’interfaçage et tous les choix de conception seront présentés. Le troisième chapitre décrit la conception d’une radio de réveil, un circuit toujours actif qui active le noeud capteur lorsqu’une requête est envoyée. Le choix de l’architecture de chaque bloc sera expliqué, en détaillant les différents aspects de chaque bloc. Les blocs sont les suivants : Un détecteur d’enveloppe pour la réception des données ; Un comparateur pour la démodulation des données ; Un oscillateur pour fournir une horloge pour le système, ; Un corrélateur pour comparer le message reçu avec une référence ; Une source de courant pour assurer la robustesse thermique.Le dernier chapitre fournit une analyse de l’ensemble du noeud de capteur sans fil. Une estimation de l’autonomie du noeud est présentée et une comparaison avec un noeud conçu avec des composants du marché est également présentée. Des perspectives d’amélioration pour les travaux futurs seront également exposées
There has been an upsurge in the number of connected devices in the IoT(Internetof Things) context. The multiplication of Wireless Sensor Networks (WSNs) lead toan increase of the number of batteries and of waste generated. In a context of green electronics, the development of self-sustained circuits supplied with energy harvesting has to be managed.Chapter I will give an overview of wireless sensor networks, including a brief history these systems, the different fields of application, the challenges and some possible solutions to overcome these issues.Chapter II will present the design of a custom Microcontroller Unit (MCU) which runs the WSN with a minimum power consumption. The architecture of the microcontroller,the instruction set, the interfacing and all the design choices will be presented.Chapter III describes the design of a Wake-Up Radio (WuRx), an always-on circuit which switches on the WSN when a request is sent. The choice for the architecture of each block Will be explained, while detailing the different aspects of each block.The blocks areas follows : An envelope detector for data reception ;A comparator for data demodulation ; An oscillator to provide a clock for the system ; A correlator to compare the received message with a reference,; A current source to provide temperature robustness.Chapter IV provides an analysis of the entire wireless sensor node. An estimation of the node autonomy is presented and a comparison with a node designed with market components is presented. Perspectives of improvement for future works will also be presented

6

Kraemer, Michael M. "Design of a low-power 60 GHz transceiver front-end and behavioral modeling and implementation of its key building blocks in 65 nm CMOS." Thesis, Toulouse, INSA, 2010. http://www.theses.fr/2010ISAT0027/document.

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La réglementation mondiale, pour des appareils de courte portée, permet l’utilisation sans licence de plusieurs Gigahertz de bande autour de 60 GHz. La bande des 60 GHz répond aux besoins des applications telles que les réseaux de capteurs très haut débit autonome en énergie,ou les transmissions à plusieurs Gbit/s avec des contraintes de consommation d’énergie. Il y a encore peu de temps, les interfaces radios fonctionnant dans la bande millimétrique n’étaient réalisables qu’en utilisant des technologies III-V couteuses. Aujourd’hui, les avancées des technologies CMOS nanométriques permettent la conception et la production en masse des circuits intégrées radiofréquences (RFIC) à faible coût.Cette thèse s’inscrit dans des travaux de recherches dédiés à la réalisation d’un système dans un boîtier (SiP, System in Package) à 60 GHz contenant à la fois l’interface radio (bande de base et circuits RF) ainsi qu’un réseau d’antennes. La première partie de cette thèse est dédiée la conception de la tête RF de l’émetteur-récepteur à faible consommation pour l’interface radio. Les blocs clefs de cette tête RF (amplificateurs, mélangeurs et un oscillateur commandé en tension) sont conçus, réalisés et mesurés en utilisant la technologie CMOS 65 nm de ST Microelectronics. Des éléments actifs et passifs sont développés spécifiquement pour l’utilisation au sein de ces blocs. Une étape importante vers l’intégration de la tête RF complète de l’émetteur-récepteur est l’assemblage de ces blocs de base afin de réaliser une puce émetteur et une puce récepteur. A ce but, une tête RF pour le récepteur a été réalisée. Ce circuit présent une consommation et un encombrement plus réduit que l’état de l’art.La deuxième partie de cette thèse présente le développement des modèles comportementaux des blocs de base conçus. Ces modèles au niveau système sont nécessaires afin de simuler le comportement du SIP, qui devient trop complexe si des modèles détaillés du niveau circuitsont utilisés. Dans cette thèse, une nouvelle technique modélisant le comportement en régime transitoire et régime permanent ainsi que le bruit de phase des oscillateurs commandés en tension est proposée. Ce modèle est implémenté dans le langage de description de matérielVHDL-AMS. La technique proposée utilise des réseaux de neurones artificiels pour approximer la caractéristique non linéaire du circuit. La dynamique est décrite dans l’espace d’état. Grâce à ce modèle, il est possible de réduire d’une façon drastique le temps de calcul des simulations système tout en conservant une excellente précision
Worldwide regulations for short range communication devices allow the unlicensed use of several Gigahertz of bandwidth in the frequency band around 60GHz. This 60GHz band is ideally suited for applications like very high data rate, energy-autonomous wireless sensor networks or Gbit/s multimedia links with low power constraints. Not long ago, radio interfaces that operate in the millimeter-wave frequency range could only be realized using expensive compound semiconductor technologies. Today, the latest sub-micron CMOS technologies can be used to design 60GHz radio frequency integrated circuits (RFICs)at very low cost in mass production. This thesis is part of an effort to realize a low power System in Package (SiP) including both the radio interface (with baseband and RF circuitry) and an antenna array to directly transmit and receive a 60GHz signal. The first part of this thesis deals with the design of the low power RF transceiver front-end for the radio interface. The key building blocks of this RF front-end (amplifiers, mixers and a voltage controlled oscillator (VCO)) are designed, realized and measured using the 65nm CMOS technology of ST Microelectronics. Full custom active and passive devices are developed for the use within these building blocks. An important step towards the full integration of the RF transceiver front-end is the assembly of these building blocks to form basic transmitter and receiver chips. Circuits with small chip size and low power consumption compared to the state of the art have been accomplished.The second part of this thesis concerns the development of behavioral models for the designed building blocks. These system level models are necessary to simulate the behavior of the entire SiP, which becomes too complex when using detailed circuit level models. In particular, a novel technique to model the transient, steady state and phase noise behavior of the VCO in the hardware description language VHDL-AMS is proposed and implemented. The model uses a state space description to describe the dynamic behavior of the VCO. Its nonlinearity is approximated by artificial neural networks. A drastic reduction of simulation time with respect to the circuit level model has been achieved, while at the same time maintaining a very high level of accuracy

7

Coulot, Thomas. "Stratégie d'alimentation pour les SoCs RF très faible consommation." Phd thesis, Université de Grenoble, 2013. http://tel.archives-ouvertes.fr/tel-00951423.

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Les réseaux de capteurs sans fil nécessitent des fonctions de calcul et de transmissionradio associées à chaque capteur. Les SoCs RF intégrant ces fonctions doivent avoir uneautonomie la plus grande possible et donc une très faible consommation. Aujourd'hui, leursperformances énergétiques pourraient être fortement améliorées par des systèmes d'alimentationinnovants. En effet, les circuits d'alimentation remplissent leur fonction classique de conversiond'énergie mais aussi des fonctions d'isolation des blocs RF et digitaux. Leurs performancess'évaluent donc en termes d'efficacité énergétique et de réponse transitoire mais aussi d'isolationentre blocs et de réjection de bruit.Ce travail de thèse concerne l'intégration du système de gestion et de distribution del'énergie aux différents blocs RF d'un émetteur/récepteur en élaborant une méthodologie " topdown" pour déterminer la sensibilité de chaque bloc à son alimentation et en construisant unearchitecture innovante et dynamique de gestion/distribution de l'énergie sur le SoC. Cetteméthodologie repose sur la disponibilité de régulateurs de tension présentant des performancesadaptées. Un deuxième volet du travail de thèse a donc été de réaliser un régulateur linéaire detype LDO à forte réjection sur une bande passante relativement large et bien adapté àl'alimentation de blocs RF très sensibles aux bruits de l'alimentation.

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Kraemer, Michael. "Design of a low-power 60 GHz transceiver front-end and behavioral modeling and implementation of its key building blocks in 65 nm CMOS." Phd thesis, INSA de Toulouse, 2010. http://tel.archives-ouvertes.fr/tel-00554674.

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Анотація:

Worldwide regulations for short range communication devices allow the unlicensed use of several Gigahertz of bandwidth in the frequency band around 60 GHz. This 60GHz band is ideally suited for applications like very high data rate, energy-autonomous wireless sensor networks or Gbit/s multimedia links with low power constraints. Not long ago, radio interfaces that operate in the millimeter-wave frequency range could only be realized using expensive compound semiconductor technologies. Today, the latest sub-micron CMOS technologies can be used to design 60GHz radio frequency integrated circuits (RFICs) at very low cost in mass production. This thesis is part of an effort to realize a low power System in Package (SiP) including both the radio interface (with baseband and RF circuitry) and an antenna array to directly transmit and receive a 60GHz signal. The first part of this thesis deals with the design of the low power RF transceiver front-end for the radio interface. The key building blocks of this RF front-end (amplifiers, mixers and a voltage controlled oscillator (VCO)) are designed, realized and measured using the 65nm CMOS technology of ST Microelectronics. Full custom active and passive devices are developed and characterized for the use within these building blocks. An important step towards the full integration of the RF transceiver front-end is the assembly of these building blocks to form a basic receiver chip. Circuits with small chip size and low power consumption compared to the state of the art have been accomplished. The second part of this thesis concerns the development of behavioral models for the designed building blocks. These system level models are necessary to simulate the behavior of the entire SiP, which becomes too complex when using detailed circuit level models. In particular, a novel technique to model the transient, steady state and phase noise behavior of the VCO in the hardware description language VHDL-AMS is proposed and implemente d. The model uses a state space description to describe the dynamic behavior of the VCO. Its nonlinearity is approximated by artificial neural networks. A drastic reduction of simulation time with respect to the circuit level model has been achieved, while at the same time maintaining a very high level of accuracy.

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Inanlou, Farzad Michael-David. "Innovative transceiver approaches for low-power near-field and far-field applications." Diss., Georgia Institute of Technology, 2014. http://hdl.handle.net/1853/52245.

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Анотація:

Wireless operation, near-field or far-field, is a core functionality of any mobile or autonomous system. These systems are battery operated or most often utilize energy scavenging as a means of power generation. Limited access to power, expected long and uninterrupted operation, and constrained physical parameters (e.g. weight and size), which limit overall power harvesting capabilities, are factors that outline the importance for innovative low-power approaches and designs in advanced low-power wireless applications. Low-power approaches become especially important for the wireless transceiver, the block in charge of wireless/remote functionality of the system, as this block is usually the most power hungry component in an integrated system-on-chip (SoC). Three such advanced applications with stringent power requirements are examined including space-based exploratory remote sensing probes and their associated radiation effects, millimeter-wave phased-array radar for high-altitude tactical and geological imaging, and implantable biomedical devices (IMDs), leading to the proposal and implementation of low-power wireless solutions for these applications in SiGe BiCMOS and CMOS and platforms.

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Sirigiri, Vijay Krishna. "Ultra-Low Power Ultra-Fast Hybrid CNEMS-CMOS FPGAs." Case Western Reserve University School of Graduate Studies / OhioLINK, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=case1291259866.

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Книги з теми "Ultra Low Power CMOS RF":

1

Yeo, Kiat Seng. CMOS/BiCMOS ULSI: Low voltage, low power. Upper Saddle River, NJ: Prentice Hall PTR, 2002.

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2

Alvarado, Unai, Guillermo Bistué, and Iñigo Adín. Low Power RF Circuit Design in Standard CMOS Technology. Berlin, Heidelberg: Springer Berlin Heidelberg, 2012. http://dx.doi.org/10.1007/978-3-642-22987-9.

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3

Lin, Zhicheng, Pui-In Mak, and Rui Paulo Martins. Ultra-Low-Power and Ultra-Low-Cost Short-Range Wireless Receivers in Nanoscale CMOS. Cham: Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-21524-2.

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4

Severo, Lucas Compassi, and Wilhelmus Adrianus Maria Van Noije. Ultra-low Voltage Low Power Active-RC Filters and Amplifiers for Low Energy RF Receivers. Cham: Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-030-90103-5.

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5

Yŏnʼguwŏn, Hanʼguk Chŏnja Tʻongsin, ред. Chʻo chŏjŏllyŏk RF/HW/SW tʻonghap SoC =: Integrated development of ultra low power. [Seoul]: Chŏngbo Tʻongsinbu, 2008.

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6

Yeo, Kiat-Seng, Samir S. Rofail, and Wang-Ling Goh. CMOS/BiCMOS ULSI: Low Voltage, Low Power. Prentice Hall PTR, 2001.

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7

Low Power Rf Circuit Design In Standard Cmos Technology. Springer, 2011.

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8

Alvarado, Unai, Guillermo Bistué, and Iñigo Adín. Low Power RF Circuit Design in Standard CMOS Technology. Springer, 2011.

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9

Alvarado, Unai, Guillermo Bistué, and Iñigo Adín. Low Power RF Circuit Design in Standard CMOS Technology. Springer, 2013.

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10

Martins, Rui Paulo, Zhicheng Lin, and Pui-In Mak (Elvis). Ultra-Low-Power and Ultra-Low-Cost Short-Range Wireless Receivers in Nanoscale CMOS. Springer, 2015.

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Частини книг з теми "Ultra Low Power CMOS RF":

1

Law, Man-Kay. "Ultra-low Power/Energy Efficient High Accuracy CMOS Temperature Sensors." In Selected Topics in Power, RF, and Mixed-Signal ICs, 229–66. New York: River Publishers, 2022. http://dx.doi.org/10.1201/9781003339434-7.

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2

Wang, Yongpan, Chun Zhang, Ziqiang Wang, and Yongming Li. "An Ultra Low Power RF Frontend of UHF RFID Transponder Using 65 nm CMOS Technology." In Advances in Intelligent and Soft Computing, 85–92. Berlin, Heidelberg: Springer Berlin Heidelberg, 2012. http://dx.doi.org/10.1007/978-3-642-29148-7_13.

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3

Yadav, Namrata, Deepak Prasad, Vijay Nath, and Manish Kumar. "An Ultra Low Power CMOS RF Front-End-Based LNA and Mixer for GPS Application." In Proceedings of the International Conference on Microelectronics, Computing & Communication Systems, 375–85. Singapore: Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-5565-2_33.

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4

Harisankar, P. S., Vaibhav Ruparelia, Mayank Chakraverty, and Hisham Rahman. "Implementation and Analysis of Ultra Low Power 2.4 GHz RF CMOS Double Balanced Down Conversion Subthreshold Mixer." In Lecture Notes in Electrical Engineering, 485–95. New Delhi: Springer India, 2015. http://dx.doi.org/10.1007/978-81-322-2728-1_45.

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5

Yee, Dennis. "Broadband RF Transmission and Modulation." In Low-Power CMOS Wireless Communications, 83–115. Boston, MA: Springer US, 1998. http://dx.doi.org/10.1007/978-1-4615-5457-8_5.

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6

Sheng, Samuel, and Robert Brodersen. "The Receiver: Analog RF Front-End." In Low-Power CMOS Wireless Communications, 117–74. Boston, MA: Springer US, 1998. http://dx.doi.org/10.1007/978-1-4615-5457-8_6.

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7

Babaie, Masoud, Mina Shahmohammadi, and Robert Bogdan Staszewski. "An Ultra-Low Phase Noise Class-F2 CMOS Oscillator." In RF CMOS Oscillators for Modern Wireless Applications, 59–85. New York: River Publishers, 2022. http://dx.doi.org/10.1201/9781003339311-4.

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8

Yunbo, Zhou, Yu Zongguang, and Yang Yu. "Ultra-Low Power CMOS Charge-Sensitive Preamplifier." In Intelligence Computation and Evolutionary Computation, 975–82. Berlin, Heidelberg: Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-31656-2_134.

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9

Svelto, Francesco, Enrico Sacchi, Francesco Gatta, Danilo Manstretta, and Rinaldo Castello. "CMOS Low-Noise Amplifier Design." In Low-Power Design Techniques and CAD Tools for Analog and RF Integrated Circuits, 251–65. Boston, MA: Springer US, 2001. http://dx.doi.org/10.1007/0-306-48089-1_11.

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10

Singh, Jyoti, Megha Agarwal, Vinita Mardi, Madhu Ray, Deepak Prasad, Vijay Nath, and Manish Mishra. "Design of Ultra-Low-Power CMOS Class E Power Amplifier." In Proceedings of the International Conference on Microelectronics, Computing & Communication Systems, 317–26. Singapore: Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-5565-2_28.

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Тези доповідей конференцій з теми "Ultra Low Power CMOS RF":

1

Chen, Pang-Hsing, and Jeng-Rern Yang. "A 3–10 GHz low power ultra-wideband CMOS LNA." In 2011 IEEE International RF and Microwave Conference (RFM). IEEE, 2011. http://dx.doi.org/10.1109/rfm.2011.6168766.

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2

Salmeh, Roghoyeh. "An Ultra Low Power ESD Protected Mixer in 90nm RF CMOS." In 2006 49th IEEE International Midwest Symposium on Circuits and Systems. IEEE, 2006. http://dx.doi.org/10.1109/mwscas.2006.381991.

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3

Abdelbadie, Sameh A., Andrew A. Mikhael, Mostafa M. Helmy, Bassel A. Elgharabawy, and Ahmed N. Mohieldin. "An ultra-low-power RF receiver for IoT applications using 65nm CMOS technology." In 2018 7th International Conference on Modern Circuits and Systems Technologies (MOCAST). IEEE, 2018. http://dx.doi.org/10.1109/mocast.2018.8376581.

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4

Wang, R., Y. Qi, and H. M. Lavasani. "A Highly Efficient CMOS Rectifier for Ultra-Low-Power Ambient RF Energy Harvesting." In 2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS). IEEE, 2021. http://dx.doi.org/10.1109/mwscas47672.2021.9531775.

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5

Noghabaei, Seyed Mohammad, Rafael L. Radin, Yvon Savaria, and Mohamad Sawan. "A High-Efficiency Ultra-Low-Power CMOS Rectifier for RF Energy Harvesting Applications." In 2018 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2018. http://dx.doi.org/10.1109/iscas.2018.8351149.

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6

Al-Shebanee, Durgham, Ralf Wunderlich, and Stefan Heinen. "Design of highly sensitive CMOS RF energy harvester using ultra-low power charge pump." In 2015 IEEE Wireless Power Transfer Conference (WPTC). IEEE, 2015. http://dx.doi.org/10.1109/wpt.2015.7140163.

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7

Tu, Xiaojun, and Jeremy H. Holleman. "An ultra-low-power 902–928MHz RF receiver front-end in CMOS 90nm process." In 2012 IEEE International Symposium on Circuits and Systems - ISCAS 2012. IEEE, 2012. http://dx.doi.org/10.1109/iscas.2012.6271726.

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8

Pour, Fariborz Lohrabi, and Dong Sam Ha. "2.4 GHz Ultra-Low Power Direct Digital-to-RF CMOS Transmitter for Biosensing Applications." In 2023 IEEE Biomedical Circuits and Systems Conference (BioCAS). IEEE, 2023. http://dx.doi.org/10.1109/biocas58349.2023.10388855.

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9

Hora, Jefferson A., Nieva M. Mapula, Emmanuel D. Talagon, Marnier B. Bate, Rovil S. Berido, and Gene Fe P. Palencia. "Design of RF to DC converter in 90nm CMOS technology for ultra-low power application." In 2015 International Conference on Humanoid, Nanotechnology, Information Technology,Communication and Control, Environment and Management (HNICEM). IEEE, 2015. http://dx.doi.org/10.1109/hnicem.2015.7393175.

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Ikeda, Sho, Sang-yeop Lee, Shin Yonezawa, Yiming Fang, Motohiro Takayasu, Taisuke Hamada, Yosuke Ishikawa, Hiroyuki Ito, Noboru Ishihara, and Kazuya Masu. "A 0.5-V 5.8-GHz ultra-low-power RF transceiver for wireless sensor network in 65nm CMOS." In 2014 IEEE Radio Frequency Integrated Circuits Symposium (RFIC). IEEE, 2014. http://dx.doi.org/10.1109/rfic.2014.6851649.

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