Статті в журналах з теми "Tunnel FETs"
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Lind, Erik, Elvedin Memisevic, Anil W. Dey, and Lars-Erik Wernersson. "III-V Heterostructure Nanowire Tunnel FETs." IEEE Journal of the Electron Devices Society 3, no. 3 (May 2015): 96–102. http://dx.doi.org/10.1109/jeds.2015.2388811.
Повний текст джерелаPandey, Rahul, Saurabh Mookerjea, and Suman Datta. "Opportunities and Challenges of Tunnel FETs." IEEE Transactions on Circuits and Systems I: Regular Papers 63, no. 12 (December 2016): 2128–38. http://dx.doi.org/10.1109/tcsi.2016.2614698.
Повний текст джерелаSedighi, Behnam, Xiaobo Sharon Hu, Huichu Liu, Joseph J. Nahas, and Michael Niemier. "Analog Circuit Design Using Tunnel-FETs." IEEE Transactions on Circuits and Systems I: Regular Papers 62, no. 1 (January 2015): 39–48. http://dx.doi.org/10.1109/tcsi.2014.2342371.
Повний текст джерелаMoselund, K. E., H. Schmid, C. Bessire, M. T. Bjork, H. Ghoneim, and H. Riel. "InAs–Si Nanowire Heterojunction Tunnel FETs." IEEE Electron Device Letters 33, no. 10 (October 2012): 1453–55. http://dx.doi.org/10.1109/led.2012.2206789.
Повний текст джерелаOrtiz-Conde, Adelmo, Francisco J. García-Sánchez, Juan Muci, Andrea Sucre-González, João Antonio Martino, Paula Ghedini Der Agopian, and Cor Claeys. "Threshold voltage extraction in Tunnel FETs." Solid-State Electronics 93 (March 2014): 49–55. http://dx.doi.org/10.1016/j.sse.2013.12.010.
Повний текст джерелаWu, Jianzhi, Jie Min, and Yuan Taur. "Short-Channel Effects in Tunnel FETs." IEEE Transactions on Electron Devices 62, no. 9 (September 2015): 3019–24. http://dx.doi.org/10.1109/ted.2015.2458977.
Повний текст джерелаVerhulst, Anne S., William G. Vandenberghe, Karen Maex, Stefan De Gendt, Marc M. Heyns, and Guido Groeseneken. "Complementary Silicon-Based Heterostructure Tunnel-FETs With High Tunnel Rates." IEEE Electron Device Letters 29, no. 12 (December 2008): 1398–401. http://dx.doi.org/10.1109/led.2008.2007599.
Повний текст джерелаHuang, Jun Z., Pengyu Long, Michael Povolotskyi, Gerhard Klimeck, and Mark J. W. Rodwell. "P-Type Tunnel FETs With Triple Heterojunctions." IEEE Journal of the Electron Devices Society 4, no. 6 (November 2016): 410–15. http://dx.doi.org/10.1109/jeds.2016.2614915.
Повний текст джерелаAvedillo, M. J., and J. Núñez. "Improving speed of tunnel FETs logic circuits." Electronics Letters 51, no. 21 (October 2015): 1702–4. http://dx.doi.org/10.1049/el.2015.2416.
Повний текст джерелаPandey, Rahul, Bijesh Rajamohanan, Huichu Liu, Vijaykrishnan Narayanan, and Suman Datta. "Electrical Noise in Heterojunction Interband Tunnel FETs." IEEE Transactions on Electron Devices 61, no. 2 (February 2014): 552–60. http://dx.doi.org/10.1109/ted.2013.2293497.
Повний текст джерелаDayeh, Shadi A., and S. Tom Picraux. "Axial Ge/Si Nanowire Heterostructure Tunnel FETs." ECS Transactions 33, no. 6 (December 17, 2019): 373–78. http://dx.doi.org/10.1149/1.3487568.
Повний текст джерелаRichter, S., S. Blaeser, L. Knoll, S. Trellenkamp, A. Fox, A. Schäfer, J. M. Hartmann, Q. T. Zhao, and S. Mantl. "Silicon–germanium nanowire tunnel-FETs with homo- and heterostructure tunnel junctions." Solid-State Electronics 98 (August 2014): 75–80. http://dx.doi.org/10.1016/j.sse.2014.04.014.
Повний текст джерелаGudlavalleti, R. H., B. Saman, R. Mays, M. Lingalugari, E. Heller, J. Chandy, and F. Jain. "Modeling of Multi-State Si and Ge Cladded Quantum Dot Gate FETs Using Verilog and ABM Simulations." International Journal of High Speed Electronics and Systems 28, no. 03n04 (September 2019): 1940026. http://dx.doi.org/10.1142/s0129156419400263.
Повний текст джерелаAghanejad Ahmadchally, Alireza, and Morteza Gholipour. "Investigation of 6-armchair graphene nanoribbon tunnel FETs." Journal of Computational Electronics 20, no. 3 (May 6, 2021): 1114–24. http://dx.doi.org/10.1007/s10825-021-01709-4.
Повний текст джерелаZhang, Qin, Yeqing Lu, Curt A. Richter, Debdeep Jena, and Alan Seabaugh. "Optimum Bandgap and Supply Voltage in Tunnel FETs." IEEE Transactions on Electron Devices 61, no. 8 (August 2014): 2719–24. http://dx.doi.org/10.1109/ted.2014.2330805.
Повний текст джерелаIlatikhameneh, Hesameddin, Gerhard Klimeck, and Rajib Rahman. "Can Homojunction Tunnel FETs Scale Below 10 nm?" IEEE Electron Device Letters 37, no. 1 (January 2016): 115–18. http://dx.doi.org/10.1109/led.2015.2501820.
Повний текст джерелаChen, Hongwei, Li Yuan, Qi Zhou, Chunhua Zhou, and Kevin J. Chen. "Normally-off AlGaN/GaN power tunnel-junction FETs." physica status solidi (c) 9, no. 3-4 (February 3, 2012): 871–74. http://dx.doi.org/10.1002/pssc.201100338.
Повний текст джерелаPala, Marco G., and David Esseni. "Interface Traps in InAs Nanowire Tunnel-FETs and MOSFETs—Part I: Model Description and Single Trap Analysis in Tunnel-FETs." IEEE Transactions on Electron Devices 60, no. 9 (September 2013): 2795–801. http://dx.doi.org/10.1109/ted.2013.2274196.
Повний текст джерелаKARMAKAR, SUPRIYA, JOHN A. CHANDY, and FAQUIR C. JAIN. "APPLICATION OF 25 NM QUANTUM DOT GATE FETs TO THE DESIGN OF ADC AND DAC CIRCUITS." International Journal of High Speed Electronics and Systems 20, no. 03 (September 2011): 653–68. http://dx.doi.org/10.1142/s0129156411006945.
Повний текст джерелаChen, Yi-Ju, and Bing-Yue Tsui. "Bandgap engineering of Si1− x Ge x epitaxial tunnel layer for tunnel FETs." Japanese Journal of Applied Physics 57, no. 8 (July 13, 2018): 084201. http://dx.doi.org/10.7567/jjap.57.084201.
Повний текст джерелаZhao, Q. T., S. Richter, L. Knoll, G. V. Luong, S. Blaeser, C. Schulte-Braucks, A. Schafer, S. Trellenkamp, D. Buca, and S. Mantl. "(Invited) Si Nanowire Tunnel FETs for Energy Efficient Nanoelectronics." ECS Transactions 66, no. 4 (May 15, 2015): 69–78. http://dx.doi.org/10.1149/06604.0069ecst.
Повний текст джерелаMallik, A. "Tunnel FETs for Mixed-Signal System-On-Chip Applications." ECS Transactions 53, no. 5 (May 2, 2013): 93–104. http://dx.doi.org/10.1149/05305.0093ecst.
Повний текст джерелаConzatti, F., M. G. Pala, and D. Esseni. "Surface-Roughness-Induced Variability in Nanowire InAs Tunnel FETs." IEEE Electron Device Letters 33, no. 6 (June 2012): 806–8. http://dx.doi.org/10.1109/led.2012.2192091.
Повний текст джерелаJiang, Zhi, Yiqi Zhuang, Cong Li, Ping Wang, and Yuqi Liu. "Vertical-dual-source tunnel FETs with steeper subthreshold swing." Journal of Semiconductors 37, no. 9 (September 2016): 094003. http://dx.doi.org/10.1088/1674-4926/37/9/094003.
Повний текст джерелаFiore, Antonio, Jacopo Franco, Moonju Cho, Felice Crupi, Sebastiano Strangio, Philippe J. Roussel, Rita Rooyackers, Nadine Collaert, and Dimitri Linten. "Single Defect Discharge Events in Vertical-Nanowire Tunnel-FETs." IEEE Transactions on Device and Materials Reliability 17, no. 1 (March 2017): 253–58. http://dx.doi.org/10.1109/tdmr.2017.2655623.
Повний текст джерелаConzatti, F., M. G. Pala, D. Esseni, E. Bano, and L. Selmi. "Strain-Induced Performance Improvements in InAs Nanowire Tunnel FETs." IEEE Transactions on Electron Devices 59, no. 8 (August 2012): 2085–92. http://dx.doi.org/10.1109/ted.2012.2200253.
Повний текст джерелаZhang, Lining, Xinnan Lin, Jin He, and Mansun Chan. "An Analytical Charge Model for Double-Gate Tunnel FETs." IEEE Transactions on Electron Devices 59, no. 12 (December 2012): 3217–23. http://dx.doi.org/10.1109/ted.2012.2217145.
Повний текст джерелаGupta, Sumeet Kumar, Jaydeep P. Kulkarni, Suman Datta, and Kaushik Roy. "Heterojunction Intra-Band Tunnel FETs for Low-Voltage SRAMs." IEEE Transactions on Electron Devices 59, no. 12 (December 2012): 3533–42. http://dx.doi.org/10.1109/ted.2012.2221127.
Повний текст джерелаBoucart, Kathy, and Adrian Mihai Ionescu. "A new definition of threshold voltage in Tunnel FETs." Solid-State Electronics 52, no. 9 (September 2008): 1318–23. http://dx.doi.org/10.1016/j.sse.2008.04.003.
Повний текст джерелаNajmzadeh, M., K. Boucart, W. Riess, and A. M. Ionescu. "Asymmetrically strained all-silicon multi-gate n-Tunnel FETs." Solid-State Electronics 54, no. 9 (September 2010): 935–41. http://dx.doi.org/10.1016/j.sse.2010.04.037.
Повний текст джерелаHutin, L., R. P. Oeflein, J. Borrel, S. Martinie, C. Tabone, C. Le Royer, and M. Vinet. "Investigation of ambipolar signature in SiGeOI homojunction tunnel FETs." Solid-State Electronics 115 (January 2016): 160–66. http://dx.doi.org/10.1016/j.sse.2015.08.007.
Повний текст джерелаDing, Lili, Elena Gnani, Simone Gerardin, Marta Bagatin, Francesco Driussi, Pierpaolo Palestri, Luca Selmi, Cyrille Le Royer, and Alessandro Paccagnella. "Total Ionizing Dose Effects in Si-Based Tunnel FETs." IEEE Transactions on Nuclear Science 61, no. 6 (December 2014): 2874–80. http://dx.doi.org/10.1109/tns.2014.2367548.
Повний текст джерелаDong, Yunpeng, Lining Zhang, Xiangbin Li, Xinnan Lin, and Mansun Chan. "A Compact Model for Double-Gate Heterojunction Tunnel FETs." IEEE Transactions on Electron Devices 63, no. 11 (November 2016): 4506–13. http://dx.doi.org/10.1109/ted.2016.2604001.
Повний текст джерелаHuang, Jun Z., Pengyu Long, Michael Povolotskyi, Gerhard Klimeck, and Mark J. W. Rodwell. "Scalable GaSb/InAs Tunnel FETs With Nonuniform Body Thickness." IEEE Transactions on Electron Devices 64, no. 1 (January 2017): 96–101. http://dx.doi.org/10.1109/ted.2016.2624744.
Повний текст джерелаMori, Yoshiaki, Shingo Sato, Yasuhisa Omura, Avik Chattopadhyay, and Abhijit Mallik. "On the definition of threshold voltage for tunnel FETs." Superlattices and Microstructures 107 (July 2017): 17–27. http://dx.doi.org/10.1016/j.spmi.2017.04.002.
Повний текст джерелаPanda, Subhrasmita, Sidhartha Dash, and Guru Prasad Mishra. "Extensive electrostatic investigation of workfunction-modulated SOI tunnel FETs." Journal of Computational Electronics 15, no. 4 (October 4, 2016): 1326–33. http://dx.doi.org/10.1007/s10825-016-0907-1.
Повний текст джерелаRoy, T., Z. R. Hesabi, C. A. Joiner, A. Fujimoto, and E. M. Vogel. "Barrier engineering for double layer CVD graphene tunnel FETs." Microelectronic Engineering 109 (September 2013): 117–19. http://dx.doi.org/10.1016/j.mee.2013.02.090.
Повний текст джерелаChen, Yi-Hsuan, William Cheng-Yu Ma, Jer-Yi Lin, Chun-Yen Lin, Po-Yang Hsu, Chi-Yuan Huang, and Tien-Sheng Chao. "Impact of Crystallization Method on Poly-Si Tunnel FETs." IEEE Electron Device Letters 36, no. 10 (October 2015): 1060–62. http://dx.doi.org/10.1109/led.2015.2468060.
Повний текст джерелаDharmireddy, Ajay Kumar, Dr Sreenivasa Rao Ijjada, and Dr I. Hema Latha. "Performance Analysis of Various Fin Patterns of Hybrid Tunnel FET." International Journal of Electrical and Electronics Research 10, no. 4 (December 30, 2022): 806–10. http://dx.doi.org/10.37391/ijeer.100407.
Повний текст джерелаXu, Hui Fang, Yue Hua Dai, Bang Gui Guan, and Yong Feng Zhang. "Two-dimensional analytical model for asymmetric dual-gate tunnel FETs." Japanese Journal of Applied Physics 56, no. 1 (December 5, 2016): 014301. http://dx.doi.org/10.7567/jjap.56.014301.
Повний текст джерелаTomioka, K., T. Fukui, and J. Motohisa. "(Invited) Vertical Tunnel FETs Using III-V Nanowire/Si Heterojunctions." ECS Transactions 69, no. 10 (October 2, 2015): 109–18. http://dx.doi.org/10.1149/06910.0109ecst.
Повний текст джерелаWang, Hao, Sheng Chang, Jin He, Qijun Huang, and Feng Liu. "The Dual Effects of Gate Dielectric Constant in Tunnel FETs." IEEE Journal of the Electron Devices Society 4, no. 6 (November 2016): 445–50. http://dx.doi.org/10.1109/jeds.2016.2610478.
Повний текст джерелаTomioka, K., and T. Fukui. "(Invited) Vertical Tunnel FETs Using III-V Nanowire/Si Heterojunctions." ECS Transactions 61, no. 3 (March 26, 2014): 81–89. http://dx.doi.org/10.1149/06103.0081ecst.
Повний текст джерелаKim, Jang Hyun, Sang Wan Kim, Hyun Woo Kim, and Byung‐Gook Park. "Vertical type double gate tunnelling FETs with thin tunnel barrier." Electronics Letters 51, no. 9 (April 2015): 718–20. http://dx.doi.org/10.1049/el.2014.3864.
Повний текст джерелаChen, Cheng, Qianqian Huang, Jiadi Zhu, Yang Zhao, Lingyi Guo, and Ru Huang. "New Understanding of Random Telegraph Noise Amplitude in Tunnel FETs." IEEE Transactions on Electron Devices 64, no. 8 (August 2017): 3324–30. http://dx.doi.org/10.1109/ted.2017.2712714.
Повний текст джерелаAhmed, Sheikh Z., Daniel S. Truesdell, Yaohua Tan, Benton H. Calhoun, and Avik W. Ghosh. "A comprehensive analysis of Auger generation impacted planar Tunnel FETs." Solid-State Electronics 169 (July 2020): 107782. http://dx.doi.org/10.1016/j.sse.2020.107782.
Повний текст джерелаZhang, Lining, and Mansun Chan. "SPICE Modeling of Double-Gate Tunnel-FETs Including Channel Transports." IEEE Transactions on Electron Devices 61, no. 2 (February 2014): 300–307. http://dx.doi.org/10.1109/ted.2013.2295237.
Повний текст джерелаGholizadeh, Mahdi, and Seyed Ebrahim Hosseini. "A 2-D Analytical Model for Double-Gate Tunnel FETs." IEEE Transactions on Electron Devices 61, no. 5 (May 2014): 1494–500. http://dx.doi.org/10.1109/ted.2014.2313037.
Повний текст джерелаGhosh, Krishnendu, and Uttam Singisetti. "RF Performance and Avalanche Breakdown Analysis of InN Tunnel FETs." IEEE Transactions on Electron Devices 61, no. 10 (October 2014): 3405–10. http://dx.doi.org/10.1109/ted.2014.2344914.
Повний текст джерелаTaur, Yuan, Jianzhi Wu, and Jie Min. "An Analytic Model for Heterojunction Tunnel FETs With Exponential Barrier." IEEE Transactions on Electron Devices 62, no. 5 (May 2015): 1399–404. http://dx.doi.org/10.1109/ted.2015.2407695.
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