Дисертації з теми "Tunnel FETs"
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Horst, Fabian. "Compact DC Modeling of Tunnel-FETs." Doctoral thesis, Universitat Rovira i Virgili, 2019. http://hdl.handle.net/10803/668957.
Повний текст джерелаEn la última década, el transistor de efecto de campo con efecto túnel (TFET) ha ganado mucho interés y se maneja como un posible sucesor de la tecnología MOSFET convencional. El transporte de carga en un TFET se basa en el mecanismo de túnel de banda a banda (B2B) y, por lo tanto, la pendiente sub-umbral a temperatura ambiente puede superar el límite de 60 mV / dec. Para describir y analizar el comportamiento del TFET en las simulaciones de circuitos, esta disertación introduce un modelo compacto de CC para TFET de doble compuerta. El enfoque de modelado considera el efecto túnel B2B con el efecto parasitario de la corriente túnel asistida por trampas (TAT) en el estado ON y AMBIPOLAR del TFET. Incluye un paquete de ecuaciones compactas del potencial 2D para describir el diagrama de banda del TFET. Basado en el diagrama de banda, el B2B y la corriente TAT se derivan por separado. Para hacerlo, primero se encuentra una expresión compacta para la longitud túnel, que luego se utiliza junto con un enfoque numérico robusto de tipo Wentzel-Kramers-Brillouin (WKB) para calcular la probabilidad túnel. Luego, usando la ecuación de túnel de Landauer, la tasa de generación túnel se calcula y aproxima para llegar a una expresión de forma cerrada para la densidad de corriente. Con una aproximación adicional de la densidad de corriente por una función matemática, se logran expresiones compactas para el túnel B2B resultante y la corriente TAT. La verificación del modelo se realiza con la ayuda de los datos de simulación TCAD Sentaurus para varias configuraciones de simulación. Además, la validez del modelo se demuestra mediante mediciones de TFET complementarios fabricados. Para demostrar la estabilidad numérica y la continuidad, así como la flexibilidad, se realizan y analizan simulaciones de circuitos lógicos basados en TFET como un inversor de una sola etapa o una celda SRAM. La combinación del modelo CC con un modelo TFET AC permite una simulación transitoria de un oscilador en anillo de 11 etapas.
In the last decade, the tunnel field-effect transistor (TFET) has gained a lot of interest and is handled as a possible successor of the conventional MOSFET technology. The current transport of a TFET is based on the band-to-band (B2B) tunneling mechanism and therefore, the subthreshold slope at room temperature can overcome the limit of 60 mV/dec. In order to describe and analyze the TFET behavior in circuit simulations, this dissertation introduces a compact DC model for double-gate TFETs. The modeling approach considers the B2B tunneling and the parasitic effect of trap-assisted tunneling (TAT) in the ON- and AMBIPOLAR-state of the TFET. It includes a 2D compact potential equation package to de-scribe the band diagram of the TFET. Based on the band diagram, the B2B tunneling and TAT current part are derived separately. In order to do so, firstly a compact expression for the tunneling length is found, which is then used together with a numerical robust Wentzel-Kramers-Brillouin (WKB) approach to calculate the tunneling probability. Afterwards, using Landauer’s tunneling equation, the tunneling generation rate is calculated and approximated to come to a closed-form expression for the current density. Further approximation of the current density by a mathematical function, compact expressions for the resulting B2B tun-neling and TAT current are achieved. The verification of the model is done with the help of TCAD Sentaurus simulation data for various simulation setups. Furthermore, the validity of the model is proven by measurements of fabricated complementary TFETs. In order to demonstrate the numerical stability and continuity as well as the flexibility, simulations of TFET-based logic circuits like a single-stage inverter or an SRAM cell are performed and analyzed. The combination of the DC model with an TFET AC model allows for a transient simulation of an 11-stage ring oscillator.
Gräf, Michael. "Two-Dimensional Analytical Modeling of Tunnel-FETs." Doctoral thesis, Universitat Rovira i Virgili, 2017. http://hdl.handle.net/10803/450516.
Повний текст джерелаBasado en un mecanismo de transporte de corriente banda a banda, el Tunnel-FET es capaz de superar la limitación de pendiente sub-umbral física del MOSFET de 60 mV/dec. Por lo tanto, esto lo convierte en uno de los dispositivos más prometedores para ser el sucesor del MOSFET clásico en los últimos años. Esta tesis describe todos los pasos necesarios para modelar analíticamente un Tunnel-FET de doble puerta. El modelo incluye una solución electrostática bidimensional en todas las regiones del dispositivo, lo que permite incluso simulaciones de hetero-unión del dispositivo. Para un comportamiento más realista del dispositivo se tiene en cuenta el rendimiento del dispositivo que limita los perfiles de dopaje de forma Gaussiana en las uniones del canal. Las expresiones para las probabilidades de túnel de banda a banda y de Trap-Assisted-Tunneling (TAT) se implementan mediante un enfoque de WKB cuasi bidimensional. La corriente del dispositivo se calcula mediante la teoría de transmisión de Landauer. El modelo es válido para dispositivos de canal corto y las estancias están bien comparadas con los datos de simulación TCAD Sentaurus y con las mediciones proporcionadas. Se introduce un modelo general para las fluctuaciones del dopado aleatorio, que predice las influencias características del dispositivo en la corriente de salida y el voltaje umbral. El modelo se aplica al MOSFET, así como a los dispositivos TFET.
Based on a band-to-band current transport mechanism, the Tunnel-FET is able to overcome the physical subthreshold slope limitation of the MOSFET of 60 mV/dec. Therefore, it has become one of the most promising devices to be the successor of the classical MOSFET in the last few years. This thesis describes all necessary steps to analytically model a double-gate Tunnel-FET. The model includes a two-dimensional electrostatic solution in all device regions, which enables even hetero-junction device simulations. Device performance limiting Gaussian-shaped doping profiles at the channel junctions are taken into account for a realistic device behavior. Expressions for the band-to-band and trap-assisted-tunneling probabilities are implemented by a quasi two-dimensional WKB approach. The device current is calculated based on Landauer's transmission theory. The model is valid for short-channel devices and stays is good agreement with the TCAD Sentaurus simulation data and with the provided measurements. A general model for random-dopant-fluctuations is introduced, which predicts characteristic device influences on the output current and threshold voltage. The model is applied to MOSFET, as well as TFET devices.
Yu, Tao Ph D. Massachusetts Institute of Technology. "InGaAs/GaAsSb type-Il heterojunction vertical tunnel-FETs." Thesis, Massachusetts Institute of Technology, 2013. http://hdl.handle.net/1721.1/84857.
Повний текст джерелаCataloged from PDF version of thesis.
Includes bibliographical references (pages 59-62).
The supply voltage (VDD) scaling of conventional CMOS technology is approaching its limit due to the physical limit of 60 mV/dec subthreshold swing (SS) at room temperature and the requirement for controlled leakage current. In order to continue VDD scaling for low power applications, novel device structures with steep SS have been proposed. Tunnel-FETs (TFETs) are among the most attractive device structure due to their compatibility with conventional CMOS technology and the potential for outstanding VDD scalability. Heterostructure vertical TFETs with enhanced gate modulation promise significantly improved electrostatic control and drive current relative to lateral tunneling designs. In this thesis, vertical TFETs based on InGaAs/GaAsSb heterostructure are investigated in terms of design, fabrication and electrical characterization. Ino.53Gao.47As/ GaAso.5Sb0.5 heterostructure vertical TFETs are fabricated with an airbridge structure, designed to prevent parasitic tunneling path in the device, with a two-step highly selective undercut process. Electrical measurement of the devices with various gate areas demonstrates area-dependent tunneling current. The Ino.53Gao.47As/ GaAs0 .5 Sb. 5 vertical TFETs with HfO2 high-k gate dielectric (EOT ~ 1.3 nm) exhibit minimum sub-threshold swings of 140 and 58 mV/dec at 300 and 150 K respectively, with an ON-current density of 0.5 [mu]A/[mu]m2 at VDD = 0.5 V at 300 K. A physical model of TFET operation in the ON-state is proposed based on temperature dependent measurements, which reveal a current barrier due to an ungated region near the drain. Simulations illustrate that the gate-to-drain distance must be scaled to eliminate this barrier. In diode-mode operation, outstanding backward diode performance is demonstrated in this system for the first time, with gate-tunable curvature coefficient of 30 V1 near VDS= 0 V. These results indicate the potential of vertical TFETs in hybrid IC applications.
by Tao Yu.
S.M.
Farokhnejad, Atieh. "Compact Modeling of Intrinsic Capacitances in Double-Gate Tunnel-FETs." Doctoral thesis, Universitat Rovira i Virgili, 2020. http://hdl.handle.net/10803/669806.
Повний текст джерелаLa miniaturización de los MOSFET en los circuitos integrados ha elevado la tecnología microelectrónica. Esta tendencia también aumenta el grado de complejidad de estos circuitos y sus componentes básicos. En los MOSFET convencionales, la corriente se basa en la emisión termoiónica de portadores de carga, que por ello limita la pendiente subumbral en estos transistores a 60 mV/dec. Por tanto, para superar este límite y continuar con la miniaturización para mantener el ritmo de la ley de Moore, se requieren estructuras alternativas. Entre estas, el transistor de efecto de campo por túnel (TFET) se considera un posible sucesor del MOSFET. Debido a su mecanismo alternativo de transporte de corriente, conocido como túnel de banda a banda (B2B), la pendiente subumbral en TFET puede hacerse inferior al límite de 60 mV/dec. Para comprender y estimar el comportamiento de los TFET, no sólo como un elemento único sino también a nivel de circuito, se requiere un modelo compacto de este dispositivo. En esta tesis se presenta un modelo basado en carga para describir el comportamiento capacitivo de un TFET de doble puerta (DG TFET). Sin embargo, la simplicidad y la flexibilidad del modelo permiten usarlo para otro tipo de estructuras TFET, como los TFET planares o de nanohílos de una sola puerta (SG TFETs). El modelo es verificado con las simulaciones TCAD, así como con medidas experimentales de TFET fabricados. El modelo de capacitancia también incluye el efecto de los elementos parásitos. Además, en el contexto de este trabajo también se investiga la influencia de los contactos de barrera Schottky en el comportamiento capacitivo de los TFET. Este modelo finalmente se combina con un modelo DC compacto existente para formar un modelo TFET compacto completo. A continuación, el modelo compacto se implementa para simulaciones transitorias de circuitos osciladores de anillo basados en TFET.
Miniaturization of the MOSFETs on the integrated circuits has elevated the microelectronic technology. This trend also increases the degree of complexity of these circuits and their building blocks. In conventional MOSFETs the current is based on the thermionic—emission of charge carrier, which therefore limits the subthreshold swing in these transistors to 60 mV/dec. Hence, to overcome this limit and continue with down scaling to keep pace with the Moor’s law, alternative structures are required. Among these, the tunnel—field—effect transistor (TFET) is considered as a potential successor of the MOSFET. Due to its alternative current transport mechanism, known as band—to—band (B2B) tunneling, the subthreshold swing in TFETs can overcome the 60 mV/dec limit. In order to comprehend and estimate the behavior of TFETs, not only as a single element but also on the circuit level, a compact model of this device is required. In this dissertation a charge –based model to describes the capacitive behavior of a double—gate (DG) TFET is presented. However, simplicity and flexibility of the model allow to use it for other type of TFET structures such as single—gate (SG) planar or nanowire TFETs. The model is verified with the TCAD simulations as well as the measurement data of fabricated TFETs. The capacitance model also includes the effect of the parasitic elements. Furthermore, in the context of this work also the influence of Schottky barrier contacts on the capacitive behavior of TFETs is investigated. This model is finally combined with an existing compact DC model to form a complete compact TFET model. The compact model is then implemented for transient simulations of TFET—based inverter and ring—oscillator circuits.
Yu, Tao Ph D. Massachusetts Institute of Technology. "InGaAs/GaAsSb quantum-well Tunnel-FETs for ultra-low power applications." Thesis, Massachusetts Institute of Technology, 2016. http://hdl.handle.net/1721.1/106101.
Повний текст джерелаCataloged from PDF version of thesis.
Includes bibliographical references.
The Tunnel-FET (TFET), where carrier injection is determined by gate-controlled tunneling from the source to the channel, has been attractive as one of the promising candidates for future ultra-low power applications. In this thesis, inline-TFETs with tunneling direction aligned to the gate electric field are designed, fabricated and analyzed based on InGaAs/GaAsSb material. Using ultrathin InGaAs/GaAsSb quantum-well (QW), the device fabrication technology was developed and the tunneling properties of two successive generations of QWTFETs were investigated. In the first generation QWTFETs, the limitation of gate oxide quality on InGaAs and parasitic thermal currents manifests itself in degraded subthreshold swing (SS) of 140 mV/dec, as well as strongly temperature dependent SS from 300 K to 77 K. The second generation QWTFETs with sub-nm InP cap between gate oxide and InGaAs channel and revised structure design has demonstrated improved SS of 87 mV/dec at 300 K and temperature independent SS below 140 K, indicating the achievable tunneling current steepness with the current device design. Physical modeling and quantum simulations based on the low temperature I-V characteristics were used to analyze the fundamental gate efficiency of the experimental QWTFETs in order to reveal the ultimate intrinsic tunneling steepness of the InGaAs/GaAsSb tunneling junction. The extracted gate efficiency around 55-64% is due to the coupling of the gate capacitance and tunneling junction capacitance and degrades dramatically the attainable SS in the QWTFET. On the other hand, the implied intrinsic tunneling steepness of the InGaA/GaAsSb is around 30 mV/dec, almost identical to previously reported non-abruptness of the conduction/valence band-edge into the bandgap. The result indicates the possibility of achieving SS as low as 38 mV/dec in QWTFETs by improving gate efficiency by up to 78% with proposed optimized parameters based on simulation results. Non-logic TFET-specific circuits are also explored to understand the advantage of TFETs in real-world applications. Due to the superior nonlinearity in the device I-V characteristics and gate-dependent negative-differential-resistance (NDR) under forward bias condition (VDS < 0), experimental and simulation results of QWTFET-based RF detector, oscillator and mixer have demonstrated the potential of QWTFET in these non-logic circuit applications, especially for ultralow standby power applications.
by Tao Yu.
Ph. D.
Cavalheiro, David. "Ultra-low power circuits based on tunnel FETs for energy harvesting applications." Doctoral thesis, Universitat Politècnica de Catalunya, 2017. http://hdl.handle.net/10803/406391.
Повний текст джерелаHa habido una tremenda evolución en la tecnología de circuitos integrados en las últimas décadas. Con el escalado de transistores de metal-óxido-semiconductor (CMOS), se han hecho posibles chips más rápidos, con menos consumo de energía y más complejos con menos área y esto ha posibilitado la existencia de los aparatos electrónicos que vemos en la actualidad. La creciente demanda de portabilidad implica que el consumo de energía es un indicador clave en el diseño analógico y digital. Mientras que el consumo de potencia dinámica disminuye cuadráticamente con la disminución de la tensión de fuente de alimentación, la potencia de fugas presenta una limitación debido a la pendiente sub-umbral inverso (sub-threshold slope, SS). Una reducción de la tensión de alimentación implica una consecuente reducción de tensión umbral a fin de mantener las prestaciones que, dado el SS fijo, causa un aumento exponencial de la corriente de fuga. Esto plantea una limitación en la reducción de consumo de energía que es inherente a los transistores convencionales basados en inyección de portadores termoiónicos (MOSFETS y FinFETs). En transistores termoiónicos la SS a temperatura ambiente está limitado a 60 mV / dec. Para eludir la limitación SS de transistores convencionales se requieren dispositivos con mecanismos diferentes de inyección de portadores. El transistor túnel de efecto campo (TFET) se presenta como la tecnología más prometedora debido a su mecanismo de inyección de portadores no térmico basado en el efecto Band-To-Band Tunneling (BTBT). Los TFETs se conocen como dispositivos de alta pendiente sub-umbral (SS <60 mV / dec a temperatura ambiente). Han sido ya demostradas ganancias de corriente elevadas (ION / IOFF> 10 ^ 5) en operación de baja tensión (sub-0,25 V) y una corriente de fugas extremadamente bajo, colocando los TFETs como serios candidatos para aplicaciones de circuitos eficientes de ultra-baja potencia y energía. Los TFETs se han explorado sobre todo en circuitos digitales y aplicaciones. En esta tesis, el uso de TFETs se explora como una tecnología alternativa también para circuitos de potencia y de conversión de tensión ultra-bajas, adecuada para fuentes de energía del ambiente, usualmente muy limitadas en magnitud. Debido a que los TFETs están diseñados como diodos p-i-n en polarización inversa (hay diferente tipo de dopaje en las regiones fuente / drenador), sus características eléctricas particulares en condiciones de polarización inversa requieren cambios en las topologías de circuito convencionales. En la tesis, rectificadores, bombas de carga y circuitos de gestión de la energía (PMC) con TFETs se diseñan y analizan, realizando una evaluación de su rendimiento con la propuesta de nuevas topologías que extienden el rango de tensión y potencia de operación en comparación con tecnologías y topologías de circuitos actuales. Se proponen PMCs basados en TFET para fuentes de RF y DC y se identifican las limitaciones (con soluciones) de la utilización de TFETs en convertidores elevadores convencionales basados en inductores.
Hi ha hagut una tremenda evolució en la tecnologia de circuits integrats en les últimes dècades. Amb l'escalat de transistors de metall-òxid-semiconductor (CMOS), s'han fet possibles xips més ràpids, amb menys consum d'energia i més complexos amb menys àrea i això ha possibilitat l'existència dels aparells electrònics que veiem en l'actualitat. La creixent demanda de portabilitat implica que el consum d'energia és un indicador clau en el disseny analògic i digital. Mentre que el consum de potència dinàmica disminueix quadràticament amb la disminució de la tensió de font d'alimentació, la potència de fuites presenta una limitació a causa del pendent sub-llindar invers (sub-threshold slope, SS). Una reducció de la tensió d'alimentació implica una conseqüent reducció de tensió llindar a fi de mantenir les prestacions que, donat el SS fix, causa un augment exponencial del corrent de fuita. Això planteja una limitació en la reducció de consum d'energia que és inherent als transistors convencionals basats en injecció de portadors termoiònics (MOSFETS i FinFETs). En transistors termoiònics la SS a temperatura ambient està limitat a 60 mV / dec. Per eludir la limitació SS de transistors convencionals es requereixen dispositius amb mecanismes diferents d'injecció de portadors. El transistor túnel d'efecte camp (TFET) es presenta com la tecnologia més prometedora a causa del seu mecanisme d'injecció de portadors no tèrmic basat en l'efecte Band-To-Band Tunneling (BTBT). Els TFETs es coneixen com a dispositius d'alt pendent sots-llindar (SS <60 mV / dec a temperatura ambient). Han estat ja demostrats guanys de corrent gran (ION / IOFF> 10 ^ 5) en operació de baixa tensió (sub-0,25 V) i un corrent de fuites extremadament baix, col·locant els TFETs com a seriosos candidats per a aplicacions de circuits eficients d'ultra-baixa potència i energia. Els TFETs s'han explorat sobretot en circuits digitals i aplicacions. En aquesta tesi, l'ús de TFETs s'explora com una tecnologia alternativa també per a circuits de potència i de conversió de tensió ultra-baixes, adequada per a fonts d'energia de l'ambient, usualment molt limitades en magnitud. Degut a que els TFETs estan dissenyats com díodes p-i-n en polarització inversa (hi ha diferent tipus de dopatge en les regions font / drenador), les seves característiques elèctriques particulars en condicions de polarització inversa requereixen canvis en les topologies de circuit convencionals. En la tesi, rectificadors, bombes de càrrega i circuits de gestió de l'energia (PMC) amb TFETs es dissenyen i analitzen, realitzant una avaluació del seu rendiment amb la proposta de noves topologies que estenen el rang de tensió i potència d'operació en comparació amb tecnologies i topologies de circuits actuals. Es proposen PMCs basats en TFET per fonts de RF i DC i s'identifiquen les limitacions (amb solucions) de la utilització de TFETs en convertidors elevadors convencionals basats en inductors.
Richter, Simon [Verfasser]. "Strained silicon and silicon-germanium nanowire tunnel FETs and inverters / Simon Richter." Aachen : Hochschulbibliothek der Rheinisch-Westfälischen Technischen Hochschule Aachen, 2014. http://d-nb.info/1059533189/34.
Повний текст джерелаNarimani, Keyvan [Verfasser], Joachim [Akademischer Betreuer] Knoch, and Siegfried [Akademischer Betreuer] Mantl. "Silicon tunnel FETs for digital and analogue applications / Keyvan Narimani ; Joachim Knoch, Siegfried Mantl." Aachen : Universitätsbibliothek der RWTH Aachen, 2018. http://d-nb.info/121148758X/34.
Повний текст джерелаNarimani, Keyvan Verfasser], Joachim [Akademischer Betreuer] [Knoch, and Siegfried [Akademischer Betreuer] Mantl. "Silicon tunnel FETs for digital and analogue applications / Keyvan Narimani ; Joachim Knoch, Siegfried Mantl." Aachen : Universitätsbibliothek der RWTH Aachen, 2018. http://d-nb.info/121148758X/34.
Повний текст джерелаBlaeser, Sebastian Verfasser], Siegfried [Akademischer Betreuer] [Mantl, and Christoph [Akademischer Betreuer] Stampfer. "Strained Silicon-Germanium/Silicon Heterostructure Tunnel FETs for Low Power Applications / Sebastian Blaeser ; Siegfried Mantl, Christoph Stampfer." Aachen : Universitätsbibliothek der RWTH Aachen, 2016. http://d-nb.info/1126646431/34.
Повний текст джерелаRiederer, Felix [Verfasser]. "Skalierung von Tripel & Multi Backgate Bauteilen für die Herstellung von Tunnel- & Superlattice-FETs / Felix Riederer." München : Verlag Dr. Hut, 2018. http://d-nb.info/1164293710/34.
Повний текст джерелаBlaeser, Sebastian [Verfasser], Siegfried [Akademischer Betreuer] Mantl, and Christoph [Akademischer Betreuer] Stampfer. "Strained Silicon-Germanium/Silicon Heterostructure Tunnel FETs for Low Power Applications / Sebastian Blaeser ; Siegfried Mantl, Christoph Stampfer." Aachen : Universitätsbibliothek der RWTH Aachen, 2016. http://d-nb.info/1126646431/34.
Повний текст джерелаLuong, Gia Vinh Verfasser], Joachim [Akademischer Betreuer] [Knoch, and Siegfried [Akademischer Betreuer] Mantl. "Gate-All-Around Silicon Nanowire Tunnel FETs for Low Power Applications / Gia Vinh Luong ; Joachim Knoch, Siegfried Mantl." Aachen : Universitätsbibliothek der RWTH Aachen, 2017. http://d-nb.info/1162559780/34.
Повний текст джерелаSterkel, Martin. "Ultra-Kurzkanal Tunnel-Feldeffekt-Transistoren auf Silizium- und SOI-Substraten." Göttingen Cuvillier, 2008. http://d-nb.info/990746445/04.
Повний текст джерелаRamesh, Anisha. "TUNNELING BASED QUANTUM FUNCTIONAL DEVICES AND CIRCUITS FOR LOW POWER VLSI DESIGN." The Ohio State University, 2012. http://rave.ohiolink.edu/etdc/view?acc_num=osu1338315073.
Повний текст джерелаHaffner, Thibault. "Elaboration et intégration de nanofils GeSn pour la réalisation de dispositifs nanoélectroniques basse consommation." Thesis, Université Grenoble Alpes, 2020. https://tel.archives-ouvertes.fr/tel-03066536.
Повний текст джерелаSince the 1960's, technological development has been mainly driven by the miniaturization of components and follows the famous Moore's law. Indeed, miniaturization brought many advantages at the start. Lower switching time, more compact systems, lower supply voltage, and therefore, transistors consuming less, etc. However, this approach has started to falter in recent years. Indeed, the limits of miniaturization began to appear and the overall power consumption of the circuits began to increase which limits the realization of the systems. It then becomes necessary to develop low-consumption components, such as tunnel effect transistors. These transistors have, to date, a major defect which is their currents in the on state, much weaker than the MOSFETs. This current depends mainly on the architecture of the transistor as well as on the gap width of the source material.In this thesis, we propose to develop and study nanowires and heterostructures based on the germanium-tin alloy. The $ Ge_{1-x}Sn_x $ is an alloy of column IV which has a very small gap, less than 0.66 eV with the particularity of passing from an indirect gap to a direct gap from a concentration 10% of tin, which is favorable to tunnel effect transistors. Nanowires were developed by chemical vapor deposition using the vapor-liquid-solid mechanism and physicochemical analyzes such as X-ray spectroscopy and nano-Auger spectroscopy were used to characterize them. Hypotheses have been put forward in order to understand the mechanisms involved in the growth of GeSn nanowires and to better control their development. Axial heterostructures which will serve as basic materials for the realization of tunnel effect transistors are presented and detailed. We then present the study of the GeSn/dielectric interface in order to improve the performance of MOS capacities on GeSn, and therefore, to improve nanoelectronic devices. Chemical treatments were applied to the GeSn surface, and XPS and pAR-XPS analyzes were conducted to determine the effectiveness of the treatments. In order to improve the performance of the MOS capacities, we deposited a stack formed of an interfacial layer followed by a dielectric with high permittivity, such as $ HfO_2$, in order to obtain a low interface trap density. Finally, the integration and study of tunnel effect transistors based on heterostructures are presented. We first present the technological development stages developed in order to produce nanoelectronic devices. The doping levels of the heterostructures were evaluated by means of resistivity measurements. The performances of tunnel effect transistors were evaluated using electrical measurements and were compared with the current state of the art
Brouzet, Virginie. "Réalisation et étude des propriétés électriques d'un transistor à effet tunnel 'T-FET' à nanofil Si/SiGe." Thesis, Université Grenoble Alpes (ComUE), 2015. http://www.theses.fr/2015GREAT120/document.
Повний текст джерелаThe connected objects demand in our society is very important , given the successfull smartphone market. These newtechnological objects have the advantage to combine several functions in one ultra compact object. This diversity is possibledue to the advent of system-on-chip (SoC) and the components scaling down. The SoCs are into the More than Mooreapproach and require a large chips area, which can be reduced by the use of "More Moore" approach which was widelyused in recent years to scale down the transistors. However, this approach tends to physical limitations since the drasticscaling down of the MOSFETs ("Metal Oxide Field Efect Transistor Semicondutor") can not be continued in the future. Inaddition, the nanoŰMOSFET have parasitic efects, related to short-channel efects and a low heating dissipation. Theshort channel efects can be minimized thanks to new architectures, such as the use of nanowires, which enable a gate allaround of the channel. But the power consumption problem still drag on the transition to the next technology node and theaddition of new functions in mobile devices. Indeed, the MOSFETŠs consumed power increases with each new generation,which is mainly due to the static power increase of these transistors. To reduce it, the scientiĄc community has proposedseveral solutions, and one of the most promising is a tunnel efect transistor (TFET). Because this device exhibit lessshort-channel efects compared to the conventional MOSFET, it can operate at low drain voltages and their subthresholdslope could be lower than 60 mV/dec. The thesis aims are to fabricate and characterize tunneling transistors based onsingle silicon nanowire and silicon germanium. We will present the growth and integration of pŰiŰn nanowires TFET. Thenwe investigated the inĆuence of some parameters on the electrical performance of these transistors, in particular, the efectof the source doping level and the electrostatic gate control will be discussed. In the next part, the increase of TFETsperformance will be shown thanks to the small band-gap semiconductor use. Indeed, we insert germanium in the silicon dieto reduce the bandgap and keep a material compatible with the CMOS manufacturing. A band to band tunneling modelwas used to calculate the device current, based on the model Klaassen. Electrical measurements will be compared to thesimulated results, in order to extract the B parameter of tunnel transition for each materials used. Finally we will presentthe possible performance improvements thanks to the vertical nanowires integration
Fu, Yen-Chun. "Realisation of III-V Tunnel-FET with in-situ ultimate scaled gate stack for high performance power efficient CMOS." Thesis, University of Glasgow, 2018. http://theses.gla.ac.uk/30588/.
Повний текст джерелаWan, Jing. "Dispositifs innovants à pente sous le seuil abrupte : du TEFT au Z²-FET." Phd thesis, Université de Grenoble, 2012. http://tel.archives-ouvertes.fr/tel-00845632.
Повний текст джерелаRevelant, Alberto. "Modélisation, simulation et caractérisation de dispositifs TFET pour l'électronique à basse puissance." Thesis, Grenoble, 2014. http://www.theses.fr/2014GRENT022.
Повний текст джерелаIn the last years a significant effort has been spent by the microelectronic industry to reducethe chip power consumption of the electronic systems since the latter is becoming a majorlimitation to CMOS technology scaling.Many strategies can be adopted to reduce the power consumption. They range from thesystem to the electron device level. In the last years Tunnel Field Effect Transistors (TFET)have imposed as possible candidate devices for replacing the convential MOSFET in ultra lowpower application at supply voltages VDD < 0.5V. TFET operation is based on a Band-to-BandTunneling (BtBT) mechanism of carrier injection in the channel and they represent a disruptiverevolutionary device concept.This thesis investigates TFET modeling and simulation, a very challenging topic becauseof the difficulties in modeling BtBT accurately. We present a modified Multi Subband MonteCarlo (MSMC) that has been adapted for the simulation of Planar Ultra Thin Body (UTB)Fully Depleted Semiconductor on Insulator (FD-ScOI) homo- and hetero-junction TFET implementedwith arbitrary semiconductor materials. The model accounts for carrier quantizationwith a heuristic but accurate quantum correction validated by means of comparison with fullquantum model and experimental results.The MSMC model has been used to simulate and assess the performance of idealized homoandhetero-junction TFETs implemented in Si, SiGe alloys or InGaAs compounds.In the second part of the thesis we discuss the characterization of TFETs at low temperature.Si and SiGe homo- and hetero-junction TFETs fabricated by CEA-LETI (Grenoble,France) are considered with the objective to identify the possible presence of alternative injectionmechanisms such as Trap Assisted Tunneling
Negli ultimi anni uno sforzo significativo `e stato speso dall’industria microelettronica per ridurreil consumo di potenza da parte dei sistemi microelettronici. Esso infatti sta diventando unadelle limitazioni pi`u significative per lo scaling geometrico della tecnologia CMOS.Diverse strategie possono essere adottate per ridurre il consumo di potenza considerando ilsistema microelettronico nella sua totalit`a e scendendo fino a giungere all’ottimizzazione delsingolo dispositivo nano-elettronico. Negli ultimi anni il transistore Tunnel FET (TFET) si`e imposto come un possibile candidato per rimpiazzare, in applicazioni a consumo di potenzaestremamente basso con tensioni di alimentazione inferiori a 0.5V, i transistori convenzionaliMOSFET. Il funzionamento del TFET si basa sul meccanismo di iniezione purament quantisticodel Tunneling da banda a banda (BtBT) e che dovrebbe permettere una significativa riduzionedella potenza dissipata. Il BtBT nei dispositivi convenzionali `e un effetto parassita, nel TFETinvece esso `e utilizzato per poter ottenere significativi miglioramenti delle performance sottosogliae pertanto esso rappresenta una nuova concezione di dispositivo molto innovativa erivoluzionaria.Questa tesi analizza la modellizazione e la simulazione del TFET. Questi sono argomenti moltocomplessi vista la difficolt`a che si hanno nel modellare accuratamente il BtBT. In questo lavoroviene presentata una versione modificata del modello di trasporto Multi Subband Monte Carlo(MSMC) adattato per la simulazione di dispositivi TFET planari Ultra Thin Body Fully DepletedSilicon on Insulator (UTB FD-SOI), implementati con un canale composto da un unicosemiconduttore (omogiunzione) o con differenti materiali semiconduttori (eterogiunzione). Ilmodello proposto tiene il conto l’effetto di quantizzazione dovuto al confinamento dei portatoridi carica, con un’euristico ma accurato sistema di correzione. Tale modello `e stato poivalidato tramite una comparazione con altri modelli completamente quantistici e con risultatisperimentali.Superata la fase di validazione il modello MSMC `e utilizzato per simulare e verificare le performancedi dispositivi TFET implementati come omo o eterogiunzione in Silicio, leghe SiGe,o composti semiconduttori InGaAs.Nella seconda parte della tesi viene illustrato un lavoro di caratterizazione di TFET planari abassa temperatura (fino a 77K). Sono stati misurati dispositivi in Si e SiGe a omo o eterogiuzioneprodotti nella camera bianca del centro di ricerca francese CEA-LETI di Grenoble. Tramite talimisure `e stato possibile identificare la probabile presenza di meccanismi di iniezione alternativial BtBT come il Tunneling assistito da trappole (TAT) dimostrando come questo effetto `e,con ogni probabilit`a, la causa delle scarse performance in sottosoglia dei dispositivi TFETsperimentali a temperatura ambiente
Viereck, Cornelius. "A computer-controlled passive multi-harmonic tuner used to optimise a power FET up to the third harmonic." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1999. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape8/PQDD_0006/MQ42929.pdf.
Повний текст джерелаDiaz, llorente Carlos. "Caractérisation de transistors à effet tunnel fabriqués par un processus basse température et des architectures innovantes de TFETs pour l’intégration 3D." Thesis, Université Grenoble Alpes (ComUE), 2018. http://www.theses.fr/2018GREAT096/document.
Повний текст джерелаThis thesis presents a study of FDSOI Tunnel FETs (TFETs) from planar to trigate/nanowire structures. For the first time we report functional “Low-Temperature” (LT) TFETs fabricated with low-thermal budget (630°C) process flow, specifically designed for top tier devices in 3D sequential integration. “Dual IDVDS” method confirms that these devices are real TFETs and not Schottky FETs. Electrical characterization shows that LT TFETs performance is comparable with “High-Temperature” (HT) TFETs (1050°C). However, LT TFETs exhibit ON-current enhancement, OFF-current degradation and VTH shift with respect to HT TFETs that cannot be explained via BTBT mechanism. Charge pumping measurements reveal a higher defect density at the top silicon/oxide interface for geometries with narrow widths in LT than HT TFETs. In addition, low-frequency noise analyses shed some light on the nature of these defects. In LT TFETs, we determined a non-uniform distribution of defects at the top surface and also at the tunneling junction that causes trap-assisted tunneling (TAT). TAT is responsible of the current generation that degrades the subthreshold swing. This indicates the tight requirements for quality epitaxy growth and junction optimization in TFETs. Finally, we proposed novel TFET architectures. TCAD study shows that the extension of the source into the body region provides vertical BTBT and a larger tunneling surface. Ultra-thin heavily doped boron layers could allow the possibility to obtain simultaneously a good ON-current and sub-thermal subthreshold slope in TFETs
Wang, Chiu-Ting, and 王秋婷. "Performance Enhancement of III-V Tunnel FETs considering Line Tunneling and Non-uniform Channel Thickness." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/wh3py3.
Повний текст джерела國立中央大學
電機工程學系
106
Power scaling is one of the major challenges in modern CMOS technology for ultra-low power applications, such as emerging IoT (Internet of Things) technologies and wearable devices. Lowering the supply voltage (Vdd) is an efficient technique to achieve ultra-low power consumption for circuits. Device with steep subthreshold slope is essential in order to achieve energy-efficient switching and low leakage power as supply voltage scaling. Conventional MOSFET exhibits the lower-bound limitation of subthreshold swing (SS) which is about 60 mV/dec at room temperature. Tunneling field-effect transistors (TFETs) have been actively explored to tackle this problem and provide steep subthreshold slope below 60mV/dec [1]. Tunnel field-effect transistors (Tunnel FETs, TFETs), which have a subthreshold swing below 60 mV/decade, were proposed as an alternative to conventional MOSFETs in response to the quest for lower power consumption integrated circuits. III-V channel materials become promising materials for TFETs due to their lower bandgap which leads to better tunneling efficiency. However, III-V TFETs still show lower drive current than conventional Si MOSFET at high supply voltage due to their low density of states. This work aims at structure optimization of III-V TFETs for improving the drive current based on InGaAs/GaAsSb heterostructures. The InGaAs/GaAsSb TFET simulation framework with TCAD tool was established in this work. First, a novel TFET structure with line tunneling was proposed and analyzed comprehensively. By inserting an expitaxial layer between source and gate dielectric regions, TFET consists both lateral point tunneling and line tunneling. Compared with the conventional p-i-n TFET with point tunneling only. The on current of TFETs with epi layer and line tunneling can be further increased due to the increased tunneling area. We analyze the impact of device design on the TFET with epi layer comprehensively. The impacts of epi layer thickness (Tepi), gate-to-source overlap length (Lovs), source thickness, and gate-to-drain underlap length (Lund) on the Id-Vg characteristics of heterojunction III-V TFETs were analyzed comprehensively in this work. This study provides the device design guidelines for performance enhancement of TFETs with epi layer. Compared with the conventional TFET without epitaxial layer, the heterojunction TFET with epitaxial layer and gate to source overlap length = 10 nm shows 3.3 times higher on currents and Ion = 406 (μA/μm) at Vdd = 0.5V. Sencond, GaAs1-xSbx/In1-yGayAs heterojunction TFETs with bandgap engineering by using non-uniform channel thickness (Tch) are analyzed comprehensively for improving Ion and suppressing ambipolar leakage. Quantum confinement induced bandgap widening as a function of Tch is considered. We analyze the impact of source doping concentration (Ns), drain doping comcentration (Nd), and channel thickness (Tch) on the Id-Vg characteristics of uniform Tch Type II and Type III heterojunction TFETs. The impact of source/channel junction thickness (Ts), drain/channel junction thickness (Td), and thicker channel length (LW) on the Id-Vg characteristics of non-uniform type-II TFETs are also analyzed comprehensively. Finally, the Ioff of type-III non-uniform TFETs can be further reduced by using gate-to-drain underlap design. The Ioff can be improved by 70% as Lund changes from 0 nm to 8 nm.
Palle, Dharmendar Reddy. "Modeling of graphene-based FETs for low power digital logic and radio frequency applications." 2013. http://hdl.handle.net/2152/22008.
Повний текст джерелаtext
Wang, Yu-Wei, and 王佑瑋. "Theoretical Investigation of Optimized Nanowire Diameter and Short Channel Effects for Gate-All-Around III-V Tunnel FETs." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/44732999900811713543.
Повний текст джерела國立交通大學
電子研究所
105
This thesis investigates the diameter dependence for III-V gate-all-around homojunction and heterojunction TFET using TCAD numerical simulation. The optimized diameter has been shown due to the counterbalance of the gate control and the quantum confinement effect. In addition, model calculation for the homojunction TFET is proposed and verified with TCAD numerical simulation. Source and drain depletion is very important in modeling of TFET. The diameter dependence by model calculation also shows the same trend with TCAD numerical simulation. Finally, the short channel effect of TFET has been compared with MOSFET with considering the source-to-drain tunneling current for MOSFET. Our results indicate the scalability of MOSFET is worse than TFET due to the lowering of the tunneling barrier and the tunneling length with decreasing the gate length.
Lin, Po-Shao, and 林柏劭. "A Study on Performance Evaluation of Fin Epitaxial Tunnel Layer Tunnel FET and Performance Improvement of n-type Epitaxial Tunnel Layer Tunnel FET." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/tf69y7.
Повний текст джерела國立交通大學
電子研究所
105
Epitaxial tunnel layer (ETL) tunnel FET (TFET) has been considered to be one of the promising devices in ultra-low power applications. In this study, the performance of the planar ETL TFET and fin ETL TFET for both n-type and p-type, respectively, are evaluated by Sentaurus TCAD simulation. In addition, TFET that is doped by solid-phase diffusion (SPD) instead of ions implantation was proposed and fabricated. In the previous research, the n-type and p-type ETL TFET show the steep subthreshold swing and high on-state current in the planar structure by TCAD simulation. However, the improvement of the fin structure is not significant in the n-type TFETs (nTFET) in this study. The stronger electrostatic control caused by the fin structure would lead to the Si-to-Ge and Si-to-Si tunneling leakage current at low gate bias. The increased off-state current degrades the subthreshold slope of the fin nTFETand causes the on-state current of the planar nTFET 35% higher than that of the fin nTFET after shifting to Ioff = 1 pA/μm at Vg = 0 V. But the degradation of subthreshold swing is not observed in p-type fin TFET (fin pTFET) because there is only one tunneling path which is Ge-to-Si tunneling at the subthreshold region. Consequently, the planar pTFET shows 40% lower on-state current than the fin pTFET. In order to improve the epitaxial quality of Ge ETL, SPD was applied to form a defect-free p+ junction in the SPD TFET. The SPD TFET was fabricated and discussed for both n-type and p-type. The severe reverse leakage current of nTFET operation in previous research has been suppressed from 10-8 A/μm to 10-12 A/μm successfully though the Ge ETL is non-uniform. But the SPD nTFET still suffers from the low on-state current because of the insufficient concentration of the p+ junction and the poor Ge ETL. The temperature dependence of the on-state current shows that the transport mechanism in the SPD nTFET is dominated by trap assisted tunneling (TAT). Though fin structure improves the on-state current of the fin pTFET, it degrades the subthreshold swing and the on-state current of the fin nTFET as well. The planar nTFET is preferred to be applied in low-power circuits optimized for n-type operation, and the fin pTFET is preferred in the circuits optimized for p-type operation. In the SPD TFET, theconcentration of the p+ junction should be increased to improve the efficiency of band to band tunneling (BTBT). Besides, an ultra-thin uniform Ge layer is necessary to suppress the TAT current. If the above suggestions could be achieved, the performance of the SPD TFET will improve further more.
Wang, Pei-Yu, and 王培宇. "A Study on Tunnel FET with Epitaxial Tunnel Layer Structure." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/90836541544090748423.
Повний текст джерела國立交通大學
電子工程學系 電子研究所
104
In this dissertation, tunnel field-effect-transistor (TFET) utilizing band-to-band tunneling (BTBT) as the operation mechanism is studied. To realize the basic characteristics and the design issues for the novel device, the effects of the source junction profiles and the trap-assisted tunneling (TAT) on the bulk TFET are investigated. To further improve the TFET performance, a CMOS process compatible TFET with epitaxial tunnel layer (ETL) structure is proposed. Various device parameters of complementary ETL TFETs (CTFETs) are studied and discussed in detail by the TCAD simulation. The inverter characteristics based on the proposed CTFETs are also presented and compared with the inverter based on complementary fully depleted silicon-on-insulator MOSFET (CMOSFETs). Moreover, complementary Ge ETL TFETs are also fabricated and discussed. The effects of source junction profiles and the TAT on the bulk TFET are firstly investigated. By comparing with different source junction profiles, it indicates that the doping concentrations and profiles near the gate dielectric interface have the largest influence on TFET characteristics. The tunneling efficiency and orientation are also affected by the source junction profiles. Because the defects located within the depletion region have the largest effect on the device characteristics, the defects located near the gate interface and the junction edge degrade the TFET characteristics the most. After realizing the basic characteristics and design issues of TFET devices, a CMOS process compatible TFET with ETL structure is proposed to improve the TFET performance. Considering the process integration and material properties, Ge/Si hetero-material system is used to demonstrate the concept of the ETL TFET. Excellent device performance of Ge ETL pTFET is achieved by the structural engineering and the ETL band engineering. To achieve the configuration of complementary TFETs, Ge ETL nTFET is investigated. Because the Ge/Si hetero-material system with the valence band offset is applied, the concept of the suppression of the low electric field BTBT (LE BTBT) can apply on the Ge ETL nTFET. The LE BTBT suppression concept is illustrated and discussed by the TCAD simulation. The S.S. characteristic of Ge ETL nTFET can be further improved. The TFET-based inverter are also studied and compared with the MOSFET-based inverter. Better speed performance can be achieved as the VDD is below 0.4 V. However, high power consumption on the TFET-based inverter is observed due to the large parasitic capacitance of CTFETs. According to the power-delay analysis, TFET-based inverter exhibits not only better performance but also less power consumption as it is operated at 0.2 V. Finally, complementary Ge ETL TFETs are fabricated and discussed. The fabricated Ge ETL pTFET exhibits high tunneling current, ultralow OFF-state current, and good average subthreshold swing (S.S. ~100 mV/decade up to 10 nA / μm). The gate-to-source (CGS) capacitance is also investigated. The origin and the possible influence of the CGS are also discussed.
Teng, Chien-Hong, and 鄧建鴻. "TCAD Design of InAs Gate-All-Around Nanowire Tunnel FET Structures." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/g73uyt.
Повний текст джерела國立臺灣大學
電子工程學研究所
105
The electrical characteristics of InAs-Si heterojunction GAA NW TFET are simulated using Sentaurus TCAD produced by Synopsys. Results show that InAs-Si heterojunction can enlarge the on-state current compared with Si homo-junction and GAA structure can improve the subthreshold slope compared with single gate structure. The reasons are that the tunnel barrier width of InAs-Si heterojunction is smaller than Si homo-junction and the GAA structure has better gate control than single gate structure. Besides, the diameter of nanowire scarcely affects the performance of device due to the tunneling mainly occurring at nanowire surface. To further improve the subthreshold slope, we introduce Si pocket structure. This structure can further decrease the subthreshold slope by Si to Si tunneling mechanism. On the other hand, to further increase the on-state current, we introduce core shell structure. This structure can further increase on-state current because it enlarges the tunnel area. However, the on-state current does not increase proportional to the core length due to the tunnel barrier width in the direction across channel increases as the core length increasing.
Lin, Yu-cheng, and 林鈺城. "Investigation of Drain Lapping Effect on Tunnel-FET With Poly-Si Channel Film." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/60553590438101130651.
Повний текст джерела國立中山大學
電機工程學系研究所
104
The purpose of the research was to study the drain lapping effect of tunneling field-effect transistors (TFETs) with polycrystalline-silicon (poly-Si) channel. The transfer characteristics of source to gate overlap 2m and different drain to gate lapping length indicated that overlap is not sensitive to overlap length and measurement temperature. For this reason, the TFETs with poly-Si channel device have strong immunity against the short channel effect. When the tunneling field-effect transistors reverse turn on, the carrier transport behavior starts with tunneling of channel/drain junction. However, the underlap region of drain to gate builds the intrinsic depletion region between the channel and drain. The underlap structure can reduce the ambipolar current of tunneling field-effect transistors. There are many traps at the poly-Si intrinsic depletion region which make the carrier mobility degradation. By the higher measurement temperature, the transfer characteristics indicated that there is another reason to lead the current decrease obviously. The recombination current is significant effect of this case. The TFETs with poly-Si channel with lapping structure have potential to study, in order to find the best carrier transport behavior.
Chang, Kang, and 張綱. "Impacts of Ammonia Plasma Treatment on Tunnel-FET With Poly-Si Channel Film." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/13814733054789780118.
Повний текст джерела國立中山大學
電機工程學系研究所
104
To obtain the faster operation speed and lower cost in fabrication,Channel length is continuously scaling down. However, negligible short channel effect(SCE) are observed and lead to increased of leakage current and reduce gate control ability. Tunnel Field-effect transistor is proposed to replace MOSFET in future. Unlike traditional inversion mode transistors, band-to-band tunneling is the mainly carrier transport mechanism. The subthreshold swing(S.S.) of T-FET can overcome the limitation of 60mV/dec of MOSFET.T-FET can also suppressed the leakage current by the high energy barrier and perform a better SCE immunity. T-FET is considered a promising candidate for next generation low power applications. This thesis is mainly study for T-FET with Polycrystalline-Si channel, the channel film and the surface oxide interface of channel are rich with defects, lots of dangling bonds and strain bonds are localize in the defect. Both of them would degrade S.S. and increase leakage current. In this thesis,NH3 plasma is used to passivate the trap state. Both grain boundary trap state and interface trap can be effectively reduce by NH3 surface plasma treatment. Significant performance improvement has been observed after NH3 plasma surface treatment. Moreover, T-FET which passivated by NH3 plasma show lower degradation after positive bias stress for 1000 sec, it indicate that TFET can perform higher reliability by NH3 plasma surface treatment. As a result, Poly-Si T-FET with NH3 plasma surface treatment can obtain better propertied and suitable to be used in LCD, three Dimensional-integrated Circuit or other consumer electronic.
Hsu, Chie-Wei, and 徐誌緯. "Simulation and Investigation of Random Variations for III-V Broken-Gap Heterojunction Tunnel FET." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/75704934585062201395.
Повний текст джерела國立交通大學
電子工程學系 電子研究所
103
This thesis compares and investigates the impacts of metal-gate work-function variation (WFV) and source random-dopant-fluctuation (source RDF) for III-V broken-gap heterojunction TFET (HTFET), homojunction TFET and FinFET devices using 3-D atomistic Monte Carlo simulation. Our study indicates that the HTFET exhibts higher susceptibility to WFV near OFF state due to its broken-gap nature. For ON current variation, both the HTFET and homojunction TFET show better immunity to WFV than the III-V FinFET. Device design using source-side underlap to mitigate the impact of WFV on HTFET is also assessed. Under source RDF, the HTFET exhibits larger current variations than the homojunction TFET and FinFET. The impact of source RDF increases with decreasing source doping for HTFET near OFF state.
Gupta, Akancha, and 古璦卡. "Design of Low Voltage Vertical Channel-Tunnel FET (VC-TFET) Using Ge/SiGe Materials." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/k3s7eq.
Повний текст джерела國立交通大學
電機資訊國際學程
107
Abstract In this thesis, tunneling field-effect-transistor (TFET) based on the mechanism of band-to-band tunneling (BTBT), has been studied extensively. TFET is considered as a potential low voltage and low power transistors in certain applications for next generation transistors. Since the operating mechanism of TFET and MOSFET are different, hence, TFET is able to avoid many of the reliability and short channel issues. TFFT has the capability of achieving the sub-threshold slope of less than 60 mV/decade and small leakage current. These characteristics allow the voltage scaling and also reduce the power consumption for low power application. TFET still has some issues such as low on-state drive current value and larger gate-to-drain capacitance. To further improve the TFET performance, a novel TFET device with vertical source-channel overlap region is proposed. Ge and SiGe materials are used for the structural modelling of VC-TFET. Various design parameters of vertical channel Tunnel FET (VC-TFET) are discussed and studied in detail by using the TCAD simulation. By modulating the important device parameters to optimize the device, the electrical characteristics with improved ON-state drive current, reduced OFF-state leakage current and steeper sub-threshold swing have been achieved. After introducing the fundamental characteristics and device design concept of TFET device, the capacitance characteristics and inverter characteristics of the VC-TFET are also discussed in this work. Another critical issue is large gate-to-drain capacitance, Cgd in TFET, which can degrade the circuit delay. The proposed vertical channel TFET device design can reduce the Cgd value which result in lower circuit delay. Novel SRAM circuit topologies based on the proposed VC-TFET device are also proposed and discussed extensively. Better static noise margin can be achieved for lower VDD value. The proposed SRAM topologies based on VC-TFET device design give better noise-margin as compared to the conventional CMOS SRAM. These results show that the proposed VC-TFET is a potential device design for low voltage and low power applications.
Lee, Ko-Chun, and 李克駿. "Investigation and Comparison of Important Analog Figures of Merit for Tunnel FET and FinFET Considering Random Variations." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/01098490544975302839.
Повний текст джерела國立交通大學
電子工程學系 電子研究所
102
This thesis investigates and compares the impacts of metal-gate work function variation (WFV) and fin line edge roughness (fin LER) on the important analog FOMs (figures of merit) for TFET and FinFET devices using atomistic TCAD simulations. Our study indicates that under similar devices structure and comparable IOFF, the variability comparison between TFET and FinFET may yield different results depending on the dominant variation source for a given analog FOM. Under WFV, TFET exhibits better immunity to WFV than FinFET regarding gm/ID, Rout and intrinsic gain. For fT, however, the comparison result depends on drain bias. Under fin LER, TFET exhibits comparable immunity with FinFET in terms of gm/ID, Rout and intrinsic gain. However, TFET shows worse gm and fT immunity to fin LER than FinFET.
Chen, Yin-Nien, and 陳盈年. "Design and Analysis of Nanoscale FinFET and Tunnel FET Devices for Ultra-Low-Power SRAM, Logic and Analog Applications." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/03420513770720030664.
Повний текст джерела國立交通大學
電子工程學系 電子研究所
104
The goal of this dissertation is to provide an extensive assessment of nanoscale FinFET and TFET devices for ultra-low-power application in SRAM, logic and analog. Device-circuit interactions and co-optimizations are considered to demonstrate the advantages and concerns of these emerging devices based circuits from both the device and circuit point of view. Through our analysis, impacts of device characteristics and low-VDD operation on the leakage/delay and stability/performance of logic circuits and SRAMs, on the power/performance of analog circuits are evaluated to offer insights for both our proposed innovative circuit designs and for future low-voltage circuit designs. With superior electrostatic integrity and immune to random dopant fluctuation, FinFET device serves a promising role to replace conventional bulk MOSFET device. In addition, the possible adoption of the independent-gate control facilitates FinFET device characteristics and circuit functions. We extensively examine the stability and performance of our proposed Independently-controlled-Gate (IG) 7T FinFET SRAM cell with the conventional 6T FinFET SRAM cell and IG 6T Column-Decoupled FinFET SRAM cell. Through our analysis, our proposed IG 7T FinFET SRAM cell which exploits the independently-controlled-gate (IG) FinFET devices for reading transistor to decouple read/write paths and for access transistors to form cross-point structure provides comparable Write SNM (WSNM) and significant improvement in Read SNM (RSNM) and Half-Select SNM (HSSNM). In addition, with the 3D atomistic TCAD simulator generated Fin Line-Edge-Roughness (Fin LER) pattern, the impacts of the intrinsic device variability on the cell Read stability and Read Performance are extensively investigated. The results indicate that although the variability of independently-controlled-gate device is slightly larger compared to tied-gate device, our proposed cell provides the best μ/σ in RSNM and no Read failure events happened while other two counterparts encounter severe Read failure events due to leakage current from unselected cells flipping the storage data, revealing that our proposed cell is suitable for robust low Vmin SRAM application. Utilizing band-to-band tunneling as the major transport mechanism, Tunnel FET (TFET) device with capability to surmount the thermionic limitation and to provide superior switching characteristics is regarded as the potential candidate for ultra-low voltage digital applications. Through our comprehensive analysis of the TFET device characteristics, it is found that the pronounced Miller capacitance (CGD) in TFET device undermines the steep-slope advantages and degrades both the switching delay and switching energy. The impacts of several device designs including the Dual Oxide (DOX), Drain-Side Underlap (Dund) and Dual Metal Work Function (DWF) on mitigating the Miller capacitance while maintain the switching characteristics of TFET device are comprehensively investigated and compared. Our results indicate that TFET device with DOX design provides superior reduction in Cinv and C¬gd while retaining comparable Ion-Ioff characteristics among the three design techniques. On the other hand, to enable MOSFET devices for high-speed low-power operation with extensively reduced supply voltage, advanced assist-circuit such as using the dual-supply dual-VT technique is indispensable at the cost of more complicated assist-circuits and needs of on-chip level shifter to generate dual supplies. We use TCAD mixed-mode simulations to comprehensively investigate the feasibility of sub-0.2V high-speed low-power circuits with the four topologies, nominal MOSFET-based circuits, MOSFET-based circuit with dual supply, dual-VT assisted circuits, nominal TFET-based circuits and TFET-based circuits with DOX design. The delay, dynamic energy, and Standby power of the logic circuits including NAND, Inverter, BUS Driver and Latch are comprehensively analyzed and compared. The results indicate that DOX TFET would be the best candidate in considering both the energy-delay product (EDP) and leakage power for NAND, Inverter and Latch circuits. While for Bus Driver in which the largest delay would take place among all logic blocks investigated, both the nominal and DOX TFET-based circuits outperform the nominal MOSFET-based circuits in EDP by about two orders of magnitude and consume comparable Standby power, revealing the potential of TFET device to achieve high-speed low-power circuit operation at VDD = 0.2V. In addition to logic circuits, various TFET SRAM cells including conventional 7T/8T SRAM cell, 6T SRAM cell with assisted footer and our proposed cells to circumvent the difficulties implementing TFET with conventional 6T SRAM topology are statistically examined and compared. The results indicate that our proposed 7T Drive-Less (DL) TFET SRAM cell with the utilization of 4T DL SRAM as the basis along with the independent gate control can effectively improve the stability of the bit cell in Hold, Read and Write mode with adequate bit cell area compared with other counterparts. On the other hand, with the process compatibility in TFET and CMOS device fabrication, we propose a mixed TFET-MOSFET 8T SRAM cell to exploit merits of both TFET and MOSFET devices. The detailed analysis on stability, performance and effectiveness of using different write-assist schemes are extensively demonstrated. Through our comprehensive study, our proposed mixed TFET-MOSFET 8T SRAM cell provides significant improvement in stability, performance and Vmin, exhibiting the chance to stand for robust ultra-low power SRAM design at the cost of slightly larger bit cell area. The advantages of the TFET devices for analog applications are assessed to examine the potential for SoC applications. The detailed analog properties and the figure-of-merit (FOM) of TFET and FinFET devices including the transconductance (gm), output resistance (Ro), intrinsic gain (gm x Ro), intrinsic capacitance and linearity are comprehensively studied from intrinsic device physics point of view. Our analysis indicates that for cost-performance ultra-low voltage/power applications, TFET provides substantial merits in intrinsic gain compared with the FinFET device while for high-performance applications, FinFET device outperforms the TFET device at moderate and high voltages. Besides, the operational transconductance amplifier is taken as the fundamental block to investigate the opportunities and concerns of the TFET device for analog/mixed-signal circuit applications. The results indicate that for cost-performance ultra-low power application, TFET OTA provides more than two times higher unity-gain frequency (fT), and 10dB larger common-mode rejection ratio (CMRR) than FinFET OTA at comparable power consumption design. As the continual scaling of device dimension along with the reduced supply voltages, the impacts of intrinsic device variations become the critical concerns affecting device characteristics and circuit designs. The in-depth assessment of the impacts of Work-Function Variation and Fin Line-Edge Roughness on TFET and FinFET device characteristics are carried out through atomistic 3D TCAD simulations. Look-up table based Verilog-A model calibrated with TCAD results is built for each variation source and incorporates with HSPICE simulations to efficiently investigate impacts of Work-Function Variation and Fin Line-Edge Roughness on TFET SRAMs including our proposed mixed TFET-MOSFET 8T SRAM cell, conventional FinFET 8T SRAM cell and TFET 8T SRAM cell. For the first time, the feasibility/issues of each SRAM cell for ultra-low voltage operation considering intrinsic device variability are addressed. Our results indicate that our proposed mixed cell with exploiting merits of both devices provides superior stability and insusceptibility to intrinsic device variations, revealing its viability and robustness to operate at ultra-low voltages.
Su, Yen-So, and 蘇彥守. "Design and Simulation of Improved Swing and Ambipolar Effect for Tunnel FET by Band Engineering Using Metal at Drain Side." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/bfs697.
Повний текст джерелаRamesha, A. "Sub-Threshold Slope Modeling & Gate Alignment Issues In Tunnel Field Effect Transistor." Thesis, 2008. http://hdl.handle.net/2005/792.
Повний текст джерелаFan, Ming-Long, and 范銘隆. "Design and Analysis of Nanoscale FinFET, Tunnel FET and Hetero-Channel 3D Integrated Ultra-Thin-Body Devices for Ultra-Low-Power SRAM and Logic Circuits." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/25878819945473509609.
Повний текст джерела國立交通大學
電子工程學系 電子研究所
103
This dissertation provides an extensive assessment of nanoscale FinFET, Tunnel FET (TFET) and hetero-channel 3D integrated Ultra-Thin-Body (UTB) MOSFET for ultra-low-power applications. Device-circuit interactions and co-optimizations are considered to demonstrate the potential and concerns of these emerging devices from the device/circuit point of view. Through our analysis, the impacts of device variability and low-VDD operation on the leakage/delay and stability/performance of logic circuits and SRAM cells are evaluated to offer insights for future low-voltage circuit designs. With the superior electrostatic integrity and variability immunity of FinFET devices, the Static Noise Margin (SNM) of subthreshold FinFET SRAM cells is investigated using an analytical SNM model. Examination of the stabilities of several novel 6T FinFET cells using independent-gate technique indicates significant improvements in nominal READ SNM (RSNM) in these cells. However, the WRITE ability is found to be degraded and limits the cell robustness for certain cells in the subthreshold region. The READ/WRITE word-line voltage control technique is found to be more effective than transistor sizing in enhancing the stability of subthreshold FinFET SRAM cell. In addition, a model-assisted approach is developed to account for multiple variation sources simultaneously and efficiently when investigating the impact of device variability on the cell stability. Compared with Work-Function Variation (WFV), our results indicate that fin Line-Edge-Roughness (fin LER) dominates the overall subthreshold drain current fluctuation. With the established model approach, two recently introduced 4T and conventional 6T FinFET SRAM cells are statistically examined. Because of the reduced READ disturb, the 4T cells exhibit better nominal RSNM and the nearly ideal VWRITE,0 and VWRITE,1 of 4T cells promise the positive nominal WRITE SNM (WSNM) for selected cells. Under identical cell area, 4T SRAM cells with fewer transistors have the flexibility to increase device size (reduced σRSNM) and outperform the 6T counterpart. On the other hand, because of its vertical topology and difference in the degree of quantum confinement, the conventional sidewall conducting (110) surface orientation of FinFET can be rotated by layout to improve cell variability. It is found that NFET with (110) orientation shows larger fin LER induced threshold-voltage variation than the (100) one, while PFET exhibits the opposite trend. Therefore, with optimal orientations, significant μ/σ ratio improvement in RSNM can be achieved by using SRAM cell with (PU,PD,PG) = (110,100,100), revealing the potential of 6T FinFET cells with appropriate optimization for emerging subthreshold FinFET SRAM applications. In addition to cell, the viability and merits of small-signal differential sensing and large-signal single-ended sensing schemes for FinFET SRAM are investigated under the influence of variability. The local random variation of selected cell, leakage (and its variation) from unselected cells on the selected bit-line, and variation of sense amplifier offset voltage (VOS) and trip voltage (VTRIP) are considered simultaneously. For differential sensing scheme, the subthreshold sensing margin is severely degraded by the variation in bit-line voltage and sufficient time before enabling the sense amplifier is required. For large-signal sensing scheme, we show that there is large disparity between the sense “0” margin and sense “1” margin with significantly worse sense “0” margin limiting the affordable number of cells per bit-line and performance. Using our statistical model-based approach, it is observed that the VOS of Current-Latch Sense Amplifier (CLSA) calculated solely from threshold-voltage mismatch underestimates the actual variation and is shown to be optimistic. Compared with the conventional BULK MOSFET, FinFET enhances the feasibility of differential sensing in subthreshold SRAM applications. Under low-VDD design, the importance of Random Telegraph Noise (RTN) increases and threats the functionality of circuits. We analyze the impact of single-trap-induced RTN on FinFET devices, 6T SRAM cell, and several logic circuits. Our result indicates that the charged interface trap located near the bottom and middle region between source/drain results in most significant impact. Besides, Equivalent Oxide Thickness (EOT) scaling and higher operating temperature are found to improve the immunity to RTN. The larger variability and surface conduction of planar BULK MOSFET lead to broader dispersion and larger worst-case RTN degradation than the FinFET with smaller variability and volume conduction. In the presence of RTN, ~ 24% - 27% and ~ 13% - 15% additional variations in the leakage and delay, respectively, are observed at VDD = 0.4V for the FinFET inverter, Two-Way NAND and Two-To-One multiplexer. Using band-to-band tunneling as major conduction mechanism, Tunnel FET (TFET) with capability to surmount the thermionic limitation and provide superior switching characteristics is regarded as promising candidate for ultra-low-voltage operation. We extensively investigate the impacts of single acceptor-type or donor-type interface trap induced RTN on TFET device, SRAM circuits and its interaction with WFV. In our analysis, significant RTN amplitude is observed for a single acceptor trap near the tunneling junction, whereas a donor trap is found to cause more severe impact over a broader region across the channel region. Moreover, several device parameters which can improve the TFET subthreshold characteristics (e.g. thinner EOT, fin width or longer channel length) are found to increase the susceptibility to RTN. Under WFV, TFET exhibits weaker correlation between ION and IOFF than that in the FinFET. In the presence of WFV, the RTN amplitude can be enhanced or reduced depending on the type of trap and composition/orientation of metal-gate grain. In addition, our analysis indicates that ~ 16% extra variation (at VDD = 0.3V) in the stability of standard 8T SRAM cell and ~80mV additional VOS variation (at VDD = 0.5V) for the CLSA circuit are observed. The advantages of hetero-channel logic circuits and 6T/8T SRAM cells for low-power applications are comprehensively evaluated with monolithic 3D integration. With adequate 3D layout design, minimum leakage, equivalent to the planar 2D circuits with dual backgate biases (VBS), is achievable. Furthermore, with interlayer coupling, substantial performance improvements over the 2D counterparts are found for monolithic 3D inverters, Two-Way NAND, multiplexer, static latch and D Flip-Flop, especially for GeOI logic circuits operating in low VDD. Besides, various bit-cell layouts with different gate alignments of transistors from distinct layers are investigated for the evaluation of cell stability/performance of two-tier 6T/8T SRAM cells. Our studies indicate that stacking the NFET tier over the PFET layer results in larger design margins for cell robustness and performance. The larger improvements over the 2D counterparts make hetero-channel 3D integrated MOSFET a suitable candidate for monolithic 3D applications. For III-V UTB Heterojunction TFET (HTFET), the impact of VBS on the drain current and implications/designs for monolithic 3D SRAM cells are assessed. Compared with homojunction TFET and conventional MOSFET, our results indicate that HTFET exhibits significantly higher IOFF modulation efficiency and the influence of VBS rapidly decreases with increasing gate voltage. In addition, it is observed that the change of source available states with VBS determines the ID modulation efficiency of p-type HTFET. Depending on the source doping and operating VG, the ID of HTFET under forward VBS can be anomalously smaller than that at VBS = 0V. With the difference in the efficiency of interlayer coupling, the standard all-TFET and our proposed hybrid 8T SRAM cells are optimized with layouts and compared in 2D/3D integrations.
Hanna, Amir. "Non-Planar Nanotube and Wavy Architecture Based Ultra-High Performance Field Effect Transistors." Diss., 2016. http://hdl.handle.net/10754/621933.
Повний текст джерела(7025126), Ahmedullah Aziz. "Device-Circuit Co-Design Employing Phase Transition Materials for Low Power Electronics." Thesis, 2019.
Знайти повний текст джерелаPhase transition materials (PTM) have garnered immense interest in concurrent post-CMOS electronics, due to their unique properties such as - electrically driven abrupt resistance switching, hysteresis, and high selectivity. The phase transitions can be attributed to diverse material-specific phenomena, including- correlated electrons, filamentary ion diffusion, and dimerization. In this research, we explore the application space for these materials through extensive device-circuit co-design and propose new ideas harnessing their unique electrical properties. The abrupt transitions and high selectivity of PTMs enable steep (< 60 mV/decade) switching characteristics in Hyper-FET, a promising post-CMOS transistor. We explore device-circuit co-design methodology for Hyper-FET and identify the criterion for material down-selection. We evaluate the achievable voltage swing, energy-delay trade-off, and noise response for this novel device. In addition to the application in low power logic device, PTMs can actively facilitate non-volatile memory design. We propose a PTM augmented Spin Transfer Torque (STT) MRAM that utilizes selective phase transitions to boost the sense margin and stability of stored data, simultaneously. We show that such selective transitions can also be used to improve other MRAM designs with separate read/write paths, avoiding the possibility of read-write conflicts. Further, we analyze the application of PTMs as selectors in cross-point memories. We establish a general simulation framework for cross-point memory array with PTM based selector. We explore the biasing constraints, develop detailed design methodology, and deduce figures of merit for PTM selectors. We also develop a computationally efficient compact model to estimate the leakage through the sneak paths in a cross-point array. Subsequently, we present a new sense amplifier design utilizing PTM, which offers built-in tunable reference with low power and area demand. Finally, we show that the hysteretic characteristics of unipolar PTMs can be utilized to achieve highly efficient rectification. We validate the idea by demonstrating significant design improvements in a Cockcroft-Walton Multiplier, implemented with TS based rectifiers. We emphasize the need to explore other PTMs with high endurance, thermal stability, and faster switching to enable many more innovative applications in the future.