Статті в журналах з теми "Transistor scaling"
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Ahmed Mohammede, Arsen, Zaidoon Khalaf Mahmood, and Hüseyin Demirel. "Study of finfet transistor: critical and literature review in finfet transistor in the active filter." 3C TIC: Cuadernos de desarrollo aplicados a las TIC 12, no. 1 (March 31, 2023): 65–81. http://dx.doi.org/10.17993/3ctic.2023.121.65-81.
Повний текст джерелаDatta, Suman, Wriddhi Chakraborty, and Marko Radosavljevic. "Toward attojoule switching energy in logic transistors." Science 378, no. 6621 (November 18, 2022): 733–40. http://dx.doi.org/10.1126/science.ade7656.
Повний текст джерелаSARKOZY, S., X. MEI, W. YOSHIDA, P. H. LIU, M. LANGE, J. LEE, Z. ZHOU, et al. "AMPLIFIER GAIN PER STAGE UP TO 0.5 THz USING 35 NM InP HEMT TRANSISTORS." International Journal of High Speed Electronics and Systems 20, no. 03 (September 2011): 399–404. http://dx.doi.org/10.1142/s0129156411006684.
Повний текст джерелаReid, Dave, Campbell Millar, Scott Roy, Gareth Roy, Richard Sinnott, Gordon Stewart, Graeme Stewart, and Asen Asenov. "Enabling cutting-edge semiconductor simulation through grid technology." Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences 367, no. 1897 (June 28, 2009): 2573–84. http://dx.doi.org/10.1098/rsta.2009.0031.
Повний текст джерелаFazio, Al. "Flash Memory Scaling." MRS Bulletin 29, no. 11 (November 2004): 814–17. http://dx.doi.org/10.1557/mrs2004.233.
Повний текст джерелаAngelov, George V., Dimitar N. Nikolov, and Marin H. Hristov. "Technology and Modeling of Nonclassical Transistor Devices." Journal of Electrical and Computer Engineering 2019 (November 3, 2019): 1–18. http://dx.doi.org/10.1155/2019/4792461.
Повний текст джерелаIeong, Meikei, Vijay Narayanan, Dinkar Singh, Anna Topol, Victor Chan, and Zhibin Ren. "Transistor scaling with novel materials." Materials Today 9, no. 6 (June 2006): 26–31. http://dx.doi.org/10.1016/s1369-7021(06)71540-1.
Повний текст джерелаCastañer, Luis M., Ramon Alcubilla, and Anna Benavent. "Bipolar transistor vertical scaling framework." Solid-State Electronics 38, no. 7 (July 1995): 1367–71. http://dx.doi.org/10.1016/0038-1101(94)00254-d.
Повний текст джерелаJacob, Ajey P., Ruilong Xie, Min Gyu Sung, Lars Liebmann, Rinus T. P. Lee, and Bill Taylor. "Scaling Challenges for Advanced CMOS Devices." International Journal of High Speed Electronics and Systems 26, no. 01n02 (February 17, 2017): 1740001. http://dx.doi.org/10.1142/s0129156417400018.
Повний текст джерелаChen, Zhuo, Huilong Zhu, Guilei Wang, Qi Wang, Zhongrui Xiao, Yongkui Zhang, Jinbiao Liu, et al. "High-Quality Recrystallization of Amorphous Silicon on Si (100) Induced via Laser Annealing at the Nanoscale." Nanomaterials 13, no. 12 (June 15, 2023): 1867. http://dx.doi.org/10.3390/nano13121867.
Повний текст джерелаPark, Junhyeong, Yuseong Jang, Jinkyu Lee, and Soo-Yeon Lee. "48‐3: In‐Ga‐Zn‐O Synaptic Transistor with 1 µm Channel Length for Neuromorphic Computing." SID Symposium Digest of Technical Papers 54, no. 1 (June 2023): 699–702. http://dx.doi.org/10.1002/sdtp.16655.
Повний текст джерелаKumar, MAnil, YNSSai Kiran, U. Jagadeesh, B. Balaram, and M. Durga Prakash. "SCALING CHALLENGES FOR ADVANCED TRANSISTOR DESIGN." International Journal of Advanced Research 5, no. 5 (May 31, 2017): 340–45. http://dx.doi.org/10.21474/ijar01/4118.
Повний текст джерелаFitsilis, Michael, Yacoub Mustafa, and Rainer Waser. "Scaling the Ferroelectric Field Effect Transistor." Integrated Ferroelectrics 70, no. 1 (April 13, 2005): 29–44. http://dx.doi.org/10.1080/10584580590926657.
Повний текст джерелаChen, Wenbin. "Characterization of new materials for capacitor formation in integrated circuit technology." Boolean: Snapshots of Doctoral Research at University College Cork, no. 2010 (January 1, 2010): 26–31. http://dx.doi.org/10.33178/boolean.2010.7.
Повний текст джерелаCao, Qing, Shu-Jen Han, Jerry Tersoff, Aaron D. Franklin, Yu Zhu, Zhen Zhang, George S. Tulevski, Jianshi Tang, and Wilfried Haensch. "End-bonded contacts for carbon nanotube transistors with low, size-independent resistance." Science 350, no. 6256 (October 1, 2015): 68–72. http://dx.doi.org/10.1126/science.aac8006.
Повний текст джерелаUrteaga, M., S. Krishnan, D. Scott, Y. Wei, M. Dahlstrom, S. Lee, and M. J. W. Rodwell. "Submicron InP-based HBTs for Ultra-high Frequency Amplifiers." International Journal of High Speed Electronics and Systems 13, no. 02 (June 2003): 457–95. http://dx.doi.org/10.1142/s0129156403001806.
Повний текст джерелаJohn Chelliah, Cyril R. A., and Rajesh Swaminathan. "Current trends in changing the channel in MOSFETs by III–V semiconducting nanostructures." Nanotechnology Reviews 6, no. 6 (November 27, 2017): 613–23. http://dx.doi.org/10.1515/ntrev-2017-0155.
Повний текст джерелаKumar, Abneesh, Atal Rai, R. K. Saxena, and Suresh Patel. "To Study Effect on Current Due to Channel Length Variation." International Journal of Advance Research and Innovation 2, no. 4 (2014): 30–32. http://dx.doi.org/10.51976/ijari.241406.
Повний текст джерелаFLYNN, MICHAEL P., SUNGHYUN PARK, and CHUN C. LEE. "ACHIEVING ANALOG ACCURACY IN NANOMETER CMOS." International Journal of High Speed Electronics and Systems 15, no. 02 (June 2005): 255–75. http://dx.doi.org/10.1142/s0129156405003193.
Повний текст джерелаMishra, Brijendra, Vivek Singh Kushwah, and Rishi Sharma. "MODELING OF HYBRID MOS FOR THE IMPLEMENTATION OF SWITCHED CAPACITOR FILTER USING SINGLE ELECTRON TRANSISTOR." International Journal of Engineering Technologies and Management Research 5, no. 2 (May 4, 2020): 294–300. http://dx.doi.org/10.29121/ijetmr.v5.i2.2018.659.
Повний текст джерелаKumari, Nibha, and Prof Vandana Niranjan. "Low-Power 6T SRAM Cell using 22nm CMOS Technology." Indian Journal of VLSI Design 2, no. 2 (September 30, 2022): 5–10. http://dx.doi.org/10.54105/ijvlsid.b1210.092222.
Повний текст джерелаPackan, Paul A. "Scaling Transistors into the Deep-Submicron Regime." MRS Bulletin 25, no. 6 (June 2000): 18–21. http://dx.doi.org/10.1557/mrs2000.93.
Повний текст джерелаPatel, Ambresh, and Ritesh Sadiwala. "Optimizing and Recuperating the Leakages in Low Voltage CMOS Circuits." SAMRIDDHI : A Journal of Physical Sciences, Engineering and Technology 14, no. 02 (June 30, 2022): 202–5. http://dx.doi.org/10.18090/samriddhi.v14i02.13.
Повний текст джерелаLu, Bin Bin, and Jian Ping Hu. "Complementary Pass-Transistor Adiabatic Logic Using Dual Threshold CMOS Techniques." Applied Mechanics and Materials 39 (November 2010): 55–60. http://dx.doi.org/10.4028/www.scientific.net/amm.39.55.
Повний текст джерелаPan, Y. "A fundamental limitation for bipolar transistor scaling." IEEE Electron Device Letters 11, no. 10 (October 1990): 445–47. http://dx.doi.org/10.1109/55.62991.
Повний текст джерелаNagy, Roland, Alex Burenkov, and Jürgen Lorenz. "Numerical evaluation of the ITRS transistor scaling." Journal of Computational Electronics 14, no. 1 (November 4, 2014): 192–202. http://dx.doi.org/10.1007/s10825-014-0638-0.
Повний текст джерелаHaggag, Amr, William McMahon, Karl Hess, Björn Fischer, and Leonard F. Register. "Impact of Scaling on CMOS Chip Failure Rate, and Design Rules for Hot Carrier Reliability." VLSI Design 13, no. 1-4 (January 1, 2001): 111–15. http://dx.doi.org/10.1155/2001/90787.
Повний текст джерелаChen, Zhuo, Huilong Zhu, Guilei Wang, Qi Wang, Zhongrui Xiao, Yongkui Zhang, Jinbiao Liu, et al. "Investigation on Recrystallization Channel for Vertical C-Shaped-Channel Nanosheet FETs by Laser Annealing." Nanomaterials 13, no. 11 (June 1, 2023): 1786. http://dx.doi.org/10.3390/nano13111786.
Повний текст джерелаRenukarani, S., Bhavana Godavarthi, SK Bia Roshini, and Mohammad Khadir. "A Novel concept on 8-Transistor Dynamic Feedback Control on Static RAM Cell Array." International Journal of Engineering & Technology 7, no. 2.20 (April 18, 2018): 109. http://dx.doi.org/10.14419/ijet.v7i2.20.12185.
Повний текст джерелаSri Selvarajan, Reena, Azrul Azlan Hamzah, Norliana Yusof, and Burhanuddin Yeop Majlis. "Channel length scaling and electrical characterization of graphene field effect transistor (GFET)." Indonesian Journal of Electrical Engineering and Computer Science 15, no. 2 (August 1, 2019): 697. http://dx.doi.org/10.11591/ijeecs.v15.i2.pp697-703.
Повний текст джерелаZhao, Dongxue, Zhiliang Xia, Tao Yang, Yuancheng Yang, Wenxi Zhou, and Zongliang Huo. "A Novel Capacitorless 1T DRAM with Embedded Oxide Layer." Micromachines 13, no. 10 (October 19, 2022): 1772. http://dx.doi.org/10.3390/mi13101772.
Повний текст джерелаWong, Hei, and Kuniyuki Kakushima. "On the Vertically Stacked Gate-All-Around Nanosheet and Nanowire Transistor Scaling beyond the 5 nm Technology Node." Nanomaterials 12, no. 10 (May 19, 2022): 1739. http://dx.doi.org/10.3390/nano12101739.
Повний текст джерелаWang, Peng-Fei, Xi Lin, Lei Liu, Qing-Qing Sun, Peng Zhou, Xiao-Yong Liu, Wei Liu, Yi Gong, and David Wei Zhang. "A Semi-Floating Gate Transistor for Low-Voltage Ultrafast Memory and Sensing Operation." Science 341, no. 6146 (August 8, 2013): 640–43. http://dx.doi.org/10.1126/science.1240961.
Повний текст джерелаMasalsky, Nikolay. "Silicon on isolator ribbon field-effect nanotransistors for high-sensitivity low-power biosensor." Journal of Engineering and Technological Sciences 54, no. 2 (March 31, 2022): 220214. http://dx.doi.org/10.5614/j.eng.technol.sci.2022.54.2.14.
Повний текст джерелаEt. al., Kothamasu Jyothi,. "9T SRAM CELL WITH MT-SVL TECHNIQUE FOR LEAKAGE POWER REDUCTION." INFORMATION TECHNOLOGY IN INDUSTRY 9, no. 2 (April 13, 2021): 1139–43. http://dx.doi.org/10.17762/itii.v9i2.465.
Повний текст джерелаMarrakh, R., and A. Bouhdada. "Modeling of the I–V Characteristics for LDD-nMOSFETs in Relation with Defects Induced by Hot-Carrier Injection." Active and Passive Electronic Components 26, no. 4 (2003): 197–204. http://dx.doi.org/10.1080/08827510310001624363.
Повний текст джерелаWulf, Ulrich, and Hans Richter. "Scale-Invariant Drain Current in Nano-FETs." Journal of Nano Research 10 (April 2010): 49–61. http://dx.doi.org/10.4028/www.scientific.net/jnanor.10.49.
Повний текст джерелаKumar, Nandhaiahgari Dinesh, Rajendra Prasad Somineni, and CH Raja Kumari. "Design and analysis of different full adder cells using new technologies." International Journal of Reconfigurable and Embedded Systems (IJRES) 9, no. 2 (July 1, 2020): 116. http://dx.doi.org/10.11591/ijres.v9.i2.pp116-124.
Повний текст джерелаCao, Qing. "Carbon nanotube transistor technology for More-Moore scaling." Nano Research 14, no. 9 (April 26, 2021): 3051–69. http://dx.doi.org/10.1007/s12274-021-3459-z.
Повний текст джерелаVolcheck, V. S., and V. R. Stempitsky. "Numerical simulation of the sensor for toxic nanoparticles based on the heterostructure field effect transistor." Doklady BGUIR 18, no. 8 (December 27, 2020): 62–68. http://dx.doi.org/10.35596/1729-7648-2020-18-8-62-68.
Повний текст джерелаGul, Waqas, Maitham Shams, and Dhamin Al-Khalili. "SRAM Cell Design Challenges in Modern Deep Sub-Micron Technologies: An Overview." Micromachines 13, no. 8 (August 17, 2022): 1332. http://dx.doi.org/10.3390/mi13081332.
Повний текст джерелаDimoulas, Athanasios, Akira Toriumi, and Suzanne E. Mohney. "Source and Drain Contacts for Germanium and III–V FETs for Digital Logic." MRS Bulletin 34, no. 7 (July 2009): 522–29. http://dx.doi.org/10.1557/mrs2009.140.
Повний текст джерелаWu, C. H., G. Walter, H. W. Then, M. Feng, and N. Holonyak. "Scaling of light emitting transistor for multigigahertz optical bandwidth." Applied Physics Letters 94, no. 17 (April 27, 2009): 171101. http://dx.doi.org/10.1063/1.3126642.
Повний текст джерелаZhang, Shubo. "Review of Modern Field Effect Transistor Technologies for Scaling." Journal of Physics: Conference Series 1617 (August 2020): 012054. http://dx.doi.org/10.1088/1742-6596/1617/1/012054.
Повний текст джерелаLi, Chi-Kang, Po-Chun Yeh, Jeng-Wei Yu, Lung-Han Peng, and Yuh-Renn Wu. "Scaling performance of Ga2O3/GaN nanowire field effect transistor." Journal of Applied Physics 114, no. 16 (October 28, 2013): 163706. http://dx.doi.org/10.1063/1.4827190.
Повний текст джерелаMuller, D. A., P. M. Voyles, J. L. Grazul, and G. D. Wilk. "Exploring the physical limits of transistor scaling using STEM." Microscopy and Microanalysis 9, S02 (August 2003): 1012–13. http://dx.doi.org/10.1017/s1431927603445066.
Повний текст джерелаAbdul Tahrim, ‘Aqilah binti, Huei Chaeng Chin, Cheng Siong Lim, and Michael Loong Peng Tan. "Design and Performance Analysis of 1-Bit FinFET Full Adder Cells for Subthreshold Region at 16 nm Process Technology." Journal of Nanomaterials 2015 (2015): 1–13. http://dx.doi.org/10.1155/2015/726175.
Повний текст джерелаMertens, Hans. "Nanosheet-Based Transistor Architectures for Advanced CMOS Scaling: Wet Etch and Gas Phase Etch Challenges in Confined Spaces." Solid State Phenomena 346 (August 14, 2023): 8–13. http://dx.doi.org/10.4028/p-tzn0md.
Повний текст джерелаBirla, Shilpi, Sudip Mahanti, and Neha Singh. "Leakage reduction technique for nano-scaled devices." Circuit World 47, no. 1 (May 29, 2020): 97–104. http://dx.doi.org/10.1108/cw-12-2019-0195.
Повний текст джерелаHu, Jian Ping, and Yu Zhang. "Gate-Length Biasing Technique of Complementary Pass-Transistor Adiabatic Logic for Leakage Reduction." Advanced Materials Research 159 (December 2010): 180–85. http://dx.doi.org/10.4028/www.scientific.net/amr.159.180.
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