Дисертації з теми "Transistor scaling"
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Chen, Qiang. "Scaling limits and opportunities of double-gate MOSFETS." Diss., Georgia Institute of Technology, 2003. http://hdl.handle.net/1853/15011.
Повний текст джерелаDeshpande, Veeresh. "Scaling Beyond Moore: Single Electron Transistor and Single Atom Transistor Integration on CMOS." Phd thesis, Université de Grenoble, 2012. http://tel.archives-ouvertes.fr/tel-00813508.
Повний текст джерелаWoo, Raymond. "Band-to-band tunneling transistor scaling and design for low-power logic applications /." May be available electronically:, 2009. http://proquest.umi.com/login?COPT=REJTPTU1MTUmSU5UPTAmVkVSPTI=&clientId=12498.
Повний текст джерелаYuan, Jiahui. "Cryogenic operation of silicon-germanium heterojunction bipolar transistors and its relation to scaling and optimization." Diss., Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/33837.
Повний текст джерелаSchuette, Michael L. "Advanced processing for scaled depletion and enhancement-mode AlGaN/GaN HEMTs." The Ohio State University, 2010. http://rave.ohiolink.edu/etdc/view?acc_num=osu1275524410.
Повний текст джерелаAhmed, Adnan. "Study of Low-Temperature Effects in Silicon-Germanium Heterojunction Bipolar Transistor Technology." Thesis, Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/7227.
Повний текст джерелаConnor, Mark Anthony. "Design of Power-Scalable Gallium Nitride Class E Power Amplifiers." University of Dayton / OhioLINK, 2014. http://rave.ohiolink.edu/etdc/view?acc_num=dayton1405437893.
Повний текст джерелаNicoletti, Talitha. "Estudo de transistores UTBOX SOI não auto-alinhados como célula de memória." Universidade de São Paulo, 2013. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-10072014-012728/.
Повний текст джерелаThe main topic of this work is the study of extensionless UTBOX SOI transistors, also called underlapped devices, applied as a single transistor floating body RAM (1T-FBRAM single transistor floating body access memory). The electrical characterization of the devices was performed through static and dynamic experimental data and two dimensional simulations were implemented to confirm the obtained results. In the literature, different methods to write and read the data 1 can be found but in order to improve the dynamic parameters of the memories, as retention time and sense margin and still allows the scaling of fully depleted devices, the BJT (Bipolar Junction Transistor) method is used in this work. One of the biggest issues to meet the specifications for future generations of 1T-DRAM cells is the retention time that scales together with the channel length. In order to overcome this issue or at least slow it down, in this work, we present for the first time, a study about the retention time and sense margin dependence of the channel length where it was possible to observe that these dynamic parameters can be optimized through the back gate bias and kept constant for channel lengths higher than 50 nm for extensionless devices and 80 nm for standard ones. However, it was also observed that there is a minimal channel length which depends of the source/drain junctions, i.e. 30 nm for extensionless and 50 nm for standard devices in the sense that for shorter channel lengths than these ones, there is no room for optimization degrading the performance of the memory cell. The mechanism behind the dynamic parameters degradation was identified and attributed to the GIDL current amplification by the lateral bipolar transistor with narrow base. Simulations confirmed this effect where higher generation rates near the junctions were presented only when the band-toband- tunneling adjustment was considered (bbt.kane model). Comparing the performance of standard and extensionless devices in both digital and analog electrical parameters and also in memory applications, it was found that extensionless devices present better performance since they reach faster switching which means lower subthreshold slope; less influence of the electrical field in the channel charges; less variation of the threshold voltage even increasing the temperature. Furthermore, it was seen that the gate length can be further scaled using underlap junctions since these devices are less susceptible to the GIDL current, presenting less electric field and generation rate near the source/drain junctions and reach a retention time of around 4 ms and sense margin of 71A/m. According to the International Technology Roadmap for Semiconductor of 2011, the retention time for the existing DRAM is around 64 ms. In order to increase the retention time of the 1T-DRAMs to values close to 64 ms it is recommended the use of extensionless devices and also the substitution of silicon by materials with higher band gap, i.e., gallium arsenide and siliconcarbon, which makes difficult the electron tunneling therefore, decreasing the GIDL.
Murali, Raghunath. "Scaling opportunities for bulk accumulation and inversion MOSFETs for gigascale integration." Diss., Available online, Georgia Institute of Technology, 2004:, 2004. http://etd.gatech.edu/theses/submitted/etd-02132004-173432/unrestricted/murali%5FRaghunath%5F405%5F.pdf.
Повний текст джерелаHess, Dennis, Committee Member; Meindl, James, Committee Chair; Allen, Phillip, Committee Member; Cressler, John, Committee Member; Davis, Jeffrey, Committee Member. Vita. Includes bibliographical references (leaves 108-119).
Hoppe, Arne [Verfasser]. "Scaling limits and Megahertz operation in thiophene-based field effect transistors / Arne Hoppe." Bremen : IRC-Library, Information Resource Center der Jacobs University Bremen, 2008. http://d-nb.info/1034966928/34.
Повний текст джерелаWang, Lihui. "Quantum Mechanical Effects on MOSFET Scaling." Diss., Available online, Georgia Institute of Technology, 2006, 2006. http://etd.gatech.edu/theses/available/etd-07072006-111805/.
Повний текст джерелаPhilip First, Committee Member ; Ian F. Akyildiz, Committee Member ; Russell Dupuis, Committee Member ; James D. Meindl, Committee Chair ; Willianm R. Callen, Committee Member.
Chaves, Romero Ferney Alveiro. "Study and Modeling of Multi‐ Gate Transistors in the Context of CMOS Technology Scaling." Doctoral thesis, Universitat Autònoma de Barcelona, 2012. http://hdl.handle.net/10803/96232.
Повний текст джерелаThe scaling of the conventional MOSFETs has led these devices to the nanoscale to increase both the performance and the number of components per chip. In this process, the so-called “Short Channel Effects” have arisen as a limiting factor. To extend the use of the bulk MOSFETs, the most effective ways of suppressing such effects are the reduction of the gate oxide thickness and increasing of the channel doping concentration. When the gate oxide thickness is reduced to a few atomic layers, quantum mechanical tunneling is responsible of a huge increase in the gate leakage current impairing the normal operation of MOSFETs. This has made mandatory the use of high permittivity materials or high-κ as gate dielectrics. Despite the proposed solutions, reduction of the physical dimensions of the conventional MOSFETs cannot be maintained. To keep the technological trend, new MOSFET structures have been suggested such as ultra-thin body Multi-Gate MOSFETs. In particular, the Double-Gate MOSFETs is considered as a promising MG structure for its several qualities and advantages in scaling. This thesis focuses on the modeling of Double-Gate MOSFET and, in particular, on the modeling of the gate leakage current critically affecting the power consumption. First we develop a compact quantum model for both the electrostatic potential and the electric charge in symmetric double-gate MOSFET with undoped thin body. Then, this quantum model is used to propose an analytical compact model for the direct tunnelling current with SiO2 as gate dielectric, firstly, and later assuming a dual layer consisting of a SiO2 interfacial layer and a high-κ material. Finally, an accurate method for the calculation of the gate tunnelling current is developed. It is based on Absorbing Boundary Conditions techniques and, more specifically, on the Perfectly Mached Layer (PML) method. This thesis is motivated by the recommendations given by the “International Technology Roadmap of Semiconductors” (ITRS) about the need for the modeling and simulation of multi-gate semiconductor structures.
Peršun, Marijan. "Scaling of the Silicon-on-Insulator Si and Si1-xGex p-MOSFETs." PDXScholar, 1995. https://pdxscholar.library.pdx.edu/open_access_etds/4934.
Повний текст джерелаFlachowsky, Stefan. "Verspannungstechniken zur Leistungssteigerung von SOI-CMOS-Transistoren." Doctoral thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2010. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-63136.
Повний текст джерелаAs conventional MOSFET scaling is reaching its limits, several novel techniques are investigated to extend the CMOS roadmap. One of these techniques is the introduction of mechanical strain in the silicon transistor channel. Because strain changes the inter-atomic distances and thus the electronic band structure of silicon, ntype and p-type transistors with strained channels can show enhanced carrier mobility and performance. The purpose of this thesis is to analyze and understand the effects of strain on the electronic properties of planar silicon-on-insulator MOSFETs for high-performance applications as well as the optimization of various stress techniques and their technological limitations. First, the effect of strain on the electronic band structure of silicon and the carrier mobility is studied systematically using the empirical pseudopotential method and the deformation potential theory. Strain-induced energy band splitting and band deformations alter the electron and hole mobility through modulated effective masses and modified scattering rates. The various concepts for strain generation inside the transistor channel are reviewed. The focus of this work is on strained overlayer films, strained Si1-xGex and Si1-yCy in the source/drain regions, stress memorization techniques and strained substrates. It is shown, that strained silicon based improvements are highly sensitive to the device layout and geometry. For that reason, numerical simulations are indispensable to analyze the efficiency of the strain techniques to transfer strain into the channel. In close relation with experimental work the results from detailed simulation studies including parameter variations and material analyses are presented, as well as a thorough investigation of critical parameters to increase the strain in the transistor channel. Thus, the process conditions and the properties of the fabricated devices can be optimized with respect to higher performance. In addition, technological limitations are discussed and the potential of the different strain techniques for further performance enhancements in future technology generations is evaluated. With the continuing reduction in device dimensions the detrimental impact of the parasitic source/drain resistance on device performance is quantified and projected to be the bottleneck for strain-induced performance improvements. Next, the effects from a combination of individual strain techniques are studied and their interactions or possible restrictions are highlighted. Finally, the transport properties in the low-field transport regime as well as under high electrical fields are analyzed and the notable differences between strained n-type and p-type transistors are discussed
Rosa, André Luís Rodeghiero. "Projeto de células e circuitos VLSI digitais CMOS para operação em baixa tensão." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2015. http://hdl.handle.net/10183/118526.
Повний текст джерелаThis work proposes a strategy for designing VLSI circuits to operate in a very-wide Voltage-Frequency Scaling (VFS) range , from the supply voltage at which the minimum energy per operation (MEP) is achieved, at the Near-Threshold regime, up to the nominal supply voltage for the processes, if so demanded by applications workload. This master thesis proposes the sizing of transistors for three library cells using MOSFETs with different threshold voltages: Regular-VT (RVT), High-VT (HVT), and Low-VT (LVT). These libraries have five combinational cells: INV, NAND, NOR, OAI21, and AOI22 with multiple strengths. The sizing rule for the transistors of the digital cells was an adapted version from related works and it is directly driven by requiring equal rise and fall times at the output for each cell in order to attenuate variability effects in the low supply voltage regime. Two registers were also included in the RVT library cell. This library cell was characterized for typical, fast, and slow processes conditions of a CMOS 65nm technology; for operation at -40ºC, 25ºC, and 125ºC temperatures, and for supply voltages varying from 200 mV up to 1.2V, to include the region of interest, for VDD near the MEP. Experiments were performed with ten VLSI circuit benchmarks: notch filter, 8051 compatible core, four combinational and four sequential ISCAS benchmark circuits. From the energy savings point of view, to operate in MEP results on average reduction of 54.46% and 99.01% when compared with the sub-threshold and nominal supply voltages, respectively. This analysis was performed for 25⁰C and typical process. When considered the performance, the very-wide VFS regime enables maximum operating frequencies varying from hundreds of kHz up to MHz/GHz at -40ºC and 25ºC, and from MHz up to GHz at 125ºC. This master thesis results, when compared with related works, showed on average an energy reduction and performance gain of 24.1% and 152.68%, respectively, for the same circuit benchmarks operating with VDD at the minimum energy point (MEP).
Gomez, gomez Ricardo. "Design of innovative solutions to improve the variability and reliability of CMOS circuits on thin film technologies." Thesis, Université Grenoble Alpes, 2020. http://www.theses.fr/2020GRALT023.
Повний текст джерелаThe increased sensitivity to Process, Voltage, Temperature, and Aging (PVTA) variations in scaled integrated circuits' technology nodes is responsible for a significant degradation in the products' specifications during high volume manufacturing. This has become a growing concern in digital circuit design, which has to cope with the increasingly stringent requirements of modern applications in terms of energy efficiency, reliability, and safety. In this thesis work, embedded timing monitoring and compensation techniques are explored to efficiently address these conflicting requirements. The proposed techniques are studied separately and then combined in 3 digital SoC demonstrators manufactured in 28nm FD-SOI CMOS technology, one of which has been measured at the time of this manuscript's writing.Embedded timing monitoring is proposed as a design solution to enable PVTA compensation, in-field safety monitoring and security protection against hardware timing attacks. The state-of-the-art timing monitors are evaluated from the perspective of an integration into industrial products, emphasizing features such as high reusability and low integration costs. The identified advantages of register-to-register timing monitoring have led to the implementation of a 3mV/bit tunable replica circuit in 28nm FD-SOI CMOS, which demonstrates a fast and accurate PVTA tracking of an ARM Cortex-R4F based SoC across slow/typical/fast process, 0.5/1.2V, -40/150ºC, and End Of Life (EOL) aging. Finally, this work proposes a novel timing monitor that overcomes the weaknesses of existing solutions, simultaneously achieving the high reusability and wide monitoring range of ring oscillators and the fast and accurate timing acquisition of tunable replica circuits.The exploration of adaptive and compensation techniques begins with the determination of their application scope in industrial designs: the improvement of the worst-case limiting corners that set the product's specifications during high volume manufacturing. Following this perspective, the optimal region of application of voltage scaling and body biasing techniques has been determined and their impact on the worst-case specifications of digital SoCs has been assessed. Finally, this work demonstrates how the power overhead induced by the separate application of voltage scaling or body biasing can be mitigated through the combination of both, specially in circuits with a variety of Operational Performance Points (OPPs).The benefits of the proposed techniques have been demonstrated in a digital SoC that optimizes its energy across 11X frequency-wide OPPs by combining adaptive voltage scaling, adaptive body biasing, and bias-in-memory-array with a tunable replica circuit for safety, embedded power regulation and compensation. Through the application of these techniques the proposed design overcomes previously reported limitations and demonstrates an improvement by 21X performance, 120mV lower Vmin, and 8X lifetime, the low-power, mid-, and high-performance OPPs respectively.The studies reported here have been included in several chapters of a scientific book to be published this year. Furthermore, they have contributed to a new technology and design platform. Finally, 3 IEEE conference publications and 3 patent applications have resulted from this thesis' work
Akgul, Yeter. "Gestion de la consommation basée sur l’adaptation dynamique de la tension, fréquence et body bias sur les systèmes sur puce en technologie FD-SOI." Thesis, Montpellier 2, 2014. http://www.theses.fr/2014MON20132/document.
Повний текст джерелаBeyond 28nm CMOS BULK technology node, some limits have been reached in terms of performance improvements. This is mainly due to the increasing power consumption. This is one of the reasons why new technologies have been developed, including those based on Silicon-On-Insulator (SOI). Moreover, the standardization of complex architectures such as multi-core architectures emphasizes the problem of power management at fine-grain. FD-SOI technologies offer new power management opportunities by adjusting, in addition to the usual parameters such as supply voltage and clock frequency, the body bias voltage. In this context, this work explores new opportunities and searches novel solutions for dynamically manage supply voltage, clock frequency and body bias voltage in order to optimize the power consumption of System on Chip.Adjusting supply voltage, frequency and body bias parameters allows multiple operating points, which must satisfy the constraints of functionality and performance. This work focuses initially at design time, proposing a method to optimize the placement of these operating points. An analytical solution to maximize power savings achieved through the use of several operating points is provided. The second important contribution of this work is a method based on convexity concept to dynamically manage the supply voltage, the frequency and the body bias voltage so as to optimize the energy efficiency. The experimental results based on real circuits show average power savings reaching 35%
Wang, Cai-Jia, and 王才嘉. "The scaling effects on the CMOS compatible bipolar transistor used in the low-noise, low offset voltage CMOS amplifier." Thesis, 1989. http://ndltd.ncl.edu.tw/handle/64237608835914195262.
Повний текст джерелаFitsilis, Michael [Verfasser]. "Scaling of the ferroelectric field effect transistor and programming concepts for non-volatile memory applications / vorgelegt von Michael Fitsilis." 2005. http://d-nb.info/975146378/34.
Повний текст джерелаMoradi, Maryam. "Vertical Thin Film Transistors for Large Area Electronics." Thesis, 2008. http://hdl.handle.net/10012/3937.
Повний текст джерелаKurakula, Sidda Reddy. "Studies On The Electrical Properties Of Titanium Dioxide Thin Film Dielectrics For Microelectronic Applications." Thesis, 2007. http://hdl.handle.net/2005/484.
Повний текст джерелаChen, Chun Yu, and 陳俊佑. "Study on Scaling Capability of Nanowire Transistors." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/06479724790748063412.
Повний текст джерела國立宜蘭大學
電子工程學系碩士班
97
The thesis mainly focuses on the scaling capability of the nanowire transistors, and the impact of quantum effect is investigated via physical 3D numerical simulation. We analyze the channel scalability and discuss how to control the short channel effects of nanowire, FinFET and Tri-Gate transistors characteristics. Several emerging patterning processes have been proposed in recent years. Due to device size scaling, quantum mechanical effects become significant. The physical quantum mechanical model is one of key figures for 3D numerical device simulation. The quantum mechanical model is analytically studied and compared with classical model. The characteristics of electron distributions on different surface orientations subject to film thickness and manufacturability of the nanowire device are investigated via 3D numerical simulation. We comprehensively examine the three types of multiple-gate structures including nanowire, FinFET and Tri-Gate devices. In order to evaluate the device performance when considering speed for logic application, the thesis also focuses on CV/Ion for CMOS inverter with advanced multiple-gate devices.
Chen, Chin-Yi, and 陳沁儀. "Scaling Issues in Trigate GaN Nanowire Transistors." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/67345808631375742762.
Повний текст джерела國立臺灣大學
光電工程學研究所
100
This thesis analyzes the scalability of nitride-based nanowire high electron mobility transistors (HEMTs). The positive polarization charge between the AlGaN and GaN interface induces high density of electron which also known as the two dimensional electron gate (2DEG). With the 2DEG, the device does not need high n-type doping to increase the electron density in the channel. Therefore, the mobility can reach a high value due to less impurity scattering in the device. We use a fully three dimensional(3D) self-consistent nite element model to solves drift-di usion and Poisson equations and obtains the electrical properties in the device with 3D structure. In the scaling issue of Si-based transistors, the structure of silicon on insulator(SOI) and the FINFET are two common ways to suppress the short channel e ect (SCE). In the GaN-based transistor, AlGaN and AlInN back barrier, similar to the structure of SOI, can suppress the SCE. How- ever, the negative polarization charge at the interface of the GaN channel and the back barrier reduces the saturation current. In this thesis, we discuss the GaN-HEMT in a 3D tri-gate struc- ture, which is similar to the structure of FINFET. The I-V curve, vtransconductance (gm), sub-threshold swing, and drain induce barrier lowering, fT are discussed. The tri-gate structure can well suppress the SCE when the wire width is reduced. However, the fT decreases at the same time due to the e ect of the lateral gate. To optimize this tri-gate structure, we replace the AlGaN top insulator with AlInN to increase the 2DEG in the channel. Furthermore, we reduce the distance between drain and source to reduce the channel resistance. With a smaller channel resistance in the channel, a higher fT can be obtained. In sum, the optimize structure can suppress the SCE without sacri cing the fT .
Hoppe, Arne. "Scaling limits and Megahertz operation in thiophene-based field effect transistors /." 2007. http://www.jacobs-university.de/phd/files/1210172114.pdf.
Повний текст джерелаTsai, Chan-Yi, and 蔡展壹. "Evaluation of the Various Scaling Routes on Novel Poly-Si Junctionless Transistors." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/t3jn55.
Повний текст джерела國立交通大學
電子物理系所
106
For the demands and developments of semiconductor industry, the device dimension is scaled down continuously. In this dissertation, we investigate the pros and cons of the multi-gate poly-Si junctionless transistors in the various scaling routes. The routes are conventionally physical scaling, novel electrical scaling, and ultimate scaling, respectively. In the conventional physical scaling route, thinning down the channel of junctionless transistor is able to enhance the switching ability, but its series resistance arise to cause the current declines as the channel dimension scaling down. In the electrical scaling route, the inverse doped poly-Si body is inserted under the channel. The P/N junction supports the volume depletion to scale the channel down, but there is dopant diffusion after the subsequent thermal process. Therefore, we also investigate the impacts of the insertion of a nano-scale dielectric for suppressing diffusion. Consequently, the switching characteristic and current level actually are improved by electrical scaling, but the channel and body concentration is a critical factor to the electrical characteristic. However, too heavy doping concentration leading serious leakage and VT roll-off as channel length increases are still unsolved issues, which make the devices hard to apply on the real circuits. Body bias can adjust the electrical characteristic efficiently (ϒ=0.306) and extend the device application. In the ultimate scaling route, the device combined with the GAA architecture and nano-scale channels shows the superior S.S (≈66mV/dec). and current level (ION ≈79 µA/µm). As a result, the GAA architecture is still the best choice in the various scaling routes.
Wang, Wei-Chun, and 王瑋駿. "Impact of Ferroelectric HfZrOx Gate-Stack Scaling on N-type and P-type Negative Capacitance Transistors." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/x7vcf2.
Повний текст джерела國立交通大學
光電系統研究所
108
In recent years, with the flourish of smart phones, Internet of Things (IoT) and other related applications, low-power consumption electronic devices are in urgent need. Tunneling FETs (TFETs) and Negative Capacitances (NCFETs) are been investigated to be different from traditional Si-based FETs to break through the thermophysical limitation of less than 60mV/decade subthershold (SS), allowing the transistors to turn on the devices with less biasing. Since the TFET has a shortage that Ion is hard to improve and a tradeoff effect with Ioff, the NC-FETs with negative capacitance effect have the potential to develop a low-power consumption transistor device. The new ferroelectric materials retain the advantages, strong polarization performances, of traditional ferroelectric materials (SBT, PZT...) and overcome the problems that traditional ferroelectric materials cannot be shrunk. However, new challenges have been emerged due to the influence of miniaturization. The thinner the overall buffer is, the thinner the buffer layer and the ferroelectric layer are, resulting in a stronger ferroelectric material polarization, and a leakage current is increased at the interface. In this master thesis, we investigate ferroelectric HfZrO material which is the most mature HfO2-based ferroelectric application so far. First, we investigate the influences on ferroelectricity of different Zr dopant content. The high dopant content induces stronger ferroelectricity. However, when Zr dopant content too high, it will result in zirconium diffusion and further induce high leakage current. Therefore, the appropriate Zr dopant content not only can keep the strong ferroelectricity but also avoid high leakage current issue. Next, we try to scale the HfZrO thin films, finding that the thickness at 7nm can remain ferroelectricity due to the grain size effect. Last, in order to study relationship with the Zr diffusion and the interfacial layer, we fabricate different thickness of interlayer. Although thin interlayer is prone to Zr diffusion and lead higher leakage current, it exhibits good performance on gate controllability. When thicken the interlayer, the obvious depolarization will degrade the gate controllability on ferroelectric gate-stack and further induce increasing Ioff in MOSFET apparently. As a result, the investigation on Zr dopant content in HfZrO NC-FET, ferroelectric gate-stack scaling and the thickness of interlayer effect, we can sum up the optimization of HfZrO NC-FET. With the success of bipolar N-type and P-type NC-FET, the investigation will help the future integration of low-power CMOS circuit technology.