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Статті в журналах з теми "Transistor scaling"
Ahmed Mohammede, Arsen, Zaidoon Khalaf Mahmood, and Hüseyin Demirel. "Study of finfet transistor: critical and literature review in finfet transistor in the active filter." 3C TIC: Cuadernos de desarrollo aplicados a las TIC 12, no. 1 (March 31, 2023): 65–81. http://dx.doi.org/10.17993/3ctic.2023.121.65-81.
Повний текст джерелаDatta, Suman, Wriddhi Chakraborty, and Marko Radosavljevic. "Toward attojoule switching energy in logic transistors." Science 378, no. 6621 (November 18, 2022): 733–40. http://dx.doi.org/10.1126/science.ade7656.
Повний текст джерелаSARKOZY, S., X. MEI, W. YOSHIDA, P. H. LIU, M. LANGE, J. LEE, Z. ZHOU, et al. "AMPLIFIER GAIN PER STAGE UP TO 0.5 THz USING 35 NM InP HEMT TRANSISTORS." International Journal of High Speed Electronics and Systems 20, no. 03 (September 2011): 399–404. http://dx.doi.org/10.1142/s0129156411006684.
Повний текст джерелаReid, Dave, Campbell Millar, Scott Roy, Gareth Roy, Richard Sinnott, Gordon Stewart, Graeme Stewart, and Asen Asenov. "Enabling cutting-edge semiconductor simulation through grid technology." Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences 367, no. 1897 (June 28, 2009): 2573–84. http://dx.doi.org/10.1098/rsta.2009.0031.
Повний текст джерелаFazio, Al. "Flash Memory Scaling." MRS Bulletin 29, no. 11 (November 2004): 814–17. http://dx.doi.org/10.1557/mrs2004.233.
Повний текст джерелаAngelov, George V., Dimitar N. Nikolov, and Marin H. Hristov. "Technology and Modeling of Nonclassical Transistor Devices." Journal of Electrical and Computer Engineering 2019 (November 3, 2019): 1–18. http://dx.doi.org/10.1155/2019/4792461.
Повний текст джерелаIeong, Meikei, Vijay Narayanan, Dinkar Singh, Anna Topol, Victor Chan, and Zhibin Ren. "Transistor scaling with novel materials." Materials Today 9, no. 6 (June 2006): 26–31. http://dx.doi.org/10.1016/s1369-7021(06)71540-1.
Повний текст джерелаCastañer, Luis M., Ramon Alcubilla, and Anna Benavent. "Bipolar transistor vertical scaling framework." Solid-State Electronics 38, no. 7 (July 1995): 1367–71. http://dx.doi.org/10.1016/0038-1101(94)00254-d.
Повний текст джерелаJacob, Ajey P., Ruilong Xie, Min Gyu Sung, Lars Liebmann, Rinus T. P. Lee, and Bill Taylor. "Scaling Challenges for Advanced CMOS Devices." International Journal of High Speed Electronics and Systems 26, no. 01n02 (February 17, 2017): 1740001. http://dx.doi.org/10.1142/s0129156417400018.
Повний текст джерелаChen, Zhuo, Huilong Zhu, Guilei Wang, Qi Wang, Zhongrui Xiao, Yongkui Zhang, Jinbiao Liu, et al. "High-Quality Recrystallization of Amorphous Silicon on Si (100) Induced via Laser Annealing at the Nanoscale." Nanomaterials 13, no. 12 (June 15, 2023): 1867. http://dx.doi.org/10.3390/nano13121867.
Повний текст джерелаДисертації з теми "Transistor scaling"
Chen, Qiang. "Scaling limits and opportunities of double-gate MOSFETS." Diss., Georgia Institute of Technology, 2003. http://hdl.handle.net/1853/15011.
Повний текст джерелаDeshpande, Veeresh. "Scaling Beyond Moore: Single Electron Transistor and Single Atom Transistor Integration on CMOS." Phd thesis, Université de Grenoble, 2012. http://tel.archives-ouvertes.fr/tel-00813508.
Повний текст джерелаWoo, Raymond. "Band-to-band tunneling transistor scaling and design for low-power logic applications /." May be available electronically:, 2009. http://proquest.umi.com/login?COPT=REJTPTU1MTUmSU5UPTAmVkVSPTI=&clientId=12498.
Повний текст джерелаYuan, Jiahui. "Cryogenic operation of silicon-germanium heterojunction bipolar transistors and its relation to scaling and optimization." Diss., Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/33837.
Повний текст джерелаSchuette, Michael L. "Advanced processing for scaled depletion and enhancement-mode AlGaN/GaN HEMTs." The Ohio State University, 2010. http://rave.ohiolink.edu/etdc/view?acc_num=osu1275524410.
Повний текст джерелаAhmed, Adnan. "Study of Low-Temperature Effects in Silicon-Germanium Heterojunction Bipolar Transistor Technology." Thesis, Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/7227.
Повний текст джерелаConnor, Mark Anthony. "Design of Power-Scalable Gallium Nitride Class E Power Amplifiers." University of Dayton / OhioLINK, 2014. http://rave.ohiolink.edu/etdc/view?acc_num=dayton1405437893.
Повний текст джерелаNicoletti, Talitha. "Estudo de transistores UTBOX SOI não auto-alinhados como célula de memória." Universidade de São Paulo, 2013. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-10072014-012728/.
Повний текст джерелаThe main topic of this work is the study of extensionless UTBOX SOI transistors, also called underlapped devices, applied as a single transistor floating body RAM (1T-FBRAM single transistor floating body access memory). The electrical characterization of the devices was performed through static and dynamic experimental data and two dimensional simulations were implemented to confirm the obtained results. In the literature, different methods to write and read the data 1 can be found but in order to improve the dynamic parameters of the memories, as retention time and sense margin and still allows the scaling of fully depleted devices, the BJT (Bipolar Junction Transistor) method is used in this work. One of the biggest issues to meet the specifications for future generations of 1T-DRAM cells is the retention time that scales together with the channel length. In order to overcome this issue or at least slow it down, in this work, we present for the first time, a study about the retention time and sense margin dependence of the channel length where it was possible to observe that these dynamic parameters can be optimized through the back gate bias and kept constant for channel lengths higher than 50 nm for extensionless devices and 80 nm for standard ones. However, it was also observed that there is a minimal channel length which depends of the source/drain junctions, i.e. 30 nm for extensionless and 50 nm for standard devices in the sense that for shorter channel lengths than these ones, there is no room for optimization degrading the performance of the memory cell. The mechanism behind the dynamic parameters degradation was identified and attributed to the GIDL current amplification by the lateral bipolar transistor with narrow base. Simulations confirmed this effect where higher generation rates near the junctions were presented only when the band-toband- tunneling adjustment was considered (bbt.kane model). Comparing the performance of standard and extensionless devices in both digital and analog electrical parameters and also in memory applications, it was found that extensionless devices present better performance since they reach faster switching which means lower subthreshold slope; less influence of the electrical field in the channel charges; less variation of the threshold voltage even increasing the temperature. Furthermore, it was seen that the gate length can be further scaled using underlap junctions since these devices are less susceptible to the GIDL current, presenting less electric field and generation rate near the source/drain junctions and reach a retention time of around 4 ms and sense margin of 71A/m. According to the International Technology Roadmap for Semiconductor of 2011, the retention time for the existing DRAM is around 64 ms. In order to increase the retention time of the 1T-DRAMs to values close to 64 ms it is recommended the use of extensionless devices and also the substitution of silicon by materials with higher band gap, i.e., gallium arsenide and siliconcarbon, which makes difficult the electron tunneling therefore, decreasing the GIDL.
Murali, Raghunath. "Scaling opportunities for bulk accumulation and inversion MOSFETs for gigascale integration." Diss., Available online, Georgia Institute of Technology, 2004:, 2004. http://etd.gatech.edu/theses/submitted/etd-02132004-173432/unrestricted/murali%5FRaghunath%5F405%5F.pdf.
Повний текст джерелаHess, Dennis, Committee Member; Meindl, James, Committee Chair; Allen, Phillip, Committee Member; Cressler, John, Committee Member; Davis, Jeffrey, Committee Member. Vita. Includes bibliographical references (leaves 108-119).
Hoppe, Arne [Verfasser]. "Scaling limits and Megahertz operation in thiophene-based field effect transistors / Arne Hoppe." Bremen : IRC-Library, Information Resource Center der Jacobs University Bremen, 2008. http://d-nb.info/1034966928/34.
Повний текст джерелаКниги з теми "Transistor scaling"
F, Eastman Lester, Society of Photo-optical Instrumentation Engineers., Society of Vacuum Coaters, and SPIE Symposium on Advances in Semiconductors and Superconductors: Physics Toward Device Applications (1990 : San Diego, Calif.), eds. High-speed electronics and device scaling: 18-19 March 1990, San Diego, California. Bellingham, Wash., USA: SPIE, 1990.
Знайти повний текст джерелаThompson, Scott, Faran Nouri, Wen-Chin Lee, and Wilman Tsai. Transistor Scaling : Volume 913: Methods, Materials and Modeling. University of Cambridge ESOL Examinations, 2014.
Знайти повний текст джерелаTransistor Scaling: Methods, Materials and Modeling: Symposium Held April 18-19, 2006, San Francisco, California, U.S.A. (Materials Research Society Symposium Proceedings). Materials Research Society, 2006.
Знайти повний текст джерелаAshraf, Nabil Shovon, Shawon Alam, and Mohaiminul Alam. New Prospects of Integrating Low Substrate Temperatures with Scaling-Sustained Device Architectural Innovation. Springer International Publishing AG, 2016.
Знайти повний текст джерелаAshraf, Nabil Shovon, Shawon Alam, and Mohaiminul Alam. New Prospects of Integrating Low Substrate Temperatures with Scaling-Sustained Device Architectural Innovation. Morgan & Claypool Publishers, 2016.
Знайти повний текст джерелаAshraf, Nabil Shovon, Shawon Alam, and Mohaiminul Alam. New Prospects of Integrating Low Substrate Temperatures with Scaling-Sustained Device Architectural Innovation. Morgan & Claypool Publishers, 2016.
Знайти повний текст джерелаЧастини книг з теми "Transistor scaling"
Julien, Levisse Alexandre Sébastien, Xifan Tang, and Pierre-Emmanuel Gaillardon. "Innovative Memory Architectures Using Functionality Enhanced Devices." In Emerging Computing: From Devices to Systems, 47–83. Singapore: Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-16-7487-7_3.
Повний текст джерелаChaudhry, Amit. "Scaling of a MOS Transistor." In Fundamentals of Nanoscaled Field Effect Transistors, 1–24. New York, NY: Springer New York, 2013. http://dx.doi.org/10.1007/978-1-4614-6822-6_1.
Повний текст джерелаLiu, T. J. K., and L. Chang. "Transistor Scaling to the Limit." In Into the Nano Era, 191–223. Berlin, Heidelberg: Springer Berlin Heidelberg, 2009. http://dx.doi.org/10.1007/978-3-540-74559-4_8.
Повний текст джерелаSkotnicki, T., and F. Boeuf. "Optimal Scaling Methodologies and Transistor Performance." In High Dielectric Constant Materials, 143–94. Berlin, Heidelberg: Springer Berlin Heidelberg, 2005. http://dx.doi.org/10.1007/3-540-26462-0_6.
Повний текст джерелаTigelaar, Howard. "The Incredible Shrinking IC: Part 2 FEOL Isolation Scaling and Transistor Scaling." In How Transistor Area Shrank by 1 Million Fold, 201–26. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-40021-7_10.
Повний текст джерелаAmiri, Iraj Sadegh, and Mahdiar Ghadiry. "Introduction on Scaling Issues of Conventional Semiconductors." In Analytical Modelling of Breakdown Effect in Graphene Nanoribbon Field Effect Transistor, 1–7. Singapore: Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-6550-7_1.
Повний текст джерелаJ.M. Veendrick, Harry. "Geometrical-, Physical- and Field-Scaling Impact on MOS Transistor Behaviour." In Nanometer CMOS ICs, 45–72. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-47597-4_2.
Повний текст джерелаVeendrick, H. J. M. "Geometrical-, physical- and field-scaling impact on MOS transistor behaviour." In Nanometer CMOS ICs, 57–91. Dordrecht: Springer Netherlands, 2008. http://dx.doi.org/10.1007/978-1-4020-8333-4_2.
Повний текст джерелаPrasher, Rakesh, Devi Dass, and Rakesh Vaid. "Novel Attributes in Scaling Issues of an InSb-Nanowire Field-Effect Transistor." In Physics of Semiconductor Devices, 677–79. Cham: Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-03002-9_174.
Повний текст джерелаNi, Haiyan, Xiaolei Sheng, and Jianping Hu. "Voltage Scaling for Adiabatic Register File Based on Complementary Pass-Transistor Adiabatic Logic." In Lecture Notes in Electrical Engineering, 39–46. Berlin, Heidelberg: Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-19706-2_6.
Повний текст джерелаТези доповідей конференцій з теми "Transistor scaling"
Yang, Fu-Liang, Hou-Yu Chen, and Chang-Yun Chang. "SOI Transistor/Power Scaling and Scaling-Strengthened Strain." In 2004 International Conference on Solid State Devices and Materials. The Japan Society of Applied Physics, 2004. http://dx.doi.org/10.7567/ssdm.2004.c-7-1.
Повний текст джерелаChen, Tianbing, Tzung-Yin Lee, Justin Allum, and Mike McPartlin. "The thermal scaling: From transistor to array." In 2014 IEEE Radio Frequency Integrated Circuits Symposium (RFIC). IEEE, 2014. http://dx.doi.org/10.1109/rfic.2014.6851675.
Повний текст джерелаTadayon, Saied, Bijan Tadayon, and Lester F. Eastman. "Effect of InAlAs emitter on the microwave performance of InAlAs/InGaAs abrupt npn heterojunction bipolar transistor." In High-Speed Electronics and Device Scaling, edited by Lester F. Eastman. SPIE, 1990. http://dx.doi.org/10.1117/12.20909.
Повний текст джерелаKim, Michael E. "GaAs heterojunction bipolar transistor device and IC technology for high-performance analog/microwave, digital, and A/D conversion applications." In High-Speed Electronics and Device Scaling, edited by Lester F. Eastman. SPIE, 1990. http://dx.doi.org/10.1117/12.20903.
Повний текст джерелаVan Der Bent, G., A. P. De Hek, and F. E. Van Vliet. "EM - Based GaN Transistor Small-Signal Model Scaling." In 2018 13th European Microwave Integrated Circuits Conference (EuMIC). IEEE, 2018. http://dx.doi.org/10.23919/eumic.2018.8539925.
Повний текст джерелаKuhn, Kelin J. "CMOS transistor scaling past 32nm and implications on variation." In 2010 21st Annual IEEE/SEMI Advanced Semiconductor Manufacturing Conference (ASMC). IEEE, 2010. http://dx.doi.org/10.1109/asmc.2010.5551461.
Повний текст джерелаWoo, Raymond, H. Y. Serene Koh, Caner Onal, P. B. Griffin, and James D. Plummer. "BTBT Transistor Scaling: Can they be Competitive with MOSFETs?" In 2008 66th Annual Device Research Conference (DRC). IEEE, 2008. http://dx.doi.org/10.1109/drc.2008.4800741.
Повний текст джерелаTian, H., Asanga H. Perera, D. O'Meara, H. De, C. K. Subramanian, P. Rehmann, James D. Hayden, and Norm Herr. "Silicon bipolar transistor scaling for advanced BiCMOS SRAM applications." In Microelectronic Manufacturing, edited by Mark Rodder, Toshiaki Tsuchiya, David Burnett, and Dirk Wristers. SPIE, 1997. http://dx.doi.org/10.1117/12.284616.
Повний текст джерелаCao, Q. "Carbon Nanotube Transistor Technology for Scaling Beyond Si CMOS." In 2016 International Conference on Solid State Devices and Materials. The Japan Society of Applied Physics, 2016. http://dx.doi.org/10.7567/ssdm.2016.j-3-01.
Повний текст джерелаShakil, S. M., and Muhammad Sana Ullah. "Analysis of HCD Effects for NMOS Transistor with Technology Scaling." In SoutheastCon 2023. IEEE, 2023. http://dx.doi.org/10.1109/southeastcon51012.2023.10115193.
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