Дисертації з теми "Thin Film Transistors (TFT)"
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Hein, Moritz. "Organic Thin-Film Transistors." Doctoral thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2017. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-167894.
Повний текст джерелаDong, Hanpeng. "Microcrystalline silicon based thin film transistors fabricated on flexible substrate." Thesis, Rennes 1, 2015. http://www.theses.fr/2015REN1S173/document.
Повний текст джерелаThis work deals with the development of microcrystalline silicon thin film transistors (TFTs) fabricated on flexible substrate at low temperature (T=180 °C). The first step of this work consists in studying the electrical stability of TFTs. The N-type TFTs fabricated on glass substrate are electrically stable under gate bias stress VGStress= +50V at T=50 °C. The threshold voltage shift (ΔVTH) was only 1.2 V during 4 hours. This electrical instability of TFTs is mainly due to carrier trapping inside the silicon nitride gate insulator. The second step of this work lies in the study of the mechanical behavior of the TFTs. Both tensile and compressive strains were applied on TFTs. The minimum curvature radius is r=1.5 mm for both tension and compression. The main limitation of TFTs comes from the mechanical strain εlimit of silicon nitride used as gate insulator of TFTs. Also, these TFTs are mechanically reliable: the variation of ION current was only 1% after 200 cycles mechanical bending. These results obtained open the way to the development of flexible electronics that can be folded in half.Finally, TFTs have been fabricated using different gate insulators in order to improve the mobility. Unfortunately, all the gate insulators used couldn’t improve mobility without sacrificing electrical stability of TFT. More detailed studies and complementary optimization of these gate insulators are necessary
Ho, Tsz Kin. "Design of TFT circuit and touchscreen electronics /." View abstract or full-text, 2009. http://library.ust.hk/cgi/db/thesis.pl?ECED%202009%20HO.
Повний текст джерелаNominanda, Helinda. "Amorphous silicon thin film transistor as nonvolatile device." Texas A&M University, 2008. http://hdl.handle.net/1969.1/86004.
Повний текст джерелаRossi, Leonardo. "Flexible oxide thin film transistors: fabrication and photoresponse." Master's thesis, Alma Mater Studiorum - Università di Bologna, 2017. http://amslaurea.unibo.it/14542/.
Повний текст джерелаFratelli, Ilaria. "Flexible oxide thin film transistors: device fabrication and kelvin probe force microscopy analysis." Master's thesis, Alma Mater Studiorum - Università di Bologna, 2017. http://amslaurea.unibo.it/13538/.
Повний текст джерелаJakob, Markus Prüfer. "Compact DC Modelling of Short-Channel Effects in Organic Thin-Film Transistors." Doctoral thesis, Universitat Rovira i Virgili, 2022. http://hdl.handle.net/10803/673905.
Повний текст джерелаLos transistores orgánicos de capa fina (TFT) son dispositivos prometedores para las pantallas flexibles de matriz activa y los conjuntos de sensores, ya que pueden fabricarse a temperaturas de proceso relativamente bajas y, por tanto, no sólo en vidrio, sino también en sustratos poliméricos. Para mejorar el rendimiento dinámico de los dispositivos y circuitos TFT, una reducción agresiva de la longitud de los canales provoca efectos extrínsecos en los dispositivos que tienen que ser capturados por modelos compactos. Esta tesis presenta modelos analíticos, basados en la física, de la degradación de la pendiente subumbral, el roll-off del voltaje umbral y el efecto DIBL en TFTs coplanares y escalonados que pueden ser implementados en cualquier modelo compacto de corriente continua arbitrario que esté definido por el voltaje umbral y la pendiente subumbral. Por lo tanto, la ecuación diferencial de Laplace se resuelve para la geometría coplanar y escalonada aplicando la transformación Schwarz-Christoffel. Las soluciones del potencial sirven de base para la definición de las ecuaciones del modelo. Además, se desarrollan modelos compactos de las barreras Schottky dependientes de la polarización en las interfaces fuente/semiconductor y drenador/semiconductor en los TFT coplanares y escalonados, que modelan la inyección y la eyección de portadores de carga, respectivamente, como corriente de emisión termoiónica
Organic thin-film transistors (TFTs) are promising devices for flexible active-matrix displays and sensor arrays, since they can be fabricated at relatively low process temperatures and thus not only on glass, but also on polymeric substrates. In order to improve the dynamic TFT and circuit performance, an aggressive reduction of the channel length causes extrinsic de-vice effects that have to be captured by compact models. This dissertation presents analytical, physics-based models of the subthreshold-swing degra-dation, the thresholdvoltage roll-off and DIBL effects in coplanar and staggered TFTs that can be implemented in any arbitrary compact dc model that are defined by the threshold voltage and the subthreshold swing. Therefore, Laplace’s differential equation is solved for the coplanar and staggered geometry by applying the Schwarz-Christoffel transformation. The potential solutions serve as a basis for the definition of the model equations. Further-more, compact models of the biasdependent Schottky barriers at the source/semiconductor and drain/semiconductor interfaces in coplanar and staggered TFTs are derived, which model the charge carriers injection and ejection, respectively, as thermionic emission cur-rent. Thereby, in case of the source barrier, the Schottky barrier lowering effect due to im-age charges is captured and therefore, an analytical expression of the electric field at the source barrier is derived.
Dosev, Dosi Konstantinov. "Fabrication, characterisation and modelling of nanocrystalline silicon thin-film transistors obtained by hot-wire chemical vapour deposition." Doctoral thesis, Universitat Politècnica de Catalunya, 2003. http://hdl.handle.net/10803/6324.
Повний текст джерелаIn this work, thin-film transistors (TFTs) were fabricated using nanocrystalline hydrogenated silicon film (nc-Si:H), deposited by HWCVD over thermally oxidized silicon wafer. The employed substrate temperature during the deposition process permits inexpensive materials as glasses or plastics to be used for various applications in large-area electronics. The deposition rate was about one order of magnitude higher than in other conventionally employed techniques. The deposited nc-Si:H films show good uniformity and reproducibility. The films consist of vertically grown columnar grains surrounded by amorphous phase. The columnar grains are thinner at the bottom (near the oxide interface) and thicker at the top of the film. Chromium layer was evaporated over the nc-Si:H in order to form drain and source contacts. Using photolithography techniques, two types of samples were fabricated. The first type (simplified) was with the chromium contacts directly deposited over the intrinsic nc-Si:H layer. No dry etching was involved in the fabrication process of this sample. The transistors on the wafer were not electrically separated from each other. Doped n+ layer was incorporated at the drain and source contacts in the second type of samples (complete samples). Dry etching was employed to eliminate the nc-Si:H between the TFTs and to isolate them electrically from each other.
The electrical characteristics of both types of nc-Si:H TFTs were similar to a-Si:H based TFTs. Nevertheless, some significant differences were observed in the characteristics of the two types of samples. The increasing of the off-current in the simplified structure was eliminated by the n+ layer in the second type of samples. This led to the improving of the on/off ratio. The n+ layer also eliminated current crowding of the output characteristics. On the other hand, the subthreshold slope, the threshold voltage and the density of states were slightly deteriorated in the samples with incorporated n+ layer. Surface states created by the dry etching could be a possible reason. Other cause could be a bad quality of the nc-Si:H/SiO2 interface. The TFTs with incorporated n+ contact layer and electrically separated on the wafer were used in the further studies of stability and device modelling.
The nc-Si:H TFTs were submitted under prolonged positive and negative gate bias stress in order to study their stability. We studied the influence of the stressing time and voltage on the transfer characteristics, threshold voltage, activation energy and density of states. The threshold voltage increased under positive gate bias stress and decreased under negative gate bias stress. After both positive and negative stresses, the threshold voltage recovered its initial values without annealing. This behaviour indicated that temporary charge trapping in the channel/gate insulator interface is the responsible process for the device performance under stress. Measurements of space-charge limited current confirmed that bulk states were not affected by the positive nor by negative stress.
Analysis of the activation energy and the density of states gave more detailed information about the physical processes taking place during the stress. Typical drawback of the nc-Si:H films grown by HWCVD with tungsten (W) filament is the bad quality of the bottom, initially grown, interfacial layer. It is normally amorphous and porous. We assume that this property of the nc-Si:H film is determining for charge trapping and the consecutive temporary changes of the TFT's characteristics. On the other hand, the absence of defect-state creation during the gate bias stress demonstrates that the nc-Si:H films did not suffer degradation under the applied stress conditions.
The electrical characteristics and the operational regimes of the nc-Si:H TFTs were studied in details in order to obtain the best possible fit using the Spice models for a-Si:H and poly-Si TFTs existing until now. The analysis of the transconductance gm showed behaviour typical for a-Si:H TFTs at low gate voltages. In contrast, at high gate voltages unexpected increasing of gm was observed, as in poly-Si TFTs. Therefore, it was impossible to fit the transfer and output characteristics with the a-Si:H TFT model neither with poly-Si TFT model.
We performed numerical simulations using the Silvaco's Atlas simulator of semiconductor devices in order to understand the physical parameters, responsible for the device behaviour. The simulations showed that the reason for this behaviour is the density of acceptor-like states, which situates the properties of nc-Si:H TFTs between the amorphous and the polycrystalline transistors. Taking into account this result, we performed analysis of the concentrations of the free and the trapped carriers in nc-Si:H layer. It was found that nc-Si:H operates in transitional regime between above-threshold and crystalline-like regimes. This transitional regime was predicted earlier, but not experimentally observed until now. Finally, we introduced new equations and three new parameters into the existing a-Si TFTs model in order to account for the transitional regime. The new proposed model permits the shapes of the transconductance, the transfer and the output characteristics to be modelled accurately.
Noring, Martin. "To automatically estimate the surface area coverage of carbon nanotubes on thin film transistors with image analysis : Bachelor’s degree project report." Thesis, Uppsala universitet, Institutionen för teknikvetenskaper, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-157168.
Повний текст джерелаZhu, Lei. "Modeling of a-Si:H TFT I-V Characteristics in the Forward Subthreshold Operation." Thesis, University of Waterloo, 2005. http://hdl.handle.net/10012/868.
Повний текст джерелаElzwawi, Salim Ahmed Ali. "Cathodic Arc Zinc Oxide for Active Electronic Devices." Thesis, University of Canterbury. Electrical and Computer Engineering, 2015. http://hdl.handle.net/10092/10852.
Повний текст джерелаUllah, Syed Shihab. "Solution Processing Electronics Using Si6 H12 Inks: Poly-Si TFTs and Co-Si MOS Capacitors." Thesis, North Dakota State University, 2011. https://hdl.handle.net/10365/28902.
Повний текст джерелаGrant, David James. "Bottom-Gate TFTs With Channel Layer Deposited by Pulsed PECVD." Thesis, University of Waterloo, 2004. http://hdl.handle.net/10012/805.
Повний текст джерелаLindner, Thomas. "Organische Feldeffekt-Transistoren: Modellierung und Simulation." Doctoral thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2005. http://nbn-resolving.de/urn:nbn:de:swb:14-1116323078792-49660.
Повний текст джерелаLindner, Thomas. "Organische Feldeffekt-Transistoren: Modellierung und Simulation." Doctoral thesis, Technische Universität Dresden, 2004. https://tud.qucosa.de/id/qucosa%3A24492.
Повний текст джерелаAbusabee, K. M. "Thin film engineering for transparent thin film transistors." Thesis, Nottingham Trent University, 2014. http://irep.ntu.ac.uk/id/eprint/127/.
Повний текст джерелаCheng, Xiang. "TFTs circuit simulation models and analogue building block designs." Thesis, University of Cambridge, 2018. https://www.repository.cam.ac.uk/handle/1810/271853.
Повний текст джерелаZhu, Wen Wei. "Organic thin film transistors." Thesis, McGill University, 2003. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=19597.
Повний текст джерелаPanda, Durga Prasanna. "Nanocrystalline silicon thin film transistors." [Ames, Iowa : Iowa State University], 2006.
Знайти повний текст джерелаQian, Feng. "Thin film transistors in polysilicon /." Full text open access at:, 1988. http://content.ohsu.edu/u?/etd,162.
Повний текст джерелаBauza, M. "Nanocrystalline silicon thin film transistors." Thesis, University College London (University of London), 2013. http://discovery.ucl.ac.uk/1385744/.
Повний текст джерелаLloyd, Giles Christian Rome. "Novel conjugated polymer thin film transistors." Thesis, University of Liverpool, 2000. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.399071.
Повний текст джерелаStott, J. E. "Organic thin film transistors : integration challenges." Thesis, University College London (University of London), 2013. http://discovery.ucl.ac.uk/1393282/.
Повний текст джерелаHerlogsson, Lars. "Electrolyte-Gated Organic Thin-Film Transistors." Doctoral thesis, Linköpings universitet, Institutionen för teknik och naturvetenskap, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-69636.
Повний текст джерелаBreban, Mihaela. "Photocurrent spectroscopy of pentacene thin film transistors." College Park, Md. : University of Maryland, 2006. http://hdl.handle.net/1903/3973.
Повний текст джерелаThesis research directed by: Physics. Title from t.p. of PDF. Includes bibliographical references. Published by UMI Dissertation Services, Ann Arbor, Mich. Also available in paper.
Chen, Y. "Novel polysilicon high voltage thin film transistors." Thesis, University of Cambridge, 1998. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.597542.
Повний текст джерелаNausieda, Ivan Alexander. "Pentacene integrated thin-film transistors and circuits." Thesis, Massachusetts Institute of Technology, 2009. http://hdl.handle.net/1721.1/55119.
Повний текст джерелаPage 179 blank. Cataloged from PDF version of thesis.
Includes bibliographical references.
Organic semiconductors offer the potential of large-area, mechanically flexible electronics due to their low processing temperatures. We have developed a near-room-temperature (< 95°C) process flow to fabricate pentacene integrated organic thin-film transistors (OTFTs) compatible with plastic substrates such as polyethylene terephthalate (PET). Integration of inkjet printed organic photoconductors (OPDs) based on titanyl pthalocyanine with OTFTs is demonstrated for the first time in an integrated process. Using the OTFT as a switch in series with an OPD, a pixel circuit was designed and measured, in addition to a proof-of-concept 4x4 active matrix imager. The individual pixels were measured to have a responsivity of 6x10-5 A/W, and a pixel on/off conductance ratio of 880, both at an irradiance of 5 mW/cm 2. The imager uses a 25 V power supply and was shown to correctly image a "T" pattern after 1st order calibration. A model for the current-voltage characteristics based upon amorphous silicon models was implemented in MATLAB to investigate design trade-offs in organic digital circuits. A dual threshold voltage process is suggested to enable area-efficient zero-VGS current sources. The area and power savings of this approach is discussed compared to a single VT process. We also motivate the necessity for lowering the power supply, both for area savings and improvement in circuit lifetime due to reduction in bias stress effects. A process flow for a dual VT OTFT technology, enabled using two gate metals, is presented. By using a low work function metal (aluminum) and a high work function metal (platinum), we can obtain two threshold voltage devices.
(cont.) Devices were measured to be nominally identical, shifted by a VSG which we call the [Delta]VT. A [Delta]VT of 0.6 V was consistently observed over multiple wafer lots. This is the first demonstration of modification of OTFT VT by changing the gate work function. Area-minimized digital logic designed in the dual VT technology was demonstrated with a 3 V supply, the lowest supply reported for integrated OTFTs. In addition, we report some of the first analog organic integrated circuits, including a differential pair with differential gain of 23 dB and common-mode rejection ratio (CMRR) of 23 dB. A two-stage uncompensated operational amplifier was fabricated and measured to have an open-loop gain of 36 dB and unity gain frequency of 7.5 Hz. The op-amp has a unity gain-bandwidth product of 473 Hz while dissipating < 2 nW with a 5 V supply. The comparator uses 5 nW of power, and has an input offset of 200 mV. We show the frequency response of the op-amp and comparator are dominated by parasitic overlap capacitances. The parasitics of the zero-VGs load limits frequency response, and technological improvements to increase operating frequency are suggested. We motivate a self-aligned process flow, which uses a high optical density gate to serve as a mask layer. A backside exposure patterns the source/drain layer. It is demonstrated that the parasitic capacitances can be reduced by almost an order of magnitude, from 1 fF/jlm to 0.15 fF/jm. A method to improve carrier mobility is also presented. These process improvements have the potential to improve the switching speeds of organic circuits by more than two orders of magnitude.
by Ivan Alexander Nausieda.
Ph.D.
Marinkovic, Marko [Verfasser]. "Contact resistance effects in thin film solar cells and thin film transistors / Marko Marinkovic." Bremen : IRC-Library, Information Resource Center der Jacobs University Bremen, 2013. http://d-nb.info/1037014243/34.
Повний текст джерелаHein, Moritz. "Organic Thin-Film Transistors: Characterization, Simulation and Stability." Doctoral thesis, 2013. https://tud.qucosa.de/id/qucosa%3A28703.
Повний текст джерелаSinha, Rajat. "Reliability Physics of Thin-Film Transistors." Thesis, 2022. https://etd.iisc.ac.in/handle/2005/5682.
Повний текст джерелаNair, Aswathi R. "Textured Gate Thin Film Transistors and Circuits." Thesis, 2018. https://etd.iisc.ac.in/handle/2005/5415.
Повний текст джерелаMoradi, Maryam. "Vertical Thin Film Transistors for Large Area Electronics." Thesis, 2008. http://hdl.handle.net/10012/3937.
Повний текст джерела"Flexible Electronics Powered by Mixed Metal Oxide Thin Film Transistors." Doctoral diss., 2016. http://hdl.handle.net/2286/R.I.37039.
Повний текст джерелаDissertation/Thesis
Doctoral Dissertation Chemical Engineering 2016
Chiu, Yi-Ming, and 邱義銘. "Study of Drain Engineering in Polycrystalline Silicon Thin-Film-Transistors (Poly-Si TFT)." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/73013755227128557554.
Повний текст джерела國立臺灣科技大學
電子工程系
93
Polycrystalline silicon (polysilicon) thin film transistor (TFT) technology is emerging as a key technology for active matrix liquid crystal displays, allowing the integration of both active matrix and driving circuitry on the same substrate. However, conventional self-aligned polysilicon TFTs present several undesired effects in the electrical characteristics, including large off-state currents (leakage), kink effect and hot carrier instabilities. These effects are related to the presence of high electric fields at the drain junction and electric field near the drain region relief is essential. In this thesis, a novel poly-Si TFTs formed by using the large-angle-tilt-implanted-drain (LATID) scheme has been analyzed. First, three types TFTs with different drain structure were fabricated. They are the conventional single source/drain TFTs, the Lightly-Doped-Drain (LDD) TFTs and the large-angle-tilt-implanted drain (LATID) TFT. Next, the electrical characteristics of the LDD TFTs formed with different fabrication parameters such as LDD implantation doses and implanting energies were investigated. From the results, the relation between electrical characteristics of the LDD TFTs and such process parameters has been identified. In the same ways, electrical characteristics of the LATID TFTs were also studied. The LATID TFTs are formed with various LATID doses, various LATID energies and various LATID tilt angle. It is found that the implantation dose and implantation energy affected the performance of the LDD and the LATID TFTs. The implantation tilt angle of the LATID TFTs, moreover, has a most profound influence on the performance of the LATID TFTs. Finally, the electrical characteristics of the conventional single source/drain TFTs, the LDD TFTs and the LATID TFTs were compared. It could be found that the LATID TFTs achieve much smaller leakage than both the conventional single source/drain TFTs and the LDD TFTs, attributable to the more effective suppression of carrier emission via trap states. Moreover, the peak impact ionization current, associated with the device reliability, of the LATID TFTs is also significantly smaller than that of the conventional TFTs and the LDD TFTs. As a result, a poly-Si TFTs with excellent device characteristics and reliability can be implemented by simply using the LATID fabrication scheme.
Chun-DaTu and 塗俊達. "Design of a-Si:H Thin-Film Transistors Driving Circuit for TFT-LCD Applications." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/10539326124633239785.
Повний текст джерела"Design of NMOS and CMOS Thin Film Transistors and Application to Electronic Textiles." Doctoral diss., 2012. http://hdl.handle.net/2286/R.I.15126.
Повний текст джерелаDissertation/Thesis
Ph.D. Electrical Engineering 2012
Trivedi, Kruti. "Design, Fabrication and Characterization of ZnO based Thin Film Schottky Diodes and Transistors." Thesis, 2022. https://etd.iisc.ac.in/handle/2005/5821.
Повний текст джерелаHuang, San-Hao, and 黃三豪. "Optical Design of Novel Thin Film Transistor (TFT) Auto Laser Repair Equipment." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/43053139906065513961.
Повний текст джерела國立中興大學
精密工程學系所
98
Taiwan plays one of the world''s leading OEM panel production roles. However, in the fast booming panel industry, the ability to handle the defects on panels is not so strong. Especially when panel size gets larger and larger and shows defective symbols, the fixing technique will be of much importance. In response to this demand, the domestic companies are using laser technology to develop “ TFT Auto Laser Repair Equipment ”, but the machine core parts “ laser repair system ” needs being imported from U.S. and Japan, and the price is high. In light of this, the main contribution of this thesis is to design “ laser repair system ”, with using of optics principle and optics software. We successfully design and simulate the internal optical components and the overall system. Thus our country has built our own design capability. In addition to “ laser repair system ”, a unique technology called “ fast fiber optic ” has been developed, which can be used to judge material defects on panels immediately. When this novel technique is integrated with the auto repair machine, this improved equipment can have the benefits of reducing human inspection errors and enhance the repair yield.
Zhang, Jia-Wei, and 張家偉. "Structure Design of Polycrystalline Silicon Thin-Film-Transistors (Poly-Si TFTs)." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/43301490118093242811.
Повний текст джерела國立臺灣科技大學
電子工程系
97
Polycrystalline silicon thin-film-transistors (Poly-Si TFTs) have been widely used in various applications, such as static random memories (SRAMs), photodetector amplifier, scanner, and active matrix liquid crystal displays (AMLCDs). The electron field mobility of the ploy-Si TFT is larger than that of the amorphous-Si (a-Si) TFT, allowing the integration of both active matrix and driving circuitry on the same substrate. However, the conventional self-aligned poly-si TFT induces several undesired effects in the electrical characteristics, including large off-state currents (leakage), kink effect and hot carrier instabilities. These effects are related to the presence of high electric fields at the drain junction and electric field near the drain region relief is essential. In order to improve the electrical properties of devices and process simplification, in this thesis, poly-Si TFTs formed by using the large-angle-tilt-implantation-through-spacer (LATITS) scheme and the hetero-structure poly-SiGe/poly-Si TFT scheme have been analyzed. First, three types TFTs with different drain structures were fabricated. They are the conventional single source/drain TFT, the Lightly-Doped-Drain (LDD) TFT and the large-angle-tilt-implantation-through-spacer (LATITS) TFT. Next, the electrical characteristics of LATITS TFTs formed with different fabrication parameters such as implantation dose, implantation energy and implantation tilt angle were investigated. And then, the electrical characteristics of the conventional single source/drain TFT, the LDD TFT, and the LATITS TFT were compared. It could be found that the LATITS TFT causes much smaller leakage current than both the conventional single source/drain TFT and the LDD TFT, attributable to the more effective suppression of carrier emission via trap states. As a result, a poly-Si TFT with excellent device characteristics and reliability can be implemented by simply using the LATITS fabrication scheme. Finally, the hetero-structure poly-SiGe/poly-Si TFT was studied. By changing the thickness of poly-SiGe and ploy-Si as well as studying the influence of different drain voltages. At low drain bias, it’s found that a thinner channel layer has the better ability to suppress the bulk punch-through, and the threshold voltage is lower. In addition, because the band gap of the poly-SiGe TFT is smaller than that of the poly-Si TFT, thus the poly-SiGe TFT shows a larger driving current. However, the leakage current for the poly-Si TFT is lower than that for the poly-SiGe TFT. Hence, we can use the hetero-structure poly-SiGe/poly-Si TFT to get a higher driving current and a lower leakage current. On the other hand, the channel layer thickness of the poly-SiGe TFT and the poly-Si TFT is changed to study its influence on device characteristics. The on-current and the leakage current are obviously increased when the gate oxide thickness is decreased, due to the better gate control ability.
Wu, Min-Lin, and 吳旻霖. "Study of buried-channel Polycrystalline Silicon Thin-Film-Transistors (Poly-Si TFTs)." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/82rtt3.
Повний текст джерела國立臺灣科技大學
電子工程系
94
Poly-Si TFTs play an important role for panel fabrications, enhancing the integration of both active matrix and peripheral driving circuitry on the same substrate. However, poly-Si TFTs lead to some poor effects, like large off-state currents, kink effect and hot carrier effect. These effects are mainly due to the high lateral electric field intensity near the drain, so it is necessary to alleviate the electric field intensity for improving those problems mentioned-above. We use TSUPREM-4 to simulate the TFT structures and operate MEDICI to simulate the electrical characteristics of devices. In this thesis, three types TFTs with different structure were studied. They are the conventional single source/drain TFTs, the TFTs with Vth-adjustment method and the buried-channel (BC) TFTs. Some fabrication parameters such as various gate oxide thicknesses and different gate length (or channel length) would also included in discussion with the three structures. After adding the LDD structure, the samples of the three structures would be also discussed. Finally, the electrical characteristics of the conventional single source/drain TFTs, the TFTs with Vth-adjustment method, the BC TFTs, and the BC TFTs with LDD structure were compared. They were the conventional single source/drain TFTs, boron implantation dose at 1E12 cm-2 doses with 20keV energy for the TFT with Vth-adjustment method, the BC TFT with phosphorus implantation dose at 2E11 cm-2 doses with 30keV energy and boron implantation dose at 1E12 cm-2 doses with 20keV energy, and the LDD structure is formed with phosphorus implantation dose at 2E11 cm-2 doses at 100 keV energy for the BC TFT. It could be found that the BC TFTs with LDD structure achieve much smaller leakage and less kink effect than the other three structures, attributable to the more effective suppression of carrier emission via trap states. Moreover, the lower lateral electric field intensity near the drain also showed in BC TFTs with LDD structure. As the result, the simple and self-aligned method for the BC with LDD structure is an effective way on panel fabrications to improve some bias-caused problems.
Raghuraman, Mathangi. "Threshold Voltage Shift Compensating Circuits in Non-Crystalline Semiconductors for Large Area Sensor Actuator Interface." Thesis, 2014. http://etd.iisc.ac.in/handle/2005/3176.
Повний текст джерела"Thin Film Transistor Control Circuitry for MEMS Acoustic Transducers." Master's thesis, 2012. http://hdl.handle.net/2286/R.I.15984.
Повний текст джерелаDissertation/Thesis
M.S. Electrical Engineering 2012
Chiou, Chi-Ming, and 邱啟明. "The method for checking alignment accuracy of a thin film transistor (TFT) by TEG test." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/44027398025017740963.
Повний текст джерела中原大學
電子工程研究所
100
Today’s TFT LCD Panel Makers use optical measurement to measure the distance of patterns exposed by two different masks to present the alignment accuracy of two mask . But it is hard to do a lot of alignment accuracy check,because the optical measurement’s tact time is very long for each inspection . This article mainly introduced the method for checking alignment accuracy of a thin film transistor (TFT),the switch is using the Mask Overlap relations to form a open or non-open circuit and combine the Array TEG(Test Element Group) for checking alignment accuracy. It was found the design of space GE/PE should be 3.5um,because after wet etching process it will become to 2um,it means that the overlap of GE/PE is almost about 1um,will match the control spec of Overlap for LCD Maker.
Lai, Erh-Kun, and 賴二琨. "Process Integration of 3D Thin Film Transistor (TFT) NAND Flash and Resistive Random Access Memory." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/6jcdv2.
Повний текст джерелаPeng, Yu-Shen, та 彭昱燊. "Process and Structure Design of Microcrystalline Silicon Thin-Film-Transistors (μC-Si TFTs)". Thesis, 2010. http://ndltd.ncl.edu.tw/handle/57982851018671873312.
Повний текст джерела國立臺灣科技大學
電子工程系
98
Microcrystalline silicon thin-film-transistors (μC-Si TFTs) have been widely studied. Due to better device characteristic, and large area growth using a lower temperature process, compared to amorphous silicon thin-film-transistors, it has larger electron field mobility and lower energy band gap. Recently, it has been believed can substitute for the a-Si:H TFTs on large substrate area liquid crystal displays application status. However, μC-Si TFTs has some unavoidable problems, such as, large leakage current, non-uniform on fabrication, and worse device characteristic than polycrystalline silicon TFTs. For the improvement of device characteristic and the process simplification for μC-Si TFTs, in this thesis, μC-Si TFTs formed by using self-aligned silicided scheme and top gate staggered-type μC-Si TFTs structure have been studied, respectively. In this thesis, μC-Si TFTs were examined by device simulation. First, the self aligned silicided scheme μC-Si TFTs are discussed. As compared to the previous top-gate staggered structure, the self-aligned silicided scheme leads to larger bending of energy band near the source region, which facilitates causing more carriers tunneling. In addition, for the top-gate staggered structure, since the source/drain electrode is spaced from the surface channel layer, the parasitic series resistance between the electrode and surface channel layer is considerably caused. As a result, the self-aligned silicided scheme can cause a larger conduction current than the top-gate staggered structure. Following, the silicide thickness of self aligned silicided scheme is changed, to study its influence to device characteristic. Second, top gate staggered type μC-Si TFTs with difference channel layer thicknesses are discussed. It is found that, for a given electrode thickness, a proper channel layer thickness should be chosen to achieve better device characteristic. Finally, as compared with single electrode metal, the stacked electrode can achieve a better trade-off between nmos and pmos driving current.
Chuang, Shu-Ya, and 莊淑雅. "A Study of Device Characteristics and Applications of Polysilicon Thin Film Transistors(TFTs)." Thesis, 1994. http://ndltd.ncl.edu.tw/handle/90113193098412417917.
Повний текст джерела國立交通大學
電子研究所
82
In this thesis, the poly-Si TFTs devices are fabricated by conventional standard CMOS and BiCMOS processes. The char- acteristics and electrical parameters of the devices have been obsreved and studied, including small dimension effect and off- current behavior. And the gate-controlled mobility is also characterized and explained. These CMOS/BiCMOS com- patible poly-Si TFTs can be used in the situation where chip area reduction of circuits is a very important concern, be- cause of its ability of three-dimensional integration. The basic application idea is that if the TFTs can be realized by any process, it will become more applicable in more situ- ation. It has also been shown that the photosensitivity of the poly- TFTs is significant. The dependences of the photocurrent on gate voltage, drain voltage and channel doping are studied, and the physical mechanisms are given.The excellent photosen- sitivity may be applied to the design of light sensor or light trigger elements and integrated on CMOS/BiCMOS chip.
Chen, Lei-Guang, and 陳雷光. "A LTPS (Low temperature polysilicon) TFT (Thin-film transistor) Chip for Dielectrophoretic Manipulation and Bio-detection." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/12593496600019510167.
Повний текст джерела國立清華大學
電子工程研究所
98
This study has successfully used LTPS TFT process technology to design a bio chip that can perform dielectrophoretic (DEP) manipulation and optical detection. The LTPS process has the benefit of less post-processing steps required than the CMOS (complementary metal oxide semiconductor) process to realize the chip. In addition, the process can provide a large chip area at low cost. Reliability, however, is the main issue that the LTPS process has to improve. The basic principle of DEP force and its mathematical model will be presented. CFD-RC software is utilized for simulation to ensure microbeads can be successfully moved to the target electrodes based on our design. Bio-detection is achieved by using image sensors. H-spice simulation is used to verify the feasibility of the circuit design. In the experiments, a thin layer of silicon dioxide is deposited on chip surface for surface functionalization and biomolecule immobilization. Immobilized microbeads can be moved to the target microelectrodes by DEP and produce specific bindings with the immobilized biomolecules on sensor surface. Those beads are successfully detected by the optical sensors underneath microelectrodes to validate the bio-recognition event.
Raghuraman, Mathangi. "Threshold Voltage Shift Compensating Circuits in Non-Crystalline Semiconductors for Large Area Sensor Actuator Interface." Thesis, 2014. http://hdl.handle.net/2005/3176.
Повний текст джерелаRajachidambaram, Jaana Saranya. "Evaluation of amorphous oxide semiconductors for thin film transistors (TFTs) and resistive random access memory (RRAM) applications." Thesis, 2011. http://hdl.handle.net/1957/26517.
Повний текст джерелаGraduation date: 2012
Access restricted to the OSU Community at author's request from Jan. 6, 2012 - Jan. 6, 2013
Chung, Lung-Sheng, and 鍾隆陞. "The Ten Thin Film Transistor-Liquid Crystal Display(TFT-LCD) Manufacturers of Operating Analysis and Performance Assessment." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/99099373048102261857.
Повний текст джерела開南大學
專案管理研究所
98
With the trend of rapid development in the digital information of the world,the product demand of information industry on light、thin and less-electricity leads the accelerated development of global thin film transistor-Liquid Crystal Display(TFT-LCD) manufacturers. Moreover, the main production line concentrates in South Korea and Taiwan and the sales volume of the global total output value is 83% approximately in the existing big factory of the thin film transistor-Liquid Crystal Display (TFT-LCD). TFT-LCD display has already been a main product of the information industry at present, in view of growing rapidly of demand in the world, the competition of TFT-LCD manufacturers have been a fierce phenomenon. The most important subject for administrator of every TFT-LCD manufacturer is how to make the best disposition of resources and create more and more profits. Korea and Japan TFT-LCD manufacturers are regarded as the research object in this research, via the relevant TFT-LCD manufacturer environmental trend analysis in the IEK and the public observation station and the public statement, and the annual financial statement in the 10 TFT-LCD manufacturers in the world; through the improvement of Data Envelopment Analysis (DEA) in order to measure the dynamic operation performance in Taiwan, Korea and Japan TFT-LCD manufacturers in 2002 to 2007. The survey results showed that the Innolux has the highest management accomplishment while the Toshiba comes up the last.