Статті в журналах: "Thin film interconnects"

1

Smy, T., S. K. Dew, and M. J. Brett. "Simulation of Microstructure and Surface Profiles of Thin Films for VLSI Metallization." MRS Bulletin 20, no. 11 (November 1995): 65–69. http://dx.doi.org/10.1557/s0883769400045619.

Повний текст джерела

Анотація:

A crucial step in the manufacture of very large-scale integration (VLSI) integrated circuits is the fabrication of reliable, low-resistance metal interconnects between semiconductor devices. The fabrication of these interconnects is generally performed by depositing a blanket metal film and then patterning it by lithographic and etching techniques. The primary means of depositing thin metal films for VLSI interconnects are sputtering and chemical vapor deposition (CVD).The creation of reliable interconnects is, however, complicated by a number of issues. In order to obtain low contact resistance, to inhibit reactions with the silicon, and to provide good adhesion to both Si and SiO2, contact, barrier, and adhesion layers are generally deposited prior to the deposition of the low-resistance metal film that forms the bulk of the interconnect. If these layers are to provide an effective barrier to diffusion of the interconnection metal to the silicon, they must be deposited in a uniform, homogeneous form. It is also necessary that the primary interconnect material have as high step coverage as is possible in order to reduce current crowding, local heating effects, and electromigration. Unfortunately, as VLSI circuit densities have increased, the fabrication of interconnects requires high aspect-ratio contact cuts, and relatively severe local topographies can result. These factors make it difficult to deposit films with good step and bottom coverage.In addition to these concerns with the film surface profile, another factor is becoming increasingly significant. Both sputtering and CVD produce thin films with characteristic microstructures. This microstructure consists of columns or grains separated by grain boundaries and voids.

Стилі APA, Harvard, Vancouver, ISO та ін.

2

Lacour, Stéphanie P., Joyelle Jones, Sigurd Wagner, Teng Li, and Z. Suo. "ELASTOMERIC INTERCONNECTS." International Journal of High Speed Electronics and Systems 16, no. 01 (March 2006): 397–407. http://dx.doi.org/10.1142/s0129156406003722.

Повний текст джерела

Анотація:

Elastomeric interconnects made of patterned thin gold films on silicone membranes, can be reversibly bent, uniaxially or radially stretched while remaining electrically conducting. Such interconnects can be stretched to double their length, cycled 1,000 times without electrical failure. While the electrical resistance may increase threefold upon stretching, the resistance values still remain ~1,000 times below the typical input impedance of amorphous silicon thin film transistors. Therefore the stretchable gold films can function as interconnects for power and signal to a fully elastic thin film transistor inverter.

Стилі APA, Harvard, Vancouver, ISO та ін.

3

Cherenack, Kunigunde H., Thomas Kinkeldei, Christoph Zysset, and Gerhard Tröster. "Woven Thin-Film Metal Interconnects." IEEE Electron Device Letters 31, no. 7 (July 2010): 740–42. http://dx.doi.org/10.1109/led.2010.2048993.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

4

Hwang, Byungil, Yurim Han, and Paolo Matteini. "BENDING FATIGUE BEHAVIOR OF AG NANOWIRE/CU THIN-FILM HYBRID INTERCONNECTS FOR WEARABLE ELECTRONICS." Facta Universitatis, Series: Mechanical Engineering 20, no. 3 (November 30, 2022): 553. http://dx.doi.org/10.22190/fume220730040h.

Повний текст джерела

Анотація:

Enhancing the mechanical reliability of metal interconnects is important for achieving highly reliable flexible/wearable electronic devices. In this study, Ag nanowire and Cu thin-film hybrid interconnects were explored as a novel concept to enhance mechanical reliability under bending fatigue. Bending fatigue tests were conducted on the Cu thin films and Cu/Ag nanowire/polyimide (CAP) interconnects. The increase in resistance was larger for the Cu thin films than for the CAP. The single-component Cu electrodes showed multiple crack initiation and propagation due to bending strain, which degraded the electrical conductivity. In CAP, however, no long-range cracks were observed, even after 300,000 cycles of bending, although a wavy structure was observed, probably due to the delamination of the Ag nanowires under repeated bending. Our study confirms that flexible Ag nanowire and metal thin-film hybrids can enhance the mechanical reliability of metal thin-film interconnects under bending fatigue.

Стилі APA, Harvard, Vancouver, ISO та ін.

5

Beers, Kimberly, Andrew E. Hollowell, and G. Bahar Basim. "Thin Film Characterization on Cu/SnAg Solder Interface for 3D Packaging Technologies." MRS Advances 5, no. 37-38 (2020): 1929–35. http://dx.doi.org/10.1557/adv.2020.309.

Повний текст джерела

Анотація:

AbstractCopper is a commonly used interconnect metal in microelectronic interconnects due to its exceptional electrical and thermal properties. Particularly in applications of the 2.5 and 3D integration, Cu is utilized in through-silicon-vias (TSVs) and flip chip interconnects between microelectronic chips for providing miniaturization, lower power and higher performance than current 2D packaging approaches. SnAg capped Cu pillars are a common high-density interconnect technology for flip chip bonding. For these interconnects, specific properties of the Cu surface, such as roughness and cleanliness, are an important factor in the process to ensure quality solder bumps. During electroplating, tight processing parameters must be met so that defects are avoided, and high bump uniformity is achieved. An understanding of the interactions at the solder and Cu pillar interface is needed, based on the electroplating parameters, to determine the best method for populating solder on the wafer surface. In this study, surface treatment techniques such as oxygen plasma cleaning were performed on the Cu surfaces and the SnAg plating chemistry for depositing the solder were evaluated through hull cell testing to qualitatively determine the range of current densities to investigate. It was observed that current density while plating played a large role in solder bump deposition morphology. At the higher current densities greater than 60 mA/cm2, bump height non-uniformity and dendritic growth are observed and at lower current densities, less than or equal to 60 mA/cm2, uniform, continuous bump height occurred.

Стилі APA, Harvard, Vancouver, ISO та ін.

6

Thompson, Carl V., and James R. Lloyd. "Electromigration and IC Interconnects." MRS Bulletin 18, no. 12 (December 1993): 19–25. http://dx.doi.org/10.1557/s088376940003904x.

Повний текст джерела

Анотація:

A modern integrated circuit (IC) is composed of 106 or more electronic devices. They are connected to form a circuit through the use of metallic films patterned into strips which function as wires to interconnect devices. These wires are usually simply referred to as interconnects. In an IC occupying the surface of a 1 cm2 Si chip, there can be 10 m of total interconnect length. This length is in the form of more than 106 line segments contacting pairs of devices and different segments of the circuit. This enormous number of wires is made possible by their small widths. Interconnect widths as small as 0.55 μm are currently used in commercial circuits, and circuits and processes leading to smaller and smaller widths are continuously in development.During operation of an IC, interconnects carry current densities as high as 4 × 105 A/cm2. This should be compared with a current density of 102 A/cm2, the maximum allowed for house wiring. Thin-film conductors can carry these high current densities only because of the relatively good heat sinking provided by the Si substrate.

Стилі APA, Harvard, Vancouver, ISO та ін.

7

Vidal, Melissa Mederos, Alexander Flacker, and Ricardo Cotrin Teixeira. "Metallization of High Purity Al2O3 Substrate with Autocatalytic NiP Thin Films for Au Interconnections in MCM packaging technology." Journal of Integrated Circuits and Systems 15, no. 2 (July 31, 2020): 1–4. http://dx.doi.org/10.29292/jics.v15i2.145.

Повний текст джерела

Анотація:

A Multichip Module (MCM) is a structure consisting of several ICs (typically bare chips) interconnected on a common supporting substrate and packaged as a single device. In this packaging technology, gold (Au) thin films are used as interconnection tracks terminated by wire bonding process to the chips. Thus, the good quality of theses Au films (for interconnects purpose) is essential. The present work proposes a metallization sequence of high purity (99.9%) and polished Al2O3 substrates, with an autocatalytic (electroless) NiP thin film follow by an electrolytic Au film in order to improve the MCM interconnections quality. The results show NiP and Au films with good adhesion, low roughness, good thickness distribution and optimal electrical properties, which allows us to establish a methodology that guarantees the reproducibility and quality of the Au interconnections in MCM devices.

Стилі APA, Harvard, Vancouver, ISO та ін.

8

Kononenko, O. V., V. N. Matveev, and D. P. Field. "Electromigration properties of multigrain aluminum thin film conductors as influenced by grain boundary structure." Journal of Materials Research 16, no. 7 (July 2001): 2124–29. http://dx.doi.org/10.1557/jmr.2001.0289.

Повний текст джерела

Анотація:

Electromigration rates in polycrystalline interconnect lines are controlled by grain-boundary diffusion. As such, reliability of such interconnects is a direct function of the grain-boundary character distribution in the lines. In the present work, drift velocity experiments were performed on multicrystalline lines of pure Al to determine the electromigration activation energy of the lines. Lines cut from films processed by partially ionized beam deposition techniques were analyzed. One set of lines was analyzed in the as-deposited condition while the other film was annealed before testing. The measured drift velocities varied dramatically between these two types of films, as did the grain-boundary character distributions measured by orientation imaging. The data were analyzed based on Borisov's equation to obtain mean grain-boundary energies. Grain-boundary energy of the film with poor electromigration performance was calculated to be that reported for random boundaries, while that for the more reliable film was calculated to be that reported for twin boundaries in Al. Percolation theory was used to aid explanation of the results based upon the fraction and connectedness of special boundaries in the films.

Стилі APA, Harvard, Vancouver, ISO та ін.

9

Reddy, Mareddy Jayanth, Isak Almyren, Jan-Erik Svensson, and Jan Froitzheim. "Strategies to Improve the Effectiveness of the Thin Film Coated Interconnects." ECS Transactions 111, no. 6 (May 19, 2023): 2243–51. http://dx.doi.org/10.1149/11106.2243ecst.

Повний текст джерела

Анотація:

Ferritic stainless steels are used as interconnect materials in solid oxide cells (SOFC/SOEC). To enhance their performance and extend the lifespan of SOC’s, FSS interconnects are typically coated with protective coatings. MCO coatings deposited through physical vapor deposition have been extensively studied for this purpose. However, most studies have been conducted on in isothermal conditions which do not reflect the conditions experienced in stacks. Stacks are typically conditioned at high temperatures, usually 100-250°C above the operating temperatures, to ensure gas tightness. Thus, it is important to understand the influence of pre-oxidation on behaviour of the interconnect. The influence of pre-oxidation on Ce/Co-coated Crofer 22 APU and AISI 441 is studied at 850°C in air. The samples are characterised using scanning electron microscopy. The oxidation behaviour of Ce/Co-coated Crofer 22 APU improved significantly upon pre-oxidation whereas only minimal effect was observed for Ce/Co-coated AISI 441.

Стилі APA, Harvard, Vancouver, ISO та ін.

10

Santos, Rúben F., Bruno M. C. Oliveira, Liliane C. G. Savaris, Paulo J. Ferreira, and Manuel F. Vieira. "Seedless Cu Electroplating on Ru-W Thin Films for Metallisation of Advanced Interconnects." International Journal of Molecular Sciences 23, no. 3 (February 8, 2022): 1891. http://dx.doi.org/10.3390/ijms23031891.

Повний текст джерела

Анотація:

For decades, Ta/TaN has been the industry standard for a diffusion barrier against Cu in interconnect metallisation. The continuous miniaturisation of transistors and interconnects into the nanoscale are pushing conventional materials to their physical limits and creating the need to replace them. Binary metallic systems, such as Ru-W, have attracted considerable attention as possible replacements due to a combination of electrical and diffusion barrier properties and the capability of direct Cu electroplating. The process of Cu electrodeposition on Ru-W is of fundamental importance in order to create thin, continuous, and adherent films for advanced interconnect metallisation. This work investigates the effects of the current density and application method on the electro-crystallisation behaviour of Cu. The film structure, morphology, and chemical composition were assessed by digital microscopy, atomic force microscopy, scanning and transmission electron microscopies, energy-dispersive X-ray spectroscopy, and X-ray diffraction. The results show that it was possible to form a thin Cu film on Ru-W with interfacial continuity for current densities higher than 5 mA·cm−2; however, the substrate regions around large Cu particles remained uncovered. Pulse-reverse current application appears to be more beneficial than direct current as it decreased the average Cu particle size.

Стилі APA, Harvard, Vancouver, ISO та ін.

11

Pennetta, C., L. Reggiani, Gy Trefán, R. Cataldo, and G. De Nunzio. "A Percolative Approach to Reliability of Thin Film Interconnects and Ultra-thin Dielectrics." VLSI Design 13, no. 1-4 (January 1, 2001): 363–67. http://dx.doi.org/10.1155/2001/38657.

Повний текст джерела

Анотація:

Degradation of thin film interconnects and ultra-thin dielectrics is studied within a stochastic approach based on a percolation technique. The thin film is modelled as a two-dimensional random resistor network at a given temperature and its degradation is characterized by a breaking probability of the single resistor. A recovery of the damage is also allowed so that a steady-state condition can be achieved. The main features of experiments are reproduced. This approach provides a unified description of degradation and failure processes in terms of physical parameters.

Стилі APA, Harvard, Vancouver, ISO та ін.

12

Ertekin, Elif, and Akilesh Lakhtakia. "Optical interconnects realizable with thin–film helicoidal bianisotropic mediums." Proceedings of the Royal Society of London. Series A: Mathematical, Physical and Engineering Sciences 457, no. 2008 (April 8, 2001): 817–36. http://dx.doi.org/10.1098/rspa.2000.0694.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

13

Frankovic, R., and G. H. Bernstein. "Electromigration drift and threshold in Cu thin-film interconnects." IEEE Transactions on Electron Devices 43, no. 12 (1996): 2233–39. http://dx.doi.org/10.1109/16.544396.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

14

Lane, T., F. Belcourt, and R. Jensen. "Electrical Characteristics of Copper/Polyimide Thin-Film Multilayer Interconnects." IEEE Transactions on Components, Hybrids, and Manufacturing Technology 10, no. 4 (December 1987): 577–85. http://dx.doi.org/10.1109/tchmt.1987.1134780.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

15

Hu, Lili, Junlan Wang, Zijian Li, Shuang Li, and Yushan Yan. "Interfacial adhesion of nanoporous zeolite thin films." Journal of Materials Research 21, no. 2 (February 1, 2006): 505–11. http://dx.doi.org/10.1557/jmr.2006.0060.

Повний текст джерела

Анотація:

Nanoporous silica zeolite thin films are promising candidates for future generation low-dielectric constant (low-k) materials. During the integration with metal interconnects, residual stresses resulting from the packaging processes may cause the low-k thin films to fracture or delaminate from the substrates. To achieve high-quality low-k zeolite thin films, it is important to carefully evaluate their adhesion performance. In this paper, a previously reported laser spallation technique is modified to investigate the interfacial adhesion of zeolite thin film-Si substrate interfaces fabricated using three different methods: spin-on, seeded growth, and in situ growth. The experimental results reported here show that seeded growth generates films with the highest measured adhesion strength (801 ± 68 MPa), followed by the in situ growth (324 ± 17 MPa), then by the spin-on (111 ± 29 MPa). The influence of the deposition method on film–substrate adhesion is discussed. This is the first time that the interfacial strength of zeolite thin films-Si substrates has been quantitatively evaluated. This paper is of great significance for the future applications of low-k zeolite thin film materials.

Стилі APA, Harvard, Vancouver, ISO та ін.

16

Seo, Min, Min Kyung Cho, Un Hyeon Kang, Sin Young Jeon, Sang-Ho Lim, and Seung Hee Han. "Low-Resistivity Cobalt and Ruthenium Ultra-Thin Film Deposition Using Bipolar HiPIMS Technique." ECS Journal of Solid State Science and Technology 11, no. 3 (March 1, 2022): 033006. http://dx.doi.org/10.1149/2162-8777/ac5805.

Повний текст джерела

Анотація:

Owing to the rapid growth of very large-scale integration technology at nanometer scales, cobalt and ruthenium interconnects are being used to solve the high-resistivity copper problem. However, with such interconnects, carbon contamination can occur during chemical vapor deposition and atomic layer deposition. Bipolar (BP) high-power impulse magnetron sputtering (HiPIMS) with a high ionization rate is an excellent vacuum process for depositing low-resistivity thin films. In this study, low-resistivity cobalt, ruthenium, and copper thin films were deposited using BP-HiPIMS, HiPIMS, and direct-current magnetron sputtering (DCMS). The resistivities of the cobalt, ruthenium, and copper thin films (<10 nm) deposited via BP-HiPIMS were 91.5, 75, and 35%, respectively, lower than the resistivities of the same film materials deposited using direct-current MS. To solve the low pass-through flux of cobalt, the target temperature was raised to the Curie temperature (approximately 1100 °C) using a thermal insulation backplate (Ti-6Al-4V), resulting in a resistivity reduction of about 73%. The study provides a novel method for the vacuum deposition of cobalt and ruthenium thin films.

Стилі APA, Harvard, Vancouver, ISO та ін.

17

Misawa, N., T. Ohba, and H. Yagi. "Planarized Copper Multilevel Interconnections for ULSI Applications." MRS Bulletin 19, no. 8 (August 1994): 63–67. http://dx.doi.org/10.1557/s088376940004776x.

Повний текст джерела

Анотація:

As the degree of large-scale integration (LSI) increases, the area of a single transistor will diminish and the density of transistors will increase. Accordingly, technology for high-density wiring to interconnect the huge number of transistors is needed because transistors cannot perform any useful functions without interconnects and electrodes. For advanced microprocessor chips with a sub-half-micron design rule and at least four interconnect layers, the minimum width of the interconnects becomes less than 0.35 μm.Aluminum or an aluminum alloy is now generally used as the interconnect material in LSI circuits because the physical and chemical properties of aluminum are compatible with current LSI processing: Aluminum forms a thin protective oxide film that withstands various thermal processes; it has relatively low electrical resistivity and halide compounds with a relatively high vapor pressure which are suitable for reactive ion etching (RIE), and it is an inexpensive material. The reliability of aluminum interconnects, however, is a major concern for maintaining the total reliability of advanced LSI. Because of its relatively low melting point, aluminum as an interconnect material is susceptible to stress- and electromigration, which leads to open failure of the interconnect. It is well-known that these failure modes are accelerated by decreasing the width and thickness of the interconnects. Hence, use of aluminum interconnects may be limited for future sub-half-micron LSIs.

Стилі APA, Harvard, Vancouver, ISO та ін.

18

Hu, K. X., C. P. Yeh, X. S. Wu, and K. Wyatt. "An Interfacial Delamination Analysis for Multichip Module Thin Film Interconnects." Journal of Electronic Packaging 118, no. 4 (December 1, 1996): 206–13. http://dx.doi.org/10.1115/1.2792154.

Повний текст джерела

Анотація:

Analysis of interfacial delamination for multichip module thin-film interconnects (MCM/TFI) is the primary objective of this paper. An interface crack model is integrated with finite-element analysis to allow for accurate numerical evaluation of the magnitude and phase angle of the complex stress intensity factor. Under the assumption of quasi-static delamination growth, the fate of an interfacial delamination after inception of propagation is determined. It is established that whether an interfacial delamination will continue to grow or become arrested depends on the functional behavior of the energy release rate and loading phase angle over the history of delamination growth. This functional behavior is numerically obtained for a typical MCM/TFI structure with delamination along die and via base, subjected to thermal loading condition. The effect of delamination interactions on the structural reliability is also investigated. It is observed that the delamination along via wall and polymer thin film can provide a benevolent mechanism to relieve thermal constraints, leading to via stress relaxation.

Стилі APA, Harvard, Vancouver, ISO та ін.

19

Hsu, Yung-Yu, Kylie Lucas, Dan Davis, Brian Elolampi, Roozbeh Ghaffari, Conor Rafferty, and Kevin Dowling. "Novel Strain Relief Design for Multilayer Thin Film Stretchable Interconnects." IEEE Transactions on Electron Devices 60, no. 7 (July 2013): 2338–45. http://dx.doi.org/10.1109/ted.2013.2264217.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

20

Shen, Y. L. "On the formation of voids in thin-film metal interconnects." Scripta Materialia 37, no. 11 (December 1997): 1805–10. http://dx.doi.org/10.1016/s1359-6462(97)00342-4.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

21

Savastiouk, Sergey, Phil Marcoux, and Jim Hewlett. "Silicon Interposers Enable High Performance Capacitors." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2011, DPC (January 1, 2011): 001996–2010. http://dx.doi.org/10.4071/2011dpc-wp45.

Повний текст джерела

Анотація:

Thin film capacitors without TSVs have been used previously. However, with the interconnect inductance being high, benefits of thin film capacitors have not been fully realized. TSV interposers with embedded capacitors provide the shortest electrical path between devices and power supply decoupling capacitors. TSVs with their very low inductance interconnects thus will enable very high electrical performance when integrated with embedded thin film capacitors. ALLVIA, on behalf of it's foundry customers, has been conducting studies of various capacitors on silicon interposers. The data presented in this paper shows after several thermal cycles that planar capacitors on silicon results in stable, reliable capacitors operating at very high frequencies. Unlike an issue of parallel resonance seen with chip capacitors, planar capacitors in interposers don't exhibit this property.

Стилі APA, Harvard, Vancouver, ISO та ін.

22

Kundu, Satwik, Rupshali Roy, M. Saifur Rahman, Suryansh Upadhyay, Rasit Onur Topaloglu, Suzanne E. Mohney, Shengxi Huang, and Swaroop Ghosh. "Exploring Topological Semi-Metals for Interconnects." Journal of Low Power Electronics and Applications 13, no. 1 (February 9, 2023): 16. http://dx.doi.org/10.3390/jlpea13010016.

Повний текст джерела

Анотація:

The size of transistors has drastically reduced over the years. Interconnects have likewise also been scaled down. Today, conventional copper (Cu)-based interconnects face a significant impediment to further scaling since their electrical conductivity decreases at smaller dimensions, which also worsens the signal delay and energy consumption. As a result, alternative scalable materials such as semi-metals and 2D materials were being investigated as potential Cu replacements. In this paper, we experimentally showed that CoPt can provide better resistivity than Cu at thin dimensions and proposed hybrid poly-Si with a CoPt coating for local routing in standard cells for compactness. We evaluated the performance gain for DRAM/eDRAM, and area vs. performance trade-off for D-Flip-Flop (DFF) using hybrid poly-Si with a thin film of CoPt. We gained up to a 3-fold reduction in delay and a 15.6% reduction in cell area with the proposed hybrid interconnect. We also studied the system-level interconnect design using NbAs, a topological semi-metal with high electron mobility at the nanoscale, and demonstrated its advantages over Cu in terms of resistivity, propagation delay, and slew rate. Our simulations revealed that NbAs could reduce the propagation delay by up to 35.88%. We further evaluated the potential system-level performance gain for NbAs-based interconnects in cache memories and observed an instructions per cycle (IPC) improvement of up to 23.8%.

Стилі APA, Harvard, Vancouver, ISO та ін.

23

Katkar, Rajesh, та Laura Mirkarimi. "Electromigration Performance of Pb-Free μPILR™ Flip-Chip Packages". International Symposium on Microelectronics 2010, № 1 (1 січня 2010): 000234–41. http://dx.doi.org/10.4071/isom-2010-tp2-paper6.

Повний текст джерела

Анотація:

The μPILR interconnect is a copper pillar manufactured as a part of a substrate pad. In this paper, we discuss the electromigration (EM) performance of Pb-free μPILR interconnects in a multi-pair daisy chain within 150μm pitch flip-chip packages. Electromigration performance of μPILR interconnects has shown a significant improvement and noticeably delayed electromigration induced failures. Voids initially begin to appear at Cu6Sn5 and solder interface on the die side, with eventual open failure due to excessive void formation along with a severe depletion of Cu Under Bump Metallization (UBM). No failure was observed on the substrate side of the interconnect regardless of the current direction. The enhanced performance of the μPILR interconnect along with other reliability benefits makes it an excellent alternative to conventional solder joints including thin film stack UBMs, thicker copper UBM as well as copper pillar on die.

Стилі APA, Harvard, Vancouver, ISO та ін.

24

Povirk, G. L., R. Mohan, and S. B. Brown. "Crystal plasticity simulations of thermal stresses in thin‐film aluminum interconnects." Journal of Applied Physics 77, no. 2 (January 15, 1995): 598–606. http://dx.doi.org/10.1063/1.359044.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

25

Wongpiya, Ranida, Jiaomin Ouyang, Taeho Roy Kim, Michael Deal, Robert Sinclair, Yoshio Nishi, and Bruce Clemens. "Amorphous thin film TaWSiC as a diffusion barrier for copper interconnects." Applied Physics Letters 103, no. 2 (July 8, 2013): 022104. http://dx.doi.org/10.1063/1.4813396.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

26

Foster, B. C., F. J. Bachner, E. S. Tormey, M. A. Occhionero, and P. A. White. "Advanced ceramic substrates for multichip modules with multilevel thin film interconnects." IEEE Transactions on Components, Hybrids, and Manufacturing Technology 14, no. 4 (1991): 784–89. http://dx.doi.org/10.1109/33.105134.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

27

Shih, W. C., and A. L. Greer. "A new precipitate phase in Al-4wt. % Cu thin-film interconnects." Journal of Electronic Materials 23, no. 12 (December 1994): 1315–23. http://dx.doi.org/10.1007/bf02649897.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

28

Laibowitz, Robert B. "High Tc Superconducting Thin Films." MRS Bulletin 14, no. 1 (January 1989): 58–62. http://dx.doi.org/10.1557/s0883769400053926.

Повний текст джерела

Анотація:

While high Tc superconductivity was first discovered in bulk material, it was apparent that thin films of these materials, particularly the compound YBa2Cu3O7-δ, would be of great interest to both science and technology. In this sense the development of these materials parallels a similar history in the low Tc materials. Initially, most of the low Tc materials of interest were single element metals such as Nb, Pb and Al in bulk form. Later work, mostly in magnets, led to the development of compounds or alloys of such metals as Nb-Sn, Nb-Ti, and many others. However, many physical and technological investigations required thin films with thicknesses in the range of 0.1-10μm. Microwave, infrared, and critical current studies are examples of some of the scientific uses of thin films. A few examples of the applications would include josephson junction-based digital computer circuits, SQUID (Superconducting Quantum Interference Devices), transmission lines, and interconnects and rf mixers. These studies are also of great interest in the high Tc materials. It is readily apparent that scientific and technological developments in superconductivity are closely interwoven.The high level of interest in thin films can be appreciated by observing that it was barely a few months after the announcement of superconductivity above 77 K that the first films of these complex, multi-element materials, superconducting at about 86 K were announced. These early efforts at thin film fabrication were generally accomplished using multi-element deposition techniques but subsequent development has seen many varieties of film fabrication techniques used quite successfully to fabricate high-quality films.

Стилі APA, Harvard, Vancouver, ISO та ін.

29

Shacham-Diamand, Yosi. "The Reliability of Aluminum/Tungsten Technology for VLSI Applications." MRS Bulletin 20, no. 11 (November 1995): 78–82. http://dx.doi.org/10.1557/s0883769400045644.

Повний текст джерела

Анотація:

Interconnects technology and back-end processing moved to the center stage of very large-scale integration (VLSI) technology in the mid-1980s. At that time, the critical dimensions dropped below 1 μm while the chip size and complexity increased to a level where interconnects were recognized to be a limiting factor. As dimensions decreased, the step coverage of sputtered aluminum inside contacts and via-contact holes decreased and alternative technologies were studied. The increasing cost of ownership (COO) of single-wafer Al sputtering processes also supported the search for alternative technologies, such as tungsten chemical vapor deposition (CVD) for via contacts and plugs (Figure 1). Only recently have all the W CVD process steps been optimized to lower cost without loss of reliability and/or performance. The development of cluster tool technology and multiwafer process modules also allowed reliable and cost-effective utilization of the W/Al technology.Tungsten technology for VLSI circuits became complementary to that of aluminum. Tungsten thin-film resistivity ρw = 7–8 μΩ cm is much higher than that of aluminum ρAl = 3–4 μΩ cm, introducing large W interconnect resistance-capacitance (RC) delays compared to Al. Therefore, tungsten is not favorable for high-speed global-interconnect schemes. However, tungsten is suitable for local interconnects where the impedance of the driving transistors is dominant and the RC interconnect delay is less significant. Tungsten is also suitable for contact filling, in which the via resistance is negligible. For these applications, tungsten became a dominant technology and was integrated with the aluminumalloy-based technology used for global interconnects.

Стилі APA, Harvard, Vancouver, ISO та ін.

30

Glickman, Evgeny E., and M. Nathan. "Electromigration Kinetics in Thin Film Interconnects: Electro-Transport Coupled to Diffusional Creep." Defect and Diffusion Forum 194-199 (April 2001): 1417–30. http://dx.doi.org/10.4028/www.scientific.net/ddf.194-199.1417.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

31

Schwarz, J. A. "Distributions of activation energies for electromigration damage in thin‐film aluminum interconnects." Journal of Applied Physics 61, no. 2 (January 15, 1987): 798–800. http://dx.doi.org/10.1063/1.338185.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

32

Kim, Choong-Un, J. W. Morris, and Hyuck-Mo Lee. "Kinetics of electromigration-induced edge drift in Al–Cu thin-film interconnects." Journal of Applied Physics 82, no. 4 (August 15, 1997): 1592–98. http://dx.doi.org/10.1063/1.365948.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

33

Han, J. H., M. C. Shin, S. H. Kang, and J. W. Morris. "Effects of precipitate distribution on electromigration in Al–Cu thin-film interconnects." Applied Physics Letters 73, no. 6 (August 10, 1998): 762–64. http://dx.doi.org/10.1063/1.121993.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

34

Yang, Chin-Hao, Wen-Luh Yang, and Wei Chang. "Copper Interconnects Grown by Electrochemical Displacing the Prepatterned SiC Barrier Thin Film." Electrochemical and Solid-State Letters 8, no. 9 (2005): C121. http://dx.doi.org/10.1149/1.1990030.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

35

Gupta, Vaibhav, John A. Sellers, Charles D. Ellis, Bhargav Yelamanchili, Simin Zou, Yang Cao, David B. Tuckerman, and Michael C. Hamilton. "Minimizing Film Stress and Degradation in Thin-Film Niobium Superconducting Cables." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2017, DPC (January 1, 2017): 1–25. http://dx.doi.org/10.4071/2017dpc-tha3_presentation4.

Повний текст джерела

Анотація:

The future of superconducting and cryogenic electronic systems can significantly benefit from densely integrated superconducting multi-layer and multi-signal flexible cables due to the massive number of electrical interconnects needed in systems such as superconducting quantum computers and cryogenic detector arrays. In order to maintain superconductivity in niobium (Nb) thin films, film stress and degradation must be minimized. We are working towards configurations with embedded traces, where it is expected that the superconductor material will be subjected to subsequent fabrication steps that must not degrade the properties of the superconductor. We previously observed degradation of the superconducting properties of Nb, such as reduction of both transition temperature and critical current, as a result of curing a polyimide passivation layer at supplier recommended curing temperature (350 oC). The deterioration in the superconducting properties may be due to mechanical stress in the film or diffusion of impurities into the Nb during the curing process Film stress plays a vital role in the superconducting properties of Nb. Previous research by other groups has focused on in situ ion bombardment, substrate fixturing and wafer preparation in order to minimize film stress. In this work, we discuss the role of argon (Ar) pressure and power during Nb sputtering on the quality of Nb and Nb/Al thin films. By varying the Ar pressure and applied power during sputter deposition, we have produced both tensile and compressive films on flexible substrates in order to find the pressure that yields a near zero stress Nb and Nb/Al thin film at room temperature. A low stress Nb film was tested with a thin Al barrier layer (of the order of 10's of nm) between Nb and polyimide to protect the Nb superconductivity during the PI curing step. Nb traces with a thickness of roughly 250nm and a width of 50um were used for this work. Nb films deposited at different Ar pressures and power levels were tested for critical transition temperature (Tc), critical current (Ic), and sheet resistance (Ω/□), to compare the superconducting behavior of different Nb films. Details of the fabrication processes, experimental procedures and performance results will be presented. This work will help determine materials stacks-ups that may be useful for future multi-layer Nb-based flexible superconducting cables. Acknowledgment: We gratefully acknowledge financial support and technical guidance from Microsoft Research for this work.

Стилі APA, Harvard, Vancouver, ISO та ін.

36

Skvortsov, Arkadiy A., Marina V. Koryachko, Pavel A. Skvortsov, and Mikhail N. Luk'yanov. "The problem of crack formation in thin sublayers of silicon oxide during pulsed heating of interconnects." Journal of Applied Research and Technology 19, no. 2 (April 30, 2021): 77–86. http://dx.doi.org/10.22201/icat.24486736e.2021.19.2.1576.

Повний текст джерела

Анотація:

It is well known that in modern micro- and nanoelectronics thin-film structures are actively used as a gate dielectric, passivating layers, membranes, etc. The research is devoted to the problem of crack formation in thin sublayers of silicon oxide during pulsed heating of interconnects on single-crystal silicon wafers. The purpose of the paper is to study the effect of surface sources of thermal shock on the cracks formation in films and aspects of crack formation in SO2 films have been studied in detail. Experimental verification of the estimates made was carried out on multilayer structures of a silicon substrate-silicon oxide sublayer-aluminum film (Si-SiO2-Al). As substrates, it was used phosphorus-doped silicon single-crystal wafers oriented in the (111) direction, with a resistivity in the range p = 0.1 Ω.сm. The authors studied the temperature fields in silicon wafers (Al-Si system) and silicon oxide wafers (Al-SiO2 system) heated by a surface metallization layer both for the case of a point heat source and for the case of a long rectangular metallization path (provided that the track length significantly exceeds its width). The calculation results showed that the temperature profile of the metallization path (width 75 μm) in the transverse direction is heterogeneous. It was also shown that, in contrast to SiO2 films, the level of appearing mechanical stresses in silicon is insufficient for the formation of cracks near the source of thermal shock. This is due to a higher tensile strength than that of oxide.

Стилі APA, Harvard, Vancouver, ISO та ін.

37

Kumar, S., P. Kumar, and R. Pratap. "Reliability Failure in Microelectronic Interconnects by Electric Current Induced Chemical Reaction." IOP Conference Series: Materials Science and Engineering 1206, no. 1 (November 1, 2021): 012026. http://dx.doi.org/10.1088/1757-899x/1206/1/012026.

Повний текст джерела

Анотація:

Abstract The electric field-induced chemical reaction in Cr thin film by a micro/nano-probe has been recently reported with detailed characterization. Although the phenomenon is employed for micro-nano fabrication, this can act as a reliability failure, where Cr is used as an adhesion layer or main interconnects in microelectronic circuits. Here, we present an investigation on the role of electric current density for such failure using a specifically designed sample. A 100 μm width and 100 nm thin Cr film is deposited perpendicular to the Pt film of similar dimensions. The anode probe (20 μm diameter) is positioned onto the Pt film, whereas the cathode probe onto the Cr film. It is observed that the chemical reaction, for an applied voltage, initiates at the edge of the Pt film and not at the cathode probe. The localized chemical reaction causes to damage the interconnection line. The analysis based on the COMSOL multiphysics simulation illustrates that the chemical reaction evolves at the high current density locations. The study also builds a fundamental understanding of the mechanism of evolution of patterning by electric field-induced chemical reactions.

Стилі APA, Harvard, Vancouver, ISO та ін.

38

Froitzheim, J., and J. E. Svensson. "Nanocoatings for SOFC Interconnects - Mitigating Chromium Volatilization and Improving Corrosion Properties." Materials Science Forum 696 (September 2011): 412–16. http://dx.doi.org/10.4028/www.scientific.net/msf.696.412.

Повний текст джерела

Анотація:

Two important degradation mechanisms in Solid Oxide Fuel Cells (SOFC) are directly related to the metallic interconnects. The formation of volatile chromium oxides from metallic interconnects commonly causes fast degradation in cell performance due to poisoning the cathode. Secondly is the ability of the metallic interconnect to form a thin protective oxide one of the most important lifetime limiting factors for SOFC. Chromium volatilization of various uncoated steels is studied as a function of temperature by a recently developed denuder technique which allows time resolved quantification of volatile chromium species. The inhibition of Cr evaporation by Co thin film coatings (800nm) is investigated; it will be shown that these coatings are more effective than much thicker ceramic coatings that are commonly used for this purpose. In order to increase the lifetime of the metallic components in SOFC nano-coatings of reactive elements (RE) have been investigated as well. The application of such coatings can reduce the corrosion rates substantially and thus increase the lifetime of the fuel cell stack. It will be shown that it is possible to combine the positive effects of RE with the beneficial effects of a Co coating and thus to obtain an interconnect material with low Cr evaporation and increased oxidation resistance.

Стилі APA, Harvard, Vancouver, ISO та ін.

39

Loupis, M. I., J. N. Avaritsiotis, and G. D. Tziallas. "Comparative Study of Statistical Distributions in Electromigration-Induced Failures of Al/Cu Thin-Film Interconnects." Active and Passive Electronic Components 16, no. 2 (1994): 119–26. http://dx.doi.org/10.1155/1994/60298.

Повний текст джерела

Анотація:

In electromigration failure studies, it is in general assumed that electromigration-induced failures may be adequately modelled by a log-normal distribution. Further to this, it has been argued that a lognormal distribution of failure times is indicative of electromigration mechanisms. We have combined post processing of existing life-data from Al/Cu + TiW bilayer interconnects with our own results from Al/Cu interconnects to show that the Log Extreme Value distribution is an equally good statistical model for electromigration failures, even in cases where grain size exceeds the linewidth. The significance of such a modelling is particularly apparent in electromigration failure rate prediction.

Стилі APA, Harvard, Vancouver, ISO та ін.

40

Yuan, X., T. Yamada, and L. Meng. "Strong electro-optic effect in Mg incorporated ZnO thin films." Applied Physics Letters 121, no. 15 (October 10, 2022): 152903. http://dx.doi.org/10.1063/5.0103831.

Повний текст джерела

Анотація:

a-axis oriented ZnMgO epitaxial thin films with a strong linear electro-optic (EO) effect were developed by radio frequency magnetron sputtering. The Mg incorporation into ZnO thin films not only obviously increases the transmittance at the wavelength range of 400–800 nm but also reduces the leakage current by 3–6 orders of magnitude. Furthermore, with the increase in the Mg content, the linear EO response enhances significantly. In particular, the derived effective EO coefficient rc of the Zn0.72Mg0.28O thin film is (7.6 ± 0.2) pm/V, which is over three times larger than the reported values for ZnO-based thin films and over twice larger than that of ZnO single crystals. The results and discussion conclude that an enhanced intrinsic contribution can be responsible for the increase in rc with Mg incorporation. These findings open the way for the ZnO-based thin films to EO devices in optical communication and optical interconnects.

Стилі APA, Harvard, Vancouver, ISO та ін.

41

Otake, Atsushi, Akira Kuroda, Roger Luo, and Paul R. Bernatis. "Introduction of a Dynamic Corrosion Inhibitor for Copper Interconnect Cleaning." Solid State Phenomena 195 (December 2012): 124–27. http://dx.doi.org/10.4028/www.scientific.net/ssp.195.124.

Повний текст джерела

Анотація:

Copper has become the material of choice for the interconnects in semiconductor devices due to its low resistance and ease of processing [1]. Device fabrication with copper requires electrochemical deposition and chemical mechanical planarization (CMP). Since the polished copper surface generated during CMP is considered to be one of the most important factors which determine the performance of the interconnect, post-CMP cleaners must efficiently remove residues generated by the polishing process [2]. CMP slurries and post-CMP cleaners frequently include corrosion inhibitors to form a protecting layer on copper surface. If a thick organic film remains on copper after cleaning processes, it can have unfavorable effects on performance of copper interconnects. To minimize this issue, the authors earlier described a corrosion inhibitor which formed a very thin protective layer and that was easily removed by plasma treatment [3, 4].

Стилі APA, Harvard, Vancouver, ISO та ін.

42

Zeng, Hao, Chao Lv, Yan Gao, Ting Yi Dong, Yong Hui Wang, and Xing Quan Wang. "Ultrahigh Purity Copper Alloy Target Used Innanoscale ULSI Interconnects." Materials Science Forum 815 (March 2015): 22–29. http://dx.doi.org/10.4028/www.scientific.net/msf.815.22.

Повний текст джерела

Анотація:

Current ULSI circuits have features with dimensions in the nanoscale region. As the critical dimension shrinks, Cu BEOL systems face reliability impacts. Alloying has been proved to be a promising technique to retard grain boundary electro-migration (EM). In this paper, dilute Cu Alloys such as Cu-Al, Cu-Mn for dual-damascene interconnect applications have been investigated. The alloy chosen principle for nanoscale interconnects has been discussed. The ultrahigh purity copper alloy target properties including purity, alloy composition, grain size and sputtering performance were investigated, to lay the foundation for the application of the large-size ultrahigh purity copper alloy target used for 300mm wafer fabrication. The relationships between deposited film behaviors and sputtering target properties in some applications were also discussed. In order to acquire high quality thin film, the properties of sputtering target such as alloy composition homogeneity, grain size and uniformity et al. have to be well controlled by proper fabrication techniques.

Стилі APA, Harvard, Vancouver, ISO та ін.

43

Park, Chan Woo, Jae Bon Koo, Chi-Sun Hwang, Hongkeun Park, Sung Gap Im, and Seung-Yun Lee. "Stretchable active matrix of oxide thin-film transistors with monolithic liquid metal interconnects." Applied Physics Express 11, no. 12 (October 29, 2018): 126501. http://dx.doi.org/10.7567/apex.11.126501.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

44

Kim, Choongun, and J. W. Morris. "The mechanism of electromigration failure of narrow Al‐2Cu‐1Si thin‐film interconnects." Journal of Applied Physics 73, no. 10 (May 15, 1993): 4885–93. http://dx.doi.org/10.1063/1.353806.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

45

Kim, Choongun, S. I. Selitser, and J. W. Morris. "Influence of microstructure on the resistivity of Al‐Cu‐Si thin‐film interconnects." Journal of Applied Physics 75, no. 2 (January 15, 1994): 879–84. http://dx.doi.org/10.1063/1.356442.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

46

Lacour, S. P., J. Jones, Z. Suo, and S. Wagner. "Design and Performance of Thin Metal Film Interconnects for Skin-Like Electronic Circuits." IEEE Electron Device Letters 25, no. 4 (April 2004): 179–81. http://dx.doi.org/10.1109/led.2004.825190.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

47

Bedouani, M., D. Lambert, and K. Kurzweil. "Electrical performance of interconnects in polyimide-copper thin-film multilayers on ceramic substrate." IEEE Transactions on Components, Packaging, and Manufacturing Technology: Part B 19, no. 2 (May 1996): 382–90. http://dx.doi.org/10.1109/96.496042.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

48

Clemens, B. M., and J. A. Bain. "Stress Determination in Textured Thin Films Using X-Ray Diffraction." MRS Bulletin 17, no. 7 (July 1992): 46–51. http://dx.doi.org/10.1557/s0883769400041658.

Повний текст джерела

Анотація:

Thin film stresses are important in many areas of technology. In the semiconductor industry, metal interconnects are prone to stress voiding and hillock formation. Stresses in passivation layers can lead to excessive substrate curvature which can cause alignment difficulty in subsequent lithographic processing. In other thin film applications, stresses can cause peeling from mechanical failure at the film-substrate interface. Beyond these issues of reliability, stress and the resulting strain can be used to tune the properties of thin film materials. For instance, strain, coupled with the magnetostrictive effect, can be utilized to induce the preferred magnetization direction. Also, epitaxial strains can be used to adjust the bandgap of semiconductors. Finally, the anomalous mechanical properties of multilayered materials are thought to be partially due to the extreme strain states in the constituents of these materials. To fully optimize thin film performance, a fundamental understanding of the causes and effects of thin film stress is needed. These studies in turn rely on detailed characterization of the stress and strain state of thin films.X-ray diffraction and the elastic response of materials provide a powerful method for determining stresses. Stresses alter the spacing of crystallographic planes in crystals by amounts easily measured by x-ray diffraction. Each set of crystal planes can act as an in-situ strain gauge, which can be probed by x-ray diffraction in the appropriate geometry. Hence it is not surprising that x-ray diffraction is one of the most widely used techniques for determining stress and strain in materials. (For reviews of this topic, see References 5–7.) This article is a tutorial on the use of x-ray diffraction to extract the stress state and the unstrained lattice parameter from thin films. We present a handbook of useful results that can be widely applied and should be mastered by anyone seriously interested in stresses in crystalline thin films with a crystallographic growth texture.

Стилі APA, Harvard, Vancouver, ISO та ін.

49

Choi, Eunmi, and Sunggyu Pyo. "Effect of Pulsed Light Irradiation on Patterning of Reduction Graphene Oxide-Graphene Oxide Interconnects for Power Devices." Coatings 11, no. 9 (August 30, 2021): 1042. http://dx.doi.org/10.3390/coatings11091042.

Повний текст джерела

Анотація:

Reduction graphene oxide (r-GO) lines on graphene oxide (GO) films can be prepared by a photocatalytic reduction and photothermal reduction method. A mechanism of partial GO reduction by pulsed photon energy is identified for preparing patterned rGO-GO films. The photocatalytic reduction method efficiently reduces GO at low photon energies. The successful production of a patterned rGO-GO film without damage by the photo thermal reduction method is possible when an energy density of 6.0 or 6.5 J/m2 per pulse is applied to a thin GO film (thickness: 0.45 μm). The lowest resistance obtained for a photo-reduced rGO line is 0.9 kΩ sq−1. The GO-TiO2 pattern fabricated on the 0.23 μm GO-TiO2 composite sheet through the energy density of each pulse is 5.5 J/m2 for three pulses.

Стилі APA, Harvard, Vancouver, ISO та ін.

50

Takayama, Shinji. "Low resistivity Al–RE (RE=La, Pr, and Nd) alloy thin films with high thermal stability for thin-film-transistor interconnects." Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures 14, no. 5 (September 1996): 3257. http://dx.doi.org/10.1116/1.588817.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

Статті в журналах з теми "Thin film interconnects"

Оформте джерело за APA, MLA, Chicago, Harvard та іншими стилями