Готові списки джерел за темами / Test parallelization

Добірка наукової літератури з теми "Test parallelization"

Автор: Grafiati

Опубліковано: 30 травня 2022

Оновлено: 31 травня 2022

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Статті в журналах з теми "Test parallelization"

Rauchwerger, L., and D. A. Padua. "The LRPD test: speculative run-time parallelization of loops with privatization and reduction parallelization." IEEE Transactions on Parallel and Distributed Systems 10, no. 2 (1999): 160–80. http://dx.doi.org/10.1109/71.752782.

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Son, Changhwan, Wooyeol Park, HyeongGyun Kim, KyungSook Han, and Changwoo Pyo. "Parallelization of CUSUM Test in a CUDA Environment." KIISE Transactions on Computing Practices 21, no. 7 (July 15, 2015): 476–81. http://dx.doi.org/10.5626/ktcp.2015.21.7.476.

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Kong, X., D. Klappholz, and K. Psarris. "The I test: an improved dependence test for automatic parallelization and vectorization." IEEE Transactions on Parallel and Distributed Systems 2, no. 3 (July 1991): 342–49. http://dx.doi.org/10.1109/71.86109.

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DEBBI, Aimad Eddine, and Haddi BAKHTI. "Incremental Banerjee test conditions committing for robust parallelization framework." TURKISH JOURNAL OF ELECTRICAL ENGINEERING & COMPUTER SCIENCES 26, no. 5 (September 28, 2018): 2595–604. http://dx.doi.org/10.3906/elk-1712-374.

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Zhang, Lei, Guo Xin Zhang, Yi Liu, and Hai Lin Pan. "Parallelization Development Method and Realization for a FEM Simulation Program." Applied Mechanics and Materials 405-408 (September 2013): 3169–72. http://dx.doi.org/10.4028/www.scientific.net/amm.405-408.3169.

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The parallel computation of equation sets solution are crucial for finite element analysis. The paper discussed the key technology of FEM parallelization and the parallelization strategy for the FEM program is given; and then discussed the Data structure of Aztec and how to call Aztec which consists of Krylov subspace iterative methods solvers and preconditioners; finally, the realization and testing of the Aztec-based finite element program parallelization was put forward. Test results show that there are high efficiency of this method which make the SapTis software more powerful, flexible and adaptable.

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Moon, Sungdo, Byoungro So, and Mary W. Hall. "Combining Compile-Time and Run-Time Parallelization." Scientific Programming 7, no. 3-4 (1999): 247–60. http://dx.doi.org/10.1155/1999/490628.

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This paper demonstrates that significant improvements to automatic parallelization technology require that existing systems be extended in two ways: (1) they must combine high‐quality compile‐time analysis with low‐cost run‐time testing; and (2) they must take control flow into account during analysis. We support this claim with the results of an experiment that measures the safety of parallelization at run time for loops left unparallelized by the Stanford SUIF compiler’s automatic parallelization system. We present results of measurements on programs from two benchmark suites – SPECFP95and NASsample benchmarks – which identify inherently parallel loops in these programs that are missed by the compiler. We characterize remaining parallelization opportunities, and find that most of the loops require run‐time testing, analysis of control flow, or some combination of the two. We present a new compile‐time analysis technique that can be used to parallelize most of these remaining loops. This technique is designed to not only improve the results of compile‐time parallelization, but also to produce low‐cost, directed run‐time tests that allow the system to defer binding of parallelization until run‐time when safety cannot be proven statically. We call this approachpredicated array data‐flow analysis. We augment array data‐flow analysis, which the compiler uses to identify independent and privatizable arrays, by associating predicates with array data‐flow values. Predicated array data‐flow analysis allows the compiler to derive “optimistic” data‐flow values guarded by predicates; these predicates can be used to derive a run‐time test guaranteeing the safety of parallelization.

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Depolli, Matjaž, Roman Trobec, and Bogdan Filipič. "Asynchronous Master-Slave Parallelization of Differential Evolution for Multi-Objective Optimization." Evolutionary Computation 21, no. 2 (May 2013): 261–91. http://dx.doi.org/10.1162/evco_a_00076.

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In this paper, we present AMS-DEMO, an asynchronous master-slave implementation of DEMO, an evolutionary algorithm for multi-objective optimization. AMS-DEMO was designed for solving time-intensive problems efficiently on both homogeneous and heterogeneous parallel computer architectures. The algorithm is used as a test case for the asynchronous master-slave parallelization of multi-objective optimization that has not yet been thoroughly investigated. Selection lag is identified as the key property of the parallelization method, which explains how its behavior depends on the type of computer architecture and the number of processors. It is arrived at analytically and from the empirical results. AMS-DEMO is tested on a benchmark problem and a time-intensive industrial optimization problem, on homogeneous and heterogeneous parallel setups, providing performance results for the algorithm and an insight into the parallelization method. A comparison is also performed between AMS-DEMO and generational master-slave DEMO to demonstrate how the asynchronous parallelization method enhances the algorithm and what benefits it brings compared to the synchronous method.

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Bukáček, Michal. "On SOMA Parallelization with Android Devices." Journal of Advanced Engineering and Computation 3, no. 3 (September 30, 2019): 441. http://dx.doi.org/10.25073/jaec.201933.247.

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Today's world is full of new, small, personal handhelds. They are called smartphones or tablets. The machines themselves always have less power than desktop computers or even mainframes which were left behind. Their computational power can be increased when they are joined together in a group and are addressing one common task. To check and demonstrate the possibility of the use of mobile devices being joined to a group, the SOMA algorithm was chosen. The well as known functions, for example; De Jong, Rosenbrock, Rastrigin or Schwefel will be used and their extremes (minimums) will be realized. The goal is to test the speed of these mobile devices to realize the extremes of more dimensional functions. The advantages and disadvantages of this swarm linking will be shown. This is an Open Access article distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/4.0/), which permits unrestricted use, distribution, and reproduction in any medium provided the original work is properly cited.

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Samardzic, Aleksandar, Dusan Starcevic, and Milan Tuba. "An implementation of ray tracing algorithm for the multiprocessor machines." Yugoslav Journal of Operations Research 16, no. 1 (2006): 125–35. http://dx.doi.org/10.2298/yjor0601125s.

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Ray Tracing is an algorithm for generating photo-realistic pictures of the 3D scenes, given scene description, lighting condition and viewing parameters as inputs. The algorithm is inherently convenient for parallelization and the simplest parallelization scheme is for the shared-memory parallel machines (multiprocessors). This paper presents two implementations of the algorithm developed by the authors for alike machines, one using the POSIX threads API and another one using the OpenMP API. The paper also presents results of rendering some test scenes using these implementations and discusses our parallel algorithm version efficiency.

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Martynenko, S. I. "Potentialities of the Robust Multigrid Technique." Computational Methods in Applied Mathematics 10, no. 1 (2010): 87–94. http://dx.doi.org/10.2478/cmam-2010-0004.

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AbstractThe present paper discusses the parallelization of the robust multigrid technique (RMT) and the possible way of applying this to unstructured grids. As opposed to the classical multigrid methods, the RMT is a trivial method of parallelization on coarse grids independent of the smoothing iterations. Estimates of the minimum speed-up and parallelism efficiency are given. An almost perfect load balance is demonstrated in a 3D illustrative test. To overcome the geometric nature of the technique, the RMT is used as a preconditioner in solving PDEs on unstructured grids. The procedure of auxiliary structured grids generation is considered in details.

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Більше джерел

Дисертації з теми "Test parallelization"

Бєй, Олександр Вікторович. "Система автоматизації процесів тестування програмного забезпечення з використанням паралелізації тестів". Master's thesis, Київ, 2018. https://ela.kpi.ua/handle/123456789/25514.

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У магістерській дисертації розроблено систему автоматизації процесів тестування програмного забезпечення із використанням паралелізації тестів. Метою даної роботи було створення системи для автоматичної перевірки функціоналу тестованого об'єкта зі зручним інтерфейсом виводу помилок. Відповідно до поставленої мети було розроблено та протестовано систему автоматизації процесів тестування програмного забезпечення із використанням паралелізації тестів. В дисертації розроблено структурна схема, схема послідовності, діаграма варіантів використання, алгоритм роботи системи та інші. В роботі розглянуто особливості деяких інструментів для автоматизації тестування та успішно використанні на практиці. Значну увагу в роботі приділено розробці фреймворка для тестування, завдяки якому швидкість написання автоматизованих тестів значно зростає. При цьому було розроблено схему роботи системи та робочу програму мовою Java. Результати цього моделювання підтвердили достовірність теоретичних відомостей. Робота може бути корисною для компаній, націлених на розвиток напрямку тестування, автоматизації процесу тестування і підвищення якості свого продукту, оскільки в роботі описані необхідні теоретичні основи, більш того, проаналізовані критерії ефективності процесу тестування. Робота містить 100 с. тексту, 49 рисунків, 20 літературних джерел та 3 додатка.
In the master's thesis was developed the system of software testing processes automation with the use of parallelization of tests. The purpose of this work was to create a system for automatically verifying the functionality of the tested object with a user-friendly error-handling interface. In accordance with the stated goal, the system of automation of software testing processes was developed and tested with the use of parallel tests. In the dissertation the structural scheme, the sequence diagram, the diagram of variants of use, the algorithm of system operation and others are developed. The paper considers the features of some tools for testing automation and successfully used in practice. Considerable attention in the work is devoted to the development of a framework for testing, thanks to which the speed of writing automated tests greatly increases. At the same time, the scheme of work of the system and the working program in the Java language was developed. The results of this simulation confirmed the reliability of the theoretical information. The work may be useful for companies aimed at developing the testing direction, automating the testing process and improving the quality of their product, since the paper describes the necessary theoretical foundations, moreover, analyzes the criteria for the effectiveness of the testing process. The work contains 100 s. text, 49 drawings, 20 literary sources and 3 appendices.
В магистерской диссертации разработана система автоматизации процессов тестирования программного обеспечения с использованием параллелизация тестов. Целью данной работы было создание системы для автоматической проверки функционала тестируемого объекта с удобным интерфейсом вывода ошибок. Согласно поставленной цели была разработана и протестирована система автоматизации процессов тестирования программного обеспечения с использованием параллелизация тестов. В диссертации разработаны структурная схема, схема последовательности, диаграмма вариантов использования, алгоритм работы системы и другие. В работе рассмотрены особенности некоторых инструментов для автоматизации тестирования и успешно использовании на практике. Значительное внимание в работе уделено разработке фреймворка для тестирования, благодаря которому скорость написания автоматизированных тестов значительно возрастает. При этом была разработана схема работы системы и рабочую программу на языке Java. Результаты этого моделирования подтвердили достоверность теоретических сведений. Работа может быть полезна для компаний, нацеленных на развитие направления тестирования, автоматизации процесса тестирования и повышения качества своего продукта, поскольку в работе описаны необходимые теоретические основы, более того, проанализированы критерии эффективности процесса тестирования.

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Cantenot, Jérôme. "Stratégies de génération de tests à partir de modèles UML/OCL interprétés en logique du premier ordre et système de contraintes." Thesis, Besançon, 2013. http://www.theses.fr/2013BESA2042/document.

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Les travaux présentés dans cette thèse proposent une méthode de génération automatique de tests à partir de modèles.Cette méthode emploie deux langages de modélisations UML4MBT et OCL4MBT qui ont été spécifiquement dérivées d’ UML et OCL pour la génération de tests. Ainsi les comportements, la structure et l’état initial du système sont décrits au travers des diagrammes de classes, d’objets et d’états-transitions.Pour générer des tests, l’évolution du modèle est représente sous la forme d’un système de transitions. Ainsi la construction de tests est équivalente à la découverte de séquences de transitions qui relient l’´état initial du système à des états validant les cibles de test.Ces séquences sont obtenues par la résolution de scénarios d’animations par des prouveurs SMT et solveurs CSP. Pour créer ces scénarios, des méta-modèles UML4MBT et CSP4MBT regroupant formules logiques et notions liées aux tests ont été établies pour chacun des outils.Afin d’optimiser les temps de générations, des stratégies ont été développé pour sélectionner et hiérarchiser les scénarios à résoudre. Ces stratégies s’appuient sur la parallélisation, les propriétés des solveurs et des prouveurs et les caractéristiques de nos encodages pour optimiser les performances. 5 stratégies emploient uniquement un prouveur et 2 stratégies reposent sur une collaboration du prouveur avec un solveur.Finalement l’intérêt de cette nouvelle méthode à été validée sur des cas d’études grâce à l’implémentation réalisée
This thesis describes an automatic test generation process from models.This process uses two modelling languages, UML4MBT and OCL4MBT, created specificallyfor tests generation. Theses languages are derived from UML and OCL. Therefore the behaviours,the structure and the initial state of the system are described by the class diagram, the objectdiagram and the state-chart.To generate tests, the evolution of the model is encoded with a transition system. Consequently,to construct a test is to find transition sequences that rely the initial state of the system to thestates described by the test targets.The sequence are obtained by the resolution of animation scenarios. This resolution is executedby SMT provers and CSP solvers. To create the scenario, two dedicated meta-models, UML4MBTand CSP4MBT have been established. Theses meta-models associate first order logic formulas withthe test notions.7 strategies have been developed to improve the tests generation time. A strategy is responsiblefor the selection and the prioritization of the scenarios. A strategy is built upon the properties ofthe solvers and provers and the specification of our encoding process. Moreover the process canalso be paralleled to get better performance. 5 strategies employ only a prover and 2 make theprover collaborate with a solver.Finally the interest of this process has been evaluated through a list of benchmark on variouscases studies

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Breitenbacher, Dominik. "Paralelizace faktorizace celých čísel z pohledu lámání RSA." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2015. http://www.nusl.cz/ntk/nusl-234905.

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This paper follows up the factorization of integers. Factorization is the most popular and used method for RSA cryptoanalysis. The SIQS was chosen as a factorization method that will be used in this paper. Although SIQS is the fastest method (up to 100 digits), it can't be effectively computed at polynomial time, so it's needed to look up for options, how to speed up the method as much as possible. One of the possible ways is paralelization. In this case OpenMP was used. Other possible way is optimalization. The goal of this paper is also to show, how easily is possible to use paralelizion and thanks to detailed analyzation the source codes one can reach relatively large speed up. Used method of iterative optimalization showed itself as a very effective tool. Using this method the implementation of SIQS achieved almost 100 multiplied speed up and at some parts of the code even more.

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Doležal, Jan. "Komponent pro sémantické obohacení." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2018. http://www.nusl.cz/ntk/nusl-385991.

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This master's thesis describes Semantic Enrichment Component (SEC), that searches entities (e.g., persons or places) in the input text document and returns information about them. The goals of this component are to create a single interface for named entity recognition tools, to enable parallel document processing, to save memory while using the knowledge base, and to speed up access to its content. To achieve these goals, the output of the named entity recognition tools in the text was specified, the tool for storing the preprocessed knowledge base into the shared memory was implemented, and the client-server scheme was used to create the component.

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Neto, Nuno Miguel Ladeira. "A Container-based architecture for accelerating software tests via setup state caching and parallelization." Master's thesis, 2019. https://hdl.handle.net/10216/122203.

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Частини книг з теми "Test parallelization"

Ionescu, Felicia, Mihail Ionescu, Cristina Coconu, and Valentin Stoica. "Coarse-Grain Parallelization of Test Vectors Generation on Multiprocessor Systems." In Lecture Notes in Computer Science, 231–40. Berlin, Heidelberg: Springer Berlin Heidelberg, 2002. http://dx.doi.org/10.1007/3-540-47840-x_24.

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Huang, Tsung-Chuan, and Po-Hsueh Hsu. "The SPNT test: A new technology for run-time speculative parallelization of loops." In Languages and Compilers for Parallel Computing, 177–91. Berlin, Heidelberg: Springer Berlin Heidelberg, 1998. http://dx.doi.org/10.1007/bfb0032691.

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Udupa, Pradeep, S. Nithyanandam, and A. Rijuvana Begum. "An Efficient Method for Testing Source Code by Test Case Reduction, Prioritization, and Prioritized Parallelization." In Advances in Intelligent Systems and Computing, 513–21. Singapore: Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-13-8618-3_53.

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Moylan, Patrick. "Parallelizations for Induced Representations of $$\text {SO}_0(2,q)$$." In Springer Proceedings in Mathematics & Statistics, 219–29. Singapore: Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-13-2715-5_12.

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Dematties, Dario, George K. Thiruvathukal, Silvio Rizzi, Alejandro Wainselboim, and B. Silvano Zanutto. "Towards High-End Scalability on Biologically-Inspired Computational Models." In Parallel Computing: Technology Trends. IOS Press, 2020. http://dx.doi.org/10.3233/apc200077.

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The interdisciplinary field of neuroscience has made significant progress in recent decades, providing the scientific community in general with a new level of understanding on how the brain works beyond the store-and-fire model found in traditional neural networks. Meanwhile, Machine Learning (ML) based on established models has seen a surge of interest in the High Performance Computing (HPC) community, especially through the use of high-end accelerators, such as Graphical Processing Units(GPUs), including HPC clusters of same. In our work, we are motivated to exploit these high-performance computing developments and understand the scaling challenges for new–biologically inspired–learning models on leadership-class HPC resources. These emerging models feature sparse and random connectivity profiles that map to more loosely-coupled parallel architectures with a large number of CPU cores per node. Contrasted with traditional ML codes, these methods exploit loosely-coupled sparse data structures as opposed to tightly-coupled dense matrix computations, which benefit from SIMD-style parallelism found on GPUs. In this paper we introduce a hybrid Message Passing Interface (MPI) and Open Multi-Processing (OpenMP) parallelization scheme to accelerate and scale our computational model based on the dynamics of cortical tissue. We ran computational tests on a leadership class visualization and analysis cluster at Argonne National Laboratory. We include a study of strong and weak scaling, where we obtained parallel efficiency measures with a minimum above 87% and a maximum above 97% for simulations of our biologically inspired neural network on up to 64 computing nodes running 8 threads each. This study shows promise of the MPI+OpenMP hybrid approach to support flexible and biologically-inspired computational experimental scenarios. In addition, we present the viability in the application of these strategies in high-end leadership computers in the future.

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Тези доповідей конференцій з теми "Test parallelization"

Mondal, Shouvick, Denini Silva, and Marcelo d'Amorim. "Soundy Automated Parallelization of Test Execution." In 2021 IEEE International Conference on Software Maintenance and Evolution (ICSME). IEEE, 2021. http://dx.doi.org/10.1109/icsme52107.2021.00034.

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Chemeris, Alexander, Julia Gorunova, and Dmiry Lazorenko. "Loop nests parallelization for digital system synthesis." In 2013 11th East-West Design and Test Symposium (EWDTS). IEEE, 2013. http://dx.doi.org/10.1109/ewdts.2013.6673180.

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Radhakrishnan, Hari, Damian W. I. Rouson, Karla Morris, Sameer Shende, and Stavros C. Kassinos. "Test-driven coarray parallelization of a legacy Fortran application." In the 1st International Workshop. New York, New York, USA: ACM Press, 2013. http://dx.doi.org/10.1145/2532352.2532356.

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Yuwan, Gu, Sun Yuqia, Zhou Tiantong, and Qiao Zengwei. "The Study of Program Control Structure Test Algorithm Parallelization." In 2010 International Conference on Electrical and Control Engineering (ICECE). IEEE, 2010. http://dx.doi.org/10.1109/icece.2010.1397.

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Geuns, S. J., M. J. G. Bekooij, T. Bijlsma, and H. Corporaal. "Parallelization of while loops in nested loop programs for shared-memory multiprocessor systems." In 2011 Design, Automation & Test in Europe. IEEE, 2011. http://dx.doi.org/10.1109/date.2011.5763118.

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Dang, F., Hao Yu, and L. Rauchwerger. "The R-LRPD test: speculative parallelization of partially parallel loops." In Proceedings 16th International Parallel and Distributed Processing Symposium. IPDPS 2002. IEEE, 2002. http://dx.doi.org/10.1109/ipdps.2002.1015493.

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Aguilar, Miguel Angel, Rainer Leupers, Gerd Ascheid, Nikolaos Kavvadias, and Liam Fitzpatrick. "Schedule-aware loop parallelization for embedded MPSoCs by exploiting parallel slack." In 2017 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 2017. http://dx.doi.org/10.23919/date.2017.7927178.

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Zrida, H. K., A. Jemai, A. C. Ammari, and M. Abid. "High level H.264/AVC video encoder parallelization for multiprocessor implementation." In 2009 Design, Automation & Test in Europe Conference & Exhibition (DATE'09). IEEE, 2009. http://dx.doi.org/10.1109/date.2009.5090800.

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Yuhui, Wang, Lei Xiaohui, Jiang Yunzhong, and Song Xinshan. "Parallelization and Performance Test to Multiple Objective Particle Swarm Optimization Algorithm." In 2010 International Forum on Information Technology and Applications (IFITA). IEEE, 2010. http://dx.doi.org/10.1109/ifita.2010.109.

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Chugunkov, I. V., A. A. Dyumin, A. A. Maksutov, and I. S. Smirnova. "Parallelization of test for assessing pseudorandom number generators using CUDA technology." In 2015 IEEE NW Russia Young Researchers in Electrical and Electronic Engineering Conference (EIConRusNW). IEEE, 2015. http://dx.doi.org/10.1109/eiconrusnw.2015.7102232.

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