Статті в журналах з теми "TCAD Design"
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Bellini, Marco, and Lars Knoll. "Advanced TCAD Design Techniques for the Performance Improvement of SiC MOSFETs." Materials Science Forum 1004 (July 2020): 865–71. http://dx.doi.org/10.4028/www.scientific.net/msf.1004.865.
Повний текст джерелаJohannesson, Daniel, Muhammad Nawaz, and Hans Peter Nee. "TCAD Model Calibration of High Voltage 4H-SiC Bipolar Junction Transistors." Materials Science Forum 963 (July 2019): 670–73. http://dx.doi.org/10.4028/www.scientific.net/msf.963.670.
Повний текст джерелаRehman, Atta Ur, Amna Siddiqui, Muhammad Nadeem, and Muhammad Usman. "Improved PERC Solar Cell Design by TCAD Simulation." Proceedings of the Pakistan Academy of Sciences: A. Physical and Computational Sciences 58, no. 4 (March 28, 2022): 61–67. http://dx.doi.org/10.53560/ppasa(58-4)637.
Повний текст джерелаPan, Zijin, Cheng Li, Mengfu Di, Feilong Zhang, and Albert Wang. "3D TCAD Analysis Enabling ESD Layout Design Optimization." IEEE Journal of the Electron Devices Society 8 (2020): 1289–96. http://dx.doi.org/10.1109/jeds.2020.3027034.
Повний текст джерелаWoo, Sola, Juhee Jeon, and Sangsig Kim. "Prediction of Device Characteristics of Feedback Field-Effect Transistors Using TCAD-Augmented Machine Learning." Micromachines 14, no. 3 (February 21, 2023): 504. http://dx.doi.org/10.3390/mi14030504.
Повний текст джерелаSingh, Vivek. "Relevance of technology computer aided design (TCAD) to process-aware design." Journal of Micro/Nanolithography, MEMS, and MOEMS 1, no. 3 (October 1, 2002): 290. http://dx.doi.org/10.1117/1.1508411.
Повний текст джерелаChen, Yu-Guang, Hui Geng, Kuan-Yu Lai, Yiyu Shi, and Shih-Chieh Chang. "Multibit Retention Registers for Power Gated Designs: Concept, Design, and Deployment." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 33, no. 4 (April 2014): 507–18. http://dx.doi.org/10.1109/tcad.2013.2293881.
Повний текст джерелаWang, Ke, Haodong Jiang, Yiming Liao, Yue Xu, Feng Yan, and Xiaoli Ji. "Degradation Prediction of GaN HEMTs under Hot-Electron Stress Based on ML-TCAD Approach." Electronics 11, no. 21 (November 2, 2022): 3582. http://dx.doi.org/10.3390/electronics11213582.
Повний текст джерелаMa, Qiang, and Evangeline F. Y. Young. "Multivoltage Floorplan Design." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 29, no. 4 (April 2010): 607–17. http://dx.doi.org/10.1109/tcad.2010.2042895.
Повний текст джерелаNandi, Prajit, Hirak Talukdar, Dhiraj Kumar, and Ashvin Kumar G. Katakwar. "A Novel Approach to Design SAR-ADC: Design Partitioning Method." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 35, no. 3 (March 2016): 346–56. http://dx.doi.org/10.1109/tcad.2015.2474379.
Повний текст джерелаPotbhare, Siddharth, Akin Akturk, Neil Goldsman, James M. McGarrity, and Anant Agarwal. "Modeling and Design of High Temperature Silicon Carbide DMOSFET Based Medium Power DC-DC Converter." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2010, HITEC (January 1, 2010): 000144–51. http://dx.doi.org/10.4071/hitec-spotbhare-tp22.
Повний текст джерелаKwon, Hyoungcheol, Hyunsuk Huh, Hwiwon Seo, Songhee Han, Imhee Won, Jiwoong Sue, Dongyean Oh, et al. "TCAD augmented generative adversarial network for hot-spot detection and mask-layout optimization in a large area HARC etching process." Physics of Plasmas 29, no. 7 (July 2022): 073504. http://dx.doi.org/10.1063/5.0093076.
Повний текст джерелаHu, Shiyan, Xiaobo Sharon Hu, and Albert Y. Zomaya. "Guest Editorial Leveraging Design Automation Techniques for Cyber-Physical System Design." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 35, no. 5 (May 2016): 697–98. http://dx.doi.org/10.1109/tcad.2016.2548179.
Повний текст джерелаVeneris, A., and M. S. Abadir. "Design rewiring using ATPG." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 21, no. 12 (December 2002): 1469–79. http://dx.doi.org/10.1109/tcad.2002.804388.
Повний текст джерелаKagalwalla, Abde Ali, Puneet Gupta, Christopher J. Progler, and Steve McDonald. "Design-Aware Mask Inspection." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 31, no. 5 (May 2012): 690–702. http://dx.doi.org/10.1109/tcad.2011.2181909.
Повний текст джерелаKahng, A. B., Seokhyeong Kang, R. Kumar, and J. Sartori. "Recovery-Driven Design: Exploiting Error Resilience in Design of Energy-Efficient Processors." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 31, no. 3 (March 2012): 404–17. http://dx.doi.org/10.1109/tcad.2011.2172610.
Повний текст джерелаLudwig, Tobias, Joakim Urdahl, Dominik Stoffel, and Wolfgang Kunz. "Properties First—Correct-By-Construction RTL Design in System-Level Design Flows." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 39, no. 10 (October 2020): 3093–106. http://dx.doi.org/10.1109/tcad.2019.2921319.
Повний текст джерелаChen, H. M., I. M. Liu, and M. D. F. Wong. "I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25, no. 11 (November 2006): 2552–56. http://dx.doi.org/10.1109/tcad.2006.873900.
Повний текст джерелаFanshu Jiao, Sergio Montano, Cristian Ferent, Alex Doboli, and Simona Doboli. "Analog Circuit Design Knowledge Mining: Discovering Topological Similarities and Uncovering Design Reasoning Strategies." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 34, no. 7 (July 2015): 1045–58. http://dx.doi.org/10.1109/tcad.2015.2418287.
Повний текст джерелаBrisk, Philip, Suman Chakraborty, Claudionor Coelho, Abdoulaye Gamatie, Swaroop Ghosh, and Xun Jiao. "TCAD EIC Message: February 2019." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 38, no. 2 (February 2019): 197–98. http://dx.doi.org/10.1109/tcad.2018.2890315.
Повний текст джерелаRazdan, R., and A. Strojwas. "A Statistical Design Rule Developer." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 5, no. 4 (October 1986): 508–20. http://dx.doi.org/10.1109/tcad.1986.1270222.
Повний текст джерелаKane, R., and S. Sahni. "A Systolic Design-Rule Checker." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 6, no. 1 (January 1987): 22–32. http://dx.doi.org/10.1109/tcad.1987.1270242.
Повний текст джерелаGnudi, A., P. Ciampolini, R. Guerrieri, M. Rudan, and G. Baccarani. "Sensitivity Analysis for Device Design." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 6, no. 5 (September 1987): 879–85. http://dx.doi.org/10.1109/tcad.1987.1270330.
Повний текст джерелаDe Smedt, B., and G. G. E. Gielen. "Watson: design space boundary exploration and model generation for analog and RF IC design." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 22, no. 2 (February 2003): 213–24. http://dx.doi.org/10.1109/tcad.2002.806598.
Повний текст джерелаDobre, Sorin Adrian, Andrew B. Kahng, and Jiajia Li. "Design Implementation With Noninteger Multiple-Height Cells for Improved Design Quality in Advanced Nodes." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 37, no. 4 (April 2018): 855–68. http://dx.doi.org/10.1109/tcad.2017.2731679.
Повний текст джерелаTao, Nick G. M., Bo-Rong Lin, Chien-Ping Lee, Tim Henderson, and Barry J. F. Lin. "Study on mechanisms of InGaP/GaAs HBT safe operating area using TCAD simulation." International Journal of Microwave and Wireless Technologies 7, no. 3-4 (April 10, 2015): 279–85. http://dx.doi.org/10.1017/s1759078715000495.
Повний текст джерелаDash, T. P., S. Dey, S. Das, J. Jena, E. Mahapatra, and C. K. Maiti. "Source/Drain Stressor Design for Advanced Devices at 7 nm Technology Node." Nanoscience & Nanotechnology-Asia 10, no. 4 (August 26, 2020): 447–56. http://dx.doi.org/10.2174/2210681209666190809101307.
Повний текст джерелаPangrle, B. M., and D. D. Gajski. "Design Tools for Intelligent Silicon Compilation." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 6, no. 6 (November 1987): 1098–112. http://dx.doi.org/10.1109/tcad.1987.1270350.
Повний текст джерелаYongseok Cheon and M. D. F. Wong. "Design hierarchy-guided multilevel circuit partitioning." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 22, no. 4 (April 2003): 420–27. http://dx.doi.org/10.1109/tcad.2003.809659.
Повний текст джерелаQiang Xu and N. Nicolici. "Multifrequency TAM design for hierarchical SOCs." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25, no. 1 (January 2006): 181–96. http://dx.doi.org/10.1109/tcad.2005.852440.
Повний текст джерелаCheng, Lei, and Martin D. F. Wong. "Floorplan Design for Multimillion Gate FPGAs." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25, no. 12 (December 2006): 2795–805. http://dx.doi.org/10.1109/tcad.2006.882481.
Повний текст джерелаJaffari, J., and M. Anis. "Variability-Aware Bulk-MOS Device Design." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 27, no. 2 (February 2008): 205–16. http://dx.doi.org/10.1109/tcad.2007.907234.
Повний текст джерелаChen, Yibin, Sean Safarpour, Joao Marques-Silva, and Andreas Veneris. "Automated Design Debugging With Maximum Satisfiability." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 29, no. 11 (November 2010): 1804–17. http://dx.doi.org/10.1109/tcad.2010.2061270.
Повний текст джерелаPan, David Z., Bei Yu, and Jhih-Rong Gao. "Design for Manufacturing With Emerging Nanolithography." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 32, no. 10 (October 2013): 1453–72. http://dx.doi.org/10.1109/tcad.2013.2276751.
Повний текст джерелаSpoto, J. P., W. T. Coston, and C. Paul Hernandez. "Statistical Integrated Circuit Design and Characterization." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 5, no. 1 (January 1986): 90–103. http://dx.doi.org/10.1109/tcad.1986.1270180.
Повний текст джерелаKung-Chao Chu, J. P. Fishburn, P. Honeyman, and Y. E. Lien. "A Database-Driven VLSI Design System." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 5, no. 1 (January 1986): 180–87. http://dx.doi.org/10.1109/tcad.1986.1270185.
Повний текст джерелаChang, Wanli, Dip Goswami, Samarjit Chakraborty, Lei Ju, Chun Jason Xue, and Sidharta Andalam. "Memory-Aware Embedded Control Systems Design." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 36, no. 4 (April 2017): 586–99. http://dx.doi.org/10.1109/tcad.2016.2613933.
Повний текст джерелаPhung, L. V., D. Planson, P. Brosselard, D. Tournier, and C. Brylinski. "3D TCAD Simulations for More Efficient SiC Power Devices Design." ECS Transactions 58, no. 4 (August 31, 2013): 331–39. http://dx.doi.org/10.1149/05804.0331ecst.
Повний текст джерелаKuruvilla, Nisha. "National Workshop on Advanced Nanoscale Device Design Using TCAD [Chapters]." IEEE Solid-State Circuits Magazine 8, no. 4 (2016): 94–95. http://dx.doi.org/10.1109/mssc.2016.2601525.
Повний текст джерелаLim, Wee Han, Amy L. Ziebell, Iwan Cornelius, Mark I. Reinhard, Dale A. Prokopovich, Andrew S. Dzurak, and Anatoly B. Rosenfeld. "Cylindrical Silicon-on-Insulator Microdosimeter: Design, Fabrication and TCAD Modeling." IEEE Transactions on Nuclear Science 56, no. 2 (April 2009): 424–28. http://dx.doi.org/10.1109/tns.2009.2013467.
Повний текст джерелаBoufouss, E., J. Alvarado, and D. Flandre. "Compact modeling of the high temperature effect on the single event transient current generated by heavy ions in SOI 6T-SRAM." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2010, HITEC (January 1, 2010): 000077–82. http://dx.doi.org/10.4071/hitec-eboufouss-ta25.
Повний текст джерелаIshikawa, M., T. Matsuda, T. Yoshimura, and S. Goto. "Compaction-Based Custom LSI Layout Design Method." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 6, no. 3 (May 1987): 374–82. http://dx.doi.org/10.1109/tcad.1987.1270282.
Повний текст джерелаModarres, H., and R. J. Lomax. "A Formal Approach to Design-Rule Checking." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 6, no. 4 (July 1987): 561–73. http://dx.doi.org/10.1109/tcad.1987.1270303.
Повний текст джерелаWisniewski, M. Y. L., E. Yashchin, R. L. Franch, D. P. Conrady, D. N. Maynard, G. Fiorenza, and I. C. Noyan. "The physical design of on-chip interconnections." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 22, no. 3 (March 2003): 254–76. http://dx.doi.org/10.1109/tcad.2002.807881.
Повний текст джерелаCaldwell, A. E., H. J. Choi, A. B. Kahng, S. Mantik, M. Potkonjak, G. Qu, and J. L. Wong. "Effective Iterative Techniques for Fingerprinting Design IP." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 23, no. 2 (February 2004): 208–15. http://dx.doi.org/10.1109/tcad.2003.822126.
Повний текст джерелаRyu, K. K., and V. J. MooneyIII. "Automated Bus Generation for Multiprocessor SoC Design." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 23, no. 11 (November 2004): 1531–49. http://dx.doi.org/10.1109/tcad.2004.835119.
Повний текст джерелаAuge, I., F. Petrot, F. Donnet, and P. Gomez. "Platform-based design from parallel C specifications." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 24, no. 12 (December 2005): 1811–26. http://dx.doi.org/10.1109/tcad.2005.852431.
Повний текст джерелаAgarwal, K., M. Agarwal, D. Sylvester, and D. Blaauw. "Statistical interconnect metrics for physical-design optimization." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25, no. 7 (July 2006): 1273–88. http://dx.doi.org/10.1109/tcad.2005.855954.
Повний текст джерелаWang, G., S. Sivaswamy, C. Ababei, K. Bazargan, R. Kastner, and E. Bozorgzadeh. "Statistical Analysis and Design of HARP FPGAs." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25, no. 10 (October 2006): 2088–102. http://dx.doi.org/10.1109/tcad.2005.859485.
Повний текст джерелаDrinic, Milenko, Darko Kirovski, Seapahn Megerian, and Miodrag Potkonjak. "Latency-Guided On-Chip Bus-Network Design." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25, no. 12 (December 2006): 2663–73. http://dx.doi.org/10.1109/tcad.2006.882488.
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