Дисертації з теми "TCAD Design"
Оформте джерело за APA, MLA, Chicago, Harvard та іншими стилями
Ознайомтеся з топ-23 дисертацій для дослідження на тему "TCAD Design".
Біля кожної праці в переліку літератури доступна кнопка «Додати до бібліографії». Скористайтеся нею – і ми автоматично оформимо бібліографічне посилання на обрану працю в потрібному вам стилі цитування: APA, MLA, «Гарвард», «Чикаго», «Ванкувер» тощо.
Також ви можете завантажити повний текст наукової публікації у форматі «.pdf» та прочитати онлайн анотацію до роботи, якщо відповідні параметри наявні в метаданих.
Переглядайте дисертації для різних дисциплін та оформлюйте правильно вашу бібліографію.
Quiroga, Andrés. "Investigation and development of advanced Si/SiGe and Si/SiGeC Heterojunction Bipolar Transistors by means of Technology Modeling." Thesis, Paris 11, 2013. http://www.theses.fr/2013PA112273/document.
Повний текст джерелаThe present work investigates the technology development of state-of-the-art SiGe and SiGeC Heterojunction Bipolar Transistors (HBT) by means of technology computer aided design (TCAD). The objective of this work is to obtain an advanced HBT very close to the real device not only in its process fabrication steps, but also in its physical behavior, geometric architecture, and electrical results. This investigation may lead to achieve the best electrical performances for the devices studied, in particular a maximum operating frequency of 500 GHz. The results of this work should help to obtain more physical and realistic simulations, a better understanding of charge transport, and to facilitate the development and optimization of SiGe and SiGeC HBT devices.The TCAD simulation kits for SiGe/SiGeC HBTs developed during our work have been carried out in the framework of the STMicroelectronics bipolar technology evolution. In order to achieve accurate simulations we have used, developed, calibrated and implemented adequate process models, physical models and extraction methodologies. To our knowledge, this work is the first approach developed for SiGe/SiGeC HBTs which takes into account the impact of the strain, and of the germanium and carbon content in the base, for both: process and electrical simulations.In this work we will work with the successive evolutions of B3T, B4T and B5T technologies. For each new device fMAX improves of 100 GHz, thus the technology B3T matches to 300 GHz, B4T and B5T to 400 and 500 GHz, respectively.Chapter one introduces the SiGe SiGeC heterojunction bipolar technologies and their operating principles. This chapter deals also with the high frequency AC transistor operation, the extraction methods for fMAX and the carrier transport in extremely scaled HBTs.Chapter two analyzes the physical models adapted to SiGeC strained alloys used in this work and the electrical simulation of HBT devices. This is also an important work of synthesis leading to the selection, implementation and development of dedicated models for SiGeC HBT simulation.Chapter three describes the B3T TCAD simulation platform developed to obtain an advanced HBT very close to the real device. In this chapter the process fabrication of the B3T technology is described together with the methodology developed to simulate advanced HBT SiGeC devices by means of realistic TCAD simulations.Chapter four describes the HBT architectures developed during this work. We will propose low-cost structures with less demanding performance requirements and highly performing structures but with a higher cost of production. The B4T architecture which has been manufactured in clean-room is deeply studied in this chapter. The impact of the main fabrication steps is analyzed in order to find the keys process parameters to increase fMAX without degrading other important electrical characteristics. At the end of this chapter the results obtained is used to elaborate a TCAD simulation platform taking into account the best trade-off of the different key process parameters to obtain a SiGeC HBT working at 500 GHz of fMAX
Lemoigne, Pascal. "Simulation de la variabilité du transistor MOS." Thesis, Aix-Marseille 1, 2011. http://www.theses.fr/2011AIX10214/document.
Повний текст джерелаContinuous improvement in integrated circuits density of integration lead us to study process-induced variations in the framework of the 45 nm node, and to determine their principal contributions with the ultimate goal being to allow an accurate simulation of both transistor and circuit level variability. This work starts with a study of the state of the art of variability sources of the MOS transistor and associated simulation means. Then it focuses on the fluctuations of the channel doping, which is a difficult factor to measure statistically.After that we study the 45 nm node through a design of experiment which let us learn about natural variations of process factors but mostly about electrical performances sensitivity to those factors.Thanks to that we could identify major causes of process-induced variability at this stage of this node development. At last, with respect to those experimental results, we propose to enhance the taking in account of process variations in Monte-Carlo and corner simulations applied to compact models
PEZZAROSSA, MICHELE. "The deep Al-based JTE: development and industrialization of a novel termination design for high-power semiconductor devices." Doctoral thesis, Politecnico di Torino, 2022. http://hdl.handle.net/11583/2964780.
Повний текст джерелаQuiroga, Andres. "Investigation and development of advanced Si/SiGe and Si/SiGeC Heterojunction Bipolar Transistors by means of Technology Modeling." Phd thesis, Université Paris Sud - Paris XI, 2013. http://tel.archives-ouvertes.fr/tel-00938619.
Повний текст джерелаCleveland, William Peter. "Improving pilot understanding of TCAS through the traffic situation display." Thesis, Georgia Institute of Technology, 2013. http://hdl.handle.net/1853/47726.
Повний текст джерелаMusetha, Rendani D. "The design of CAN nodes for minimising cables on the SUNSAT's TCMD system." Thesis, Stellenbosch : Stellenbosch University, 2003. http://hdl.handle.net/10019.1/49793.
Повний текст джерелаENGLISH ABSTRACT: The aim of this thesis is to investigate a design of a microcontroller based embedded system that will be used to minimise cable harness on the SUNSAT micro-satellite. The system is called CAN node. The CAN node(s) implements CAN (Controller Area Network) serial bus architecture protocol. The protocol is implemented on the two nodes to transport data from the TCMD tot he 0 ther trays 0 f SUNSAT. CAN node( s) design proj ect focuses on the TCMD tray, because it is the central point for data communication in SUNSAT and it acts as the eyes and hands of the satellite's operator. As a result most of the communication cables are located at this tray. The two nodes are called TX-node and RX-nodes. The TX-node is used to collect data from the TCMD tray and transmits them serially to RX-node. The RX-nodes receives the TCMD data from TX-node and transmits these data to their respective nodes. In application RX-nodes need to be ten, but only one is used for testing purpose. The design had its shortcomings, of which they are discussed in this thesis. The recommendations of an ideal system are also given to elaborate how the system should behave in the real situation. Despite its shortcomings, the CAN node(s) project has successfully proven that cable harness on the TCMD tray of SUNSAT can be minimised by using CAN technology.
AFRIKAANSE OPSOMMING: Die doel van hierdie tesis is om die ontwerp van 'n mikro-beheerder gebaseerde stelsel wat die SUNSA T mikro-satelliet kabel harnas sal verklein, te ondersoek. Die stelsel word die CAN nodus genoem. Die CAN nodus implementeer die CAN (Controller Area Network) bus argitektuur protokol. Die protokol is op twee nodusse geïmplementeer om data vanaf die TCMD na ander laaie van SUNSAT te voer. Die CAN nodus ontwerp fokus op die TCMD laai, want dit is die sentrale punt vir data kommunikasie in SUNSA T en dit tree soos die oog en hande van die satelliet operateur op. As 'n gevolg, is die meeste van die kommunikasie kabels in hierdie laai. Die twee nodusse is genoem TXnodus en RX-nodus. TX-nodus word gebruik om die data van die TCMD af te kollekteer en dan versprei hulle tot hulle onderskeie nodusse. In die toepaslik moet daar tien RX-nodusse wees, maar net een is gebruik terwille van die toets. Die ontwerp het sy eie tekortkomings, wat in hierdie tesis bespreek word. Die rekommendasie van 'n ideale stelsel is ook gemaak om te bewys hoe die stelsel dit in 'n ware situasie moet gedra. Ongeag die tekortkomings daarvan, het die CAN-nodus projek suksesvol bewys dat die kabel harnas in die TCMD laai van SUNSAT kan verminder word deur die gebruik van die CAN tegnologie.
Rosenbaum, Tommy. "Performance prediction of a future silicon-germanium heterojunction bipolar transistor technology using a heterogeneous set of simulation tools and approaches." Thesis, Bordeaux, 2017. http://www.theses.fr/2017BORD0550/document.
Повний текст джерелаBipolar complementary metal-oxide-semiconductor (BiCMOS) processescan be considered as the most general solution for RF products, as theycombine the mature manufacturing tools of CMOS with the speed and drivecapabilities of silicon-germanium (SiGe) heterojunction bipolar transistors(HBTs). HBTs in turn are major contenders for partially filling the terahertzgap, which describes the range in which the frequencies generated bytransistors and lasers do not overlap (approximately 0.3THz to 30 THz). Toevaluate the capabilities of such future devices, a reliable prediction methodologyis desirable. Using a heterogeneous set of simulation tools and approachesallows to achieve this goal successively and is beneficial for troubleshooting.Various scientific fields are combined, such as technology computer-aided design(TCAD), compact modeling and parameter extraction.To create a foundation for the simulation environment and to ensure reproducibility,the used material models of the hydrodynamic and drift-diffusionapproaches are introduced in the beginning of this thesis. The physical modelsare mainly based on literature data of Monte Carlo (MC) or deterministicsimulations of the Boltzmann transport equation (BTE). However, the TCADdeck must be calibrated on measurement data too for a reliable performanceprediction of HBTs. The corresponding calibration approach is based onmeasurements of an advanced SiGe HBT technology for which a technology specific parameter set of the HICUM/L2 compact model is extracted for thehigh-speed, medium-voltage and high-voltage transistor versions. With thehelp of the results, one-dimensional transistor characteristics are generatedthat serve as reference for the doping profile and model calibration. By performingelaborate comparisons between measurement-based reference dataand simulations, the thesis advances the state-of-the-art of TCAD-based predictionsand proofs the feasibility of the approach.Finally, the performance of a future technology in 28nm is predicted byapplying the heterogeneous methodology. On the basis of the TCAD results,bottlenecks of the technology are identified
Bipolare komplementäre Metall-Oxid-Halbleiter (BiCMOS) Prozesse bietenhervorragende Rahmenbedingungen um Hochfrequenzanwendungen zurealisieren, da sie die fortschrittliche Fertigungstechnik von CMOS mit derGeschwindigkeit und Treiberleistung von Silizium-Germanium (SiGe) Heterostruktur-Bipolartransistoren (HBTs) verknüpfen. Zudem sind HBTs bedeutendeWettbewerber für die teilweise Überbrückung der Terahertz-Lücke, derFrequenzbereich zwischen Transistoren (< 0.3 THz) und Lasern (> 30 THz).Um die Leistungsfähigkeit solcher zukünftigen Bauelemente zu bewerten, isteine zuverlässige Methodologie zur Vorhersage notwendig. Die Verwendungeiner heterogenen Zusammenstellung von Simulationstools und Lösungsansätzenerlaubt es dieses Ziel schrittweise zu erreichen und erleichtert die Fehler-_ndung. Verschiedene wissenschaftliche Bereiche werden kombiniert, wie zumBeispiel der rechnergestützte Entwurf für Technologie (TCAD), die Kompaktmodellierungund Parameterextraktion.Die verwendeten Modelle des hydrodynamischen Simulationsansatzes werdenzu Beginn der Arbeit vorgestellt, um die Simulationseinstellung zu erläuternund somit die Nachvollziehbarkeit für den Leser zu verbessern. Die physikalischenModelle basieren hauptsächlich auf Literaturdaten von Monte Carlo(MC) oder deterministischen Simulationen der Boltzmann-Transportgleichung(BTE). Für eine zuverlässige Vorhersage der Eigenschaften von HBTs muss dieTCAD Kon_guration jedoch zusätzlich auf der Grundlage von Messdaten kalibriertwerden. Der zugehörige Ansatz zur Kalibrierung beruht auf Messungeneiner fortschrittlichen SiGe HBT Technologie, für welche ein technologiespezifischer HICUM/L2 Parametersatz für die high-speed, medium-voltage undhigh-voltage Transistoren extrahiert wird. Mit diesen Ergebnissen werden eindimensionaleTransistorcharakteristiken generiert, die als Referenzdaten fürdie Kalibrierung von Dotierungspro_len und physikalischer Modelle genutztwerden. Der ausführliche Vergleich dieser Referenz- und Messdaten mit Simulationengeht über den Stand der Technik TCAD-basierender Vorhersagenhinaus und weist die Machbarkeit des heterogenen Ansatzes nach.Schlieÿlich wird die Leistungsfähigkeit einer zukünftigen Technologie in28nm unter Anwendung der heterogenen Methodik vorhergesagt. Anhand derTCAD Ergebnisse wird auf Engpässe der Technologie hingewiesen
Gnawali, Krishna Prasad. "EMERGING MEMORY-BASED DESIGNS AND RESILIENCY TO RADIATION EFFECTS IN ICS." OpenSIUC, 2020. https://opensiuc.lib.siu.edu/dissertations/1863.
Повний текст джерелаGuyonneau, David. "Contribution à la détermination de surfaces conjuguées pour la transmission de puissance." Thesis, Aix-Marseille, 2013. http://www.theses.fr/2013AIXM4134.
Повний текст джерелаThe work described in the present manuscript is part of exploratory researches dealing with gears meshing surfaces optimization. After a short study of gears used in an aeronautical environment, the development of an innovative tool for tooth profile design is defined. Then, the specific behavior of a gear mesh within a helicopter main gearbox (MGB) is evaluated.A VBA software has been coded under MS Excel to generate conjugated and optimized gear tooth profiles. It advantageously defines and uses several physical parameters with their analytical formulation. The software provides at the user optimized tooth profiles according to a couple of criteria. The two “objective” functions evaluated are the efficiency and the Hertz equivalent stress within the contact using the Von Mises criterion.The work has been focused on three aspects:- The design of conjugated tooth profiles by contact sharing,- The definition of the relevant physical parameters,- The optimization of tooth profiles using Monte Carlo SimulationEventually, a generic method to design gear profiles, taking into account any physical parameters related to a gear mesh, could be expected as a future of this thesis work
Delomier, Florent. "Jeux pédagogiques collaboratifs situés : conception et mise en oeuvre dirigées par les modèles." Phd thesis, Ecole Centrale de Lyon, 2013. http://tel.archives-ouvertes.fr/tel-00995808.
Повний текст джерелаCheng, Kun-Ting, and 鄭堃廷. "GaN HEMT T-gate Optimal Design and TCAD simulaiton." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/38djj5.
Повний текст джерела國立交通大學
國際半導體產業學院
108
In this paper, we successfully build the component model with TCAD based on the actual AlGaN/GaN high electron mobility transistor, and after the simulation results and measurement results have achieved high accuracy. , to optimize the high frequency characteristics. First, we divide the T-type gate into four parts, including the gate length (Lg) of the lower half, the gate height (Hgate), and the top half gate height (Tgate) and the gate tip width. (Wgate), etc., respectively studied the effects of various dimensions on the RF performance of components, and extracted the parameters of high-frequency related components for analysis. Finally, combining the simulation results of the above four parameters, we provide an optimized T-gate design. Compared with the original design, the high-frequency characteristics of the components such as cutoff frequency and maximum oscillation frequency are significantly improved. To sum up, the research proposes a set of design methods for the gate of GaN devices, which can quickly and effectively improve the performance of high-frequency components. In addition, the TCAD component model provided in this paper is not limited to a single component. It is also applicable to the study of high-frequency components with similar materials and structures. It can be widely applied to all similar high-frequency components and is also the value of this research.
Teng, Chien-Hong, and 鄧建鴻. "TCAD Design of InAs Gate-All-Around Nanowire Tunnel FET Structures." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/g73uyt.
Повний текст джерела國立臺灣大學
電子工程學研究所
105
The electrical characteristics of InAs-Si heterojunction GAA NW TFET are simulated using Sentaurus TCAD produced by Synopsys. Results show that InAs-Si heterojunction can enlarge the on-state current compared with Si homo-junction and GAA structure can improve the subthreshold slope compared with single gate structure. The reasons are that the tunnel barrier width of InAs-Si heterojunction is smaller than Si homo-junction and the GAA structure has better gate control than single gate structure. Besides, the diameter of nanowire scarcely affects the performance of device due to the tunneling mainly occurring at nanowire surface. To further improve the subthreshold slope, we introduce Si pocket structure. This structure can further decrease the subthreshold slope by Si to Si tunneling mechanism. On the other hand, to further increase the on-state current, we introduce core shell structure. This structure can further increase on-state current because it enlarges the tunnel area. However, the on-state current does not increase proportional to the core length due to the tunnel barrier width in the direction across channel increases as the core length increasing.
Maccaronio, Vincenzo, Pietro Pantano, Giuseppe Cocorullo, and Felice Crupi. "Design of interdigitated back-contact solar cells by means of TCAD numerical simulations." Thesis, 2017. http://hdl.handle.net/10955/1309.
Повний текст джерелаLa promessa dell’energia solare come forma di energia principale è sempre più concreta, ma il nodo cruciale rimane il costo per Watt, che deve essere sempre di più avvicinato o finanche ulteriormente ridotto rispetto a quello delle reti di distribuzione energetiche esistenti. Un lavoro di ottimizzazione in termini di design e parametri di fabbricazione è quindi fondamentale per raggiungere questo obiettivo. Il silicio cristallino è il materiale maggiormente diffuso nell’industria fotovoltaica, per via di diversi fattori, tra cui l’ottimo rapporto costo/prestazioni e la vasta presenza di macchinari per la sua lavorazione, dovute al suo impiego pluridecennale nell’industria microelettronica. Fra le diverse tipologie di celle esistenti è stata scelta un’architettura che presenta entrambi i contatti metallici sul retro, chiamata per questo interdigitated back-contact (iBC). Questo particolare design offre numerosi vantaggi in termini di efficienza massima, costo di produzione ed estetica del pannello, in relazione alle celle convenzionali. Difatti, al momento attuale le maggiori efficienze in celle monogiunzione, sia a livello di laboratorio che di moduli commerciali, sono state ottenute utilizzando questa struttura, sulla quale un’approfondita attività di ricerca può quindi dimostrarsi di notevole interesse. Per il processo di analisi è stato scelto un approccio numerico, tramite l’uso del simulatore di dispositivi TCAD Sentaurus di Synopsys. L’utilizzo di simulazioni offre numerosi punti a favore rispetto all’ottimizzazione per mezzo di step ripetuti di fabbricazione. In primis, un vantaggio in termini di costi, non necessitando di macchinari, materiali e camere pulite. Inoltre un’analisi numerica rende possibile individuare ed evidenziare punti o cause specifiche di perdite o problemi di progettazione. La problematica maggiore di questo approccio risiede nella necessità di garantire l’affidabilità delle simulazioni e ciò è stato ottenuto mediante l’applicazione dello stato dell’arte di tutti i modelli fisici specifici coinvolti nel funzionamento di questo tipo di celle. La tematica di ricerca affrontata è stata quindi la progettazione di celle solari al silicio con contatti interdigitati sul retro tramite l’uso di simulazioni numeriche. Il lavoro di ottimizzazione è stato realizzato investigando uno spazio di parametri di fabbricazione molto vasto e ottenendo informazioni sui trend delle prestazioni al variare degli stessi. Nel primo capitolo è stata illustrata la fisica e i principi di funzionamento di una cella solare, iniziando dall’assorbimento della luce, passando alla sua conversione in cariche elettriche, per finire con la loro raccolta per generare potenza. I meccanismi di ricombinazione e le altre cause di perdite sono stati presentati ed esaminati. Nel secondo capitolo è stata dettagliata l’architettura di una cella solare, evidenziando le diverse regioni e presentando la struttura back-contact. Il terzo capitolo è stato dedicato alla spiegazione delle strategie di simulazione applicate in questo lavoro, con la definizione dei modelli fisici applicati e calibrati per assicurare l’accuratezza richiesta. Nei capitoli quattro e cinque sono stati presentati i risultati delle simulazioni effettuate, realizzate variando le caratteristiche geometriche delle diverse regioni della cella e i profili di drogaggio. Sono stati ottenuti i trend di comportamento relativi ai singoli parametri che, nel caso relativo ai drogaggi, permettono di affermare che per ogni regione l’andamento dell’efficienza ha una forma a campana, che presenta un ottimo di drogaggio relativo in un punto intermedio. Questo comportamento è dovuto, per bassi valori di drogaggio, all’effetto della ricombinazione sul contatto per BSF ed emettitore e della ricombinazione superficiale per l’FSF. Per alti valori di drogaggio, la degradazione dell’efficienza dipende dall’effetto della ricombinazione Auger per BSF ed emettitore e da quella superficiale per l’FSF. Per quanto riguarda i parametri geometrici, le analisi svolte evidenziano che il gap tra emettitore e BSF deve essere quanto più piccolo possibile, dato che all’aumentare della sua dimensione aumentano le perdite per effetto resistivo e di ricombinazione. È stato determinato che il valore ottimale di emitter coverage non è assoluto, ma dipende dalla resistività del bulk e dai drogaggi delle altre regioni, os cillando tra l’80% e il 90%. Per quanto riguarda il pitch ottimale, cioè la distanza tra i contatti, è stato determinato che maggiori efficenze corrispondono a valori minori, principalmente perché all’aumentare della distanza aumentano le resistenze parassite. Infine si è evidenziato che l’aggiunta di un secondo contatto sull’emettitore, equispaziato dal centro della regione, migliora l’efficienza totale poiché riduce le perdite resistive, soprattutto nel caso di celle con emettitori lunghi.
Università della Calabria
Ozbek, Ayse Merve. "Schottky barrier GaN FET model creation and verification using TCAD for technology evaluation and design." 2008. http://www.lib.ncsu.edu/theses/available/etd-03132008-111248/unrestricted/etd.pdf.
Повний текст джерелаGuevara, Granizo Marco Vinicio, and Felice Crupi. "Design of back contact solar cells featuring metallization schemes with multiple emitter contact lines based on TCAD numerical simulations." Thesis, 2017. http://hdl.handle.net/10955/1874.
Повний текст джерелаThe most hard-working goal within PV community is to design and manufacture devices featuring high-efficiency at low-cost with the better reliability as possible. The key to achieving this target is to optimize and improve the current fabrication processes as well as the layouts of the devices. TCAD modeling of PV devices turns out to be a powerful tool that lowers laboratory manufacturing costs and accelerates optimization processes by bringing guidelines of how to do it. The modeling in TCAD examines the designs before their implementation, accurately predicting its real behavior. When simulations are correctly calibrated, by changing simulations’ parameters, allow finding ways to improve designs’ parameters or just understand better the internal functioning of these devices. In this regard, this Ph.D. thesis fairly treats the electro-optical numerical simulations of interdigitated back-contact (IBC) c-Si solar cells, which nowadays is the architecture to which industry is trying to pull forward because of its numerous advantages. Among the benefits of this design are their improved efficiency due to the absence of front optical shading or the relative simplicity regarding their massive production. The aim of this thesis, it is focusing on providing guidelines of the optimal design parameters of IBC solar cells, based on the state-of-the-art of advanced numerical simulations. Two main topics are treated, (i) the development of a simplified method to compute the optical profiles ten times faster than the traditional one and (ii) an extensive study on the impact of adding multiple striped metal contacts throughout the emitter region improving the efficiency by reducing the inner series resistance. It was performed a large number of ad-hoc calibrated simulations that sweep wide ranges of modeling parameters (i.e., changing geometric sizes, doping profiles, carriers’ lifetimes, and recombination rates) to investigate their influence over the device operation, allowing to identify the most critical ones. This insight leads a better understanding of this kind of solar cells and helps to appraise ways to refine structures and enhance layouts of real devices for either laboratory or industry.
Università della Calabria
Soni, Ankit. "Physics Based Design & Development of Gallium Nitride High Electron Mobility Transistors (HEMTs) & Schottky Barrier Diodes for Power and RF Applications." Thesis, 2021. https://etd.iisc.ac.in/handle/2005/5177.
Повний текст джерела(11184600), Md monzurul Alam. "The Design, Fabrication, and Characterization of Waffle-substrate-based n-channel IGBTs in 4H-SiC." Thesis, 2021.
Знайти повний текст джерелаChen, Jin-Hao, and 陳金昊. "Vertical Partial Control TCAM Design and Implementation." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/09431620834989781409.
Повний текст джерела國立中興大學
資訊科學與工程學系
102
Ternary Content Addressable memory (TCAM) is widely used in the routing table of the network router. Besides the dynamic power dissipated in?active mode, however, TCAM also consumes?large amount of leakage power in standby mode. In this paper, we propose the vertical partial control (VPC) technique to reduce the?leakage power consumption of TCAM.?Based on the vertiacally continuous "don''t care" feature shown in the routing table, the VPC technique uses segmentation method to?reduce the leakage power dissipated in the TCAM celles with "don''t care" mask. For a 128x32-bit TCAM array, using TSMC 0.18um technology process the simulation results show that the VPC?technique can reduce the?leakage power consumption by 14.24% compared to the conventional TCAM design.
Fan, Sheng-Hsin, and 范聖欣. "Low Power TCAM Design using Segmented-Precharge Technique." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/60024472384549794681.
Повний текст джерела國立臺灣大學
資訊工程學研究所
99
Due to the characteristic of high-speed search in Ternary Content Addressable Memory (TCAM), it plays an important role in many high-speed devices, however it consumes too much power. The power consumption in conventional NOR-type TCAM is mainly from the dynamic power consumption, in which precharging all the match lines and discharging mismatched match lines during a search operation. Since the number of mismatched match lines is much more than the matched ones, most of the match lines are discharged leading to high power consumption. In this thesis, based on the characteristic of IP prefix stored in TCAM, the mask bit “0” has a continuity property when “0” appears. Therefore, we proposed a method called segmented-precharge technique in TCAM to reduce dynamic power consumption. The experimental results show that the proposed TCAM design with 4 segments is the most appropriate considering power and delay, which has 23.68% power saving and 0.74ns delay in average-case compared to the conventional TCAM.
Lu, Meng-Rong, and 呂孟蓉. "Low Power FinFET TCAM Design Using Dynamic Voltage Control." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/28137862480359261106.
Повний текст джерела國立中興大學
資訊科學與工程學系
102
With shrinking feature size, FinFET device is an attractive alternative to the conventional Bulk CMOS because of the superior ability in suppressing leakage. In this paper we propose a low-power FinFET TCAM design, in which the dynamic voltage control (DVC) technique can effectivley reduce the TCAM leakage power consumption by combining the independent-gate (IG) FinFET technique and the continuous "don''t care" feature of the mask data. Based on PTM 32 nm FinFET technology, the DVC technique can achieve 39.1% leakage power reduction compared with the traditional TCAM design.
Lai, Shu-Lin, and 賴淑琳. "Energy-Efficient TCAM Design for IP Lookup Tables in 40nm LP CMOS Process." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/06913190923307885818.
Повний текст джерела國立交通大學
電子研究所
101
Ternary content addressable memory (TCAM) is extensively adopted in routing tables of network systems and occupied great amounts of energy consumption. In this thesis, energy-efficient TCAM macros have been designed and realized in 40nm LP CMOS process with the sizes of 256x40 and 256x144, respectively. Based on the small drain current in 40nm LP CMOS process, a 16T AND-type TCAM cell with p-type comparison circuits is utilized to increase the Ion/Ioff ratio of the dynamic circuitry. Additionally, the butterfly match-line scheme with AND gates is designed to reduce the wire loading on the evaluation nodes and to ensure that the capacitance of the evaluation nodes are the same in all segments. For further reducing the energy consumption in nano-scale technologies, don’t-care-based ripple search-line and ripple bit-lines are realized to decrease both the switching activities and wire capacitance of search-lines and bit-lines. Moreover, the column-based data-aware power control is also employed to realize the leakage power reduction, write-ability and static noise margin (SNM) improvements by the power gating devices. Consequently, the timing of the power switching is tolerant to PVT variation and Vt scatter by the replica circuitry. The energy-efficient 256x40 and 256x144 TCAM macros are implemented using UMC 40nm LP CMOS technology, and the experimental results demonstrate a leakage power reduction of 28.9%, a search-line power reduction of 31.74% and an energy metric of the TCAM macro of 0.461 fJ/bit/search.
Liu, Siao-Siang, and 劉曉祥. "Design of Matchline Sense Amplifiers for FinFET-Based Ternary Content-Addressable Memory(TCAM)." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/99784352426715471019.
Повний текст джерела國立彰化師範大學
電子工程學系
104
Content-addressable memory (CAM) compares input search data in parallel against a table of stored data, and returns the address of the matching data. CAMs can be used in a wide variety of applications requiring high-speed parallel search. These applications include pattern recognition, data compression, and network address translation. The parallel search operation of CAM consumes a significant amount of energy due to the charging and discharging of the search lines and match lines with large capacitance. As the feature size continues to shrink and the corresponding transistor density increases, the planar MOSFET suffer from the increased subthershold and gate leakage currents. FinFET is considered as one of the best substitutes for planar MOSFET technology in the sub-20 nm regime. This thesis proposed two new sensing techniques for low power Ternary Content-Addressable Memory (TCAM). Matchline-Accelerating Sense Amplifiers (MLA-SA) using pulse current to reduce the power consumption of Matchlien in TCAM and employs the feedback network to boost the search speed of TCAM. We proposed a second Matchline sensing technique call “Matchline-Accelerating Low-Power sense amplifiers (MLA-LP-SA) “. MLA-LP-SA using the pulse current to charge the Matchlines and then detects the voltage development on Matchlines to determine whether the Matchline is matched. In contrast to conventional MLSAs, which adjust the charging current to the match lines based on matching result, MLA-LP-SA will not provide additional current to the match lines regardless of the matching result. We have employed Hspice to evaluate various Matchline sensing circuits using the Berkeley Short-channel IGFET Model (BSIM) common multi-gate (CMG) FinFETs with supply voltage of 0.6V and temperature of 25℃. The simulation results show that the proposed MLA-SA can reduce the energy consumption by 39%-65% and 25%-44% compared to the conventional Precharge MLSA and Current-Race MLSA. The proposed MLA-LP-SA can reduce the energy consumption by 66%-73% and 54%-63%, compared to the conventional Precharge MLSA and Current-Race MLSA. MLA-SA and MLA-LP-SA, respectively, can achieve a search time of 150.2 ps and 89.6 ps, and Energy-delay product of 0.775×10-27JS and 0.372×10-27JS, for conventional Precharge MLSA and Current-Race MLSA decreased by 64.38%, 51.65% and 82.9%, 76.79%. Keywords: Content-addressable memory, FinFET devices, Matchline Sense Amplifiers
Chan, Yun-Sheng, and 詹耘昇. "0.4V Configurable Near-Threshold TCAM Design in 28nm High-k Metal-Gate CMOS Process." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/xt3595.
Повний текст джерела國立交通大學
電子工程學系 電子研究所
104
Even though ternary content addressable (TCAM) is the power hungry circuitry, it still be extensively adopted in routing table of network systems by its high speed and unique. With the develop of the portable devices and the rise of Internet of Things (IoT), the issue of energy efficiency and low supply voltage become a major trend in SoC. If we want to introduce TCAM into IoT. Its power hungry problem should be solved first. However, conventional 6T SRAM is hard to work in low supply voltage duo to read/write ability degradation which caused by severely process variation in advance process. We realize our design in umc 28nm high-k metal-gate (HKMG) CMOS technology. We introduce the 6T Mini-array into TCAM and let it can even operate at 0.4V. Additionally, we use hierarchical PRE, power gating and ripple search-line in our design which let total energy consumption less.