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Дисертації з теми "Systèmes adaptatifs (informatique) – Réseaux logiques programmables par l'utilisateur"
Perez, Castañeda Oscar Leopoldo. "Modélisation des effets de la reconfiguration dynamique sur la flexibilité d'une architecture de traitement temps réel." Nancy 1, 2007. http://www.theses.fr/2007NAN10139.
Повний текст джерелаThe principal contribution of the wired logic compared to the microprocessor is the degree of parallelism which is in higher several orders of magnitude. However, the property of configurability of these circuits involves an additionnal cost in term of silicon surface, delay and power consumption compared to circuits ASICs. The dynamic reconfiguration of the FPGA is often presented in the literature like a means of increasing their flexibility, to approach that of the microprocessors, while preserving a level of performance that if not is close to the ASIC is higher than of the microprocessors. If the performance is in general, for a given application, more easy to quantify, the situation is quite different for flexibility. In the litterature this metric has never been defined and quantified. Moreover we did not find any definition of the flexibility of an architecture for processing of data. The principal objective of this work is by one hand, to define and quantify the flexibility and by the other hand, to model the influence of the dynamic reconfiguration on flexibility. We put at the disposition the designer a metric as well as the bases of methodology allowing it to choose or not this solution according to its constraints and objectives
Garcia, Samuel. "Architecture reconfigurable dynamiquement a grain fin pour le support d'un système d'exploitation temps réel." Paris 6, 2012. http://www.theses.fr/2012PA066495.
Повний текст джерелаMost of anticipated future applications share four major characteristics. They might all require an increased computing capacity, they will implies to take real time into account, they represent a big step in terms of complexity compared with todays typical applications, and will have to deal with the dynamic nature of the real physical world. Fine grained dynamically reconfigurable architecture (FGDRA) can be seen as next evolution of today's FPGA, aiming at dealing with very dynamic and complex real time applications while providing comparable potential computing power due to the possibility to fine tune execution architecture at a fine grain level. To make this kind of devices usable for real application designer complexity has to be abstracted by an operating system layer and adequate tool set. This combination would form an adequate solution to support future applications. This thesis exposes an innovative FGDRA architecture called OLLAF. This architecture answer both technical issues on reconfigurable computing and practical problematics of application designers. The whole architecture is designed to work in symbiosis with an operating system. Studies presented here will more particularly focus on hardware task management mechanisms in a preemptive system. We will first present our work toward trying to implement such mechanisms using existing FPGA and show that those existing architectures have to evolve to efficiently support an operating system in a highly dynamic real time situation. The OLLAF architecture will then be explained and the hardware task management mechanism will be highlighted. We then present two studies that prove this approach to constitute a huge gain compared with existing platforms in terms of resulting operating system overhead even for static application cases where dynamical reconfiguration is used only for computing resource sharing. For highly dynamical real time cases we show that not only it could lower the overhead, but it will also support cases that existing devices just cannot support
Vidal, Jorgiano. "Dynamic and partial reconfigurable embedded systems design with UML." Lorient, 2010. http://www.theses.fr/2010LORIS203.
Повний текст джерелаAdvances in reconfigurable technologies allow entire multiprocessor systems to be implemented in a single FPGA (Multiprocessor System on Programmable Chip, MP- SoPC). In order to speed up the design time of such heterogeneous systems, new modelling techniques must be developed. Furthermore, dynamic execution is a key point for modern systems, i. E. Systems that can partially change their behavior at run time in order to adjust their execution to the environment. UML (Unified Modeling Language) has been used for software modeling since its first version. Recently, with new modeling concepts added to later versions (UML 2), it has become more and more suitable for hardware modeling. This thesis is a contribution to the MOPCOM project, where we propose a set of modeling techniques in order to build complex embedded systems by using UML. The modeling techniques proposed here consider the system to be built in one complete model. Moreover, we propose a set of transformation that allows the system to be automatically generated. Our approach allows the modelling of dynamic applications onto reconfigurable platforms. Design time reduction up to 30% has been measured while using our methodology
Liu, Ting. "Optimisation par synthèse architecturale des méthodes de partitionnement temporel pour les circuits reconfigurables." Thesis, Nancy 1, 2008. http://www.theses.fr/2008NAN10013/document.
Повний текст джерелаAThe research work presented in the context of methodologies is to assist the implementation of data flow graph algorithms on dynamically reconfigurable RSoC (Reconfigurable System on Chip)-based FPGA architectures.The main strategy consists in implementing a design approach based on simultaneously both the dynamic reconfiguration (DR) and synthesis architecture (SA) in order to achieve a best Adequacy Algorithm Architecture (A3). The methodology consists in identifying and extracting the parts of an application which is described in form of DFG in order to implement either by successively partial reconfiguration (TP), or by the AS or by combining the two approaches.To develop our solution with a view of optimizing and suitable compromise between the two approaches RD and SA, we propose a parameter in order to evaluate the degree of the inter-partition implementation based on functional units shared. In order to validate the proposed methodological strategy, we present the results of the implementation of our approach on two real-time applications. A comparative analysis with the respecting of the implementation results illustrates the interest and the optimisation ability of our method, which is also for dynamic reconfiguration implementation of the complex applications on RSoC
Zhang, Xun. "Contribution aux architectures adaptatives : etude de l'efficacité énergétique dans le cas des applications à parallélisme de données." Thesis, Nancy 1, 2009. http://www.theses.fr/2009NAN10106/document.
Повний текст джерелаMy PhD project focuses on Dynamic Adaptive Runtime parallelism and frequency scaling techniques in coarse grain reconfigurable hardware architectures. This new architectural approach offers a set of new features to increase the flexibility and scalability for applications in an evolving environment with reasonable energy cost. In this architecture, the parallelism granularity and running frequency can be reconfigured by using partial and dynamic reconfiguration. The adaptive method and architecture have been already developed and tested on FPGA platforms. The measurements and results analysis based on DWT show that the energy efficiency is adjustable dynamically by using our approach. The main contribution to the research project involves an auto-adaptive method development; this means using partial and dynamic reconfiguration can reconfigure the parallelism granularity and running frequency of application. The adaptive method by adjusting the parallelism granularity and running frequency is tested with the same application. We are presenting results coming from implementations of Image processing key application and analyses the behavior of this architecture on these applications
Fournier, Émilien. "Accélération matérielle de la vérification de sûreté et vivacité sur des architectures reconfigurables." Electronic Thesis or Diss., Brest, École nationale supérieure de techniques avancées Bretagne, 2022. http://www.theses.fr/2022ENTA0006.
Повний текст джерелаModel-Checking is an automated technique used in industry for verification, a major issue in the design of reliable systems, where performance and scalability are critical. Swarm verification improves scalability through a partial approach based on concurrent execution of randomized analyses. Reconfigurable architectures promise significant performance gains. However, existing work suffers from a monolithic design that hinders the exploration of reconfigurable architecture opportunities. Moreover, these studies are limited to safety verification. To adapt the verification strategy to the problem, this thesis first proposes a hardware verification framework, allowing to gain, through a modular architecture, a semantic and algorithmic genericity, illustrated by the integration of 3 specification languages and 6 algorithms. This framework allows efficiency studies of swarm algorithms to obtain a scalable safety verification core. The results, on a high-end FPGA, show gains of an order of magnitude compared to the state-of-the-art. Finally, we propose the first hardware accelerator for safety and liveness verification. The results show an average speed-up of 4875x compared to software
Jovanovic, Slavisa. "Architecture reconfigurable de système embarqué auto-organisé." Thesis, Nancy 1, 2009. http://www.theses.fr/2009NAN10099/document.
Повний текст джерелаThe growing complexity of computing systems, mostly due to the rapid progress in Information Technology (IT) in the last decade, imposes on system designers to orient their traditional design concepts towards the new ones based on self-organizing and self-adaptive architectural solutions. On the one hand, these new architectural solutions should provide a system with a suf?cient computing power, and on the other hand, a great ?exibility and adaptivity in order to cope with all non-deterministic changes and events that may occur in the environnement in which it evolves. Within this framework, a recon?gurable MPSoC self-organizing architecture on the FPGA recon?gurable technology is studied and developped during this PhD
Hentati, Manel. "Reconfiguration dynamique partielle de décodeurs vidéo sur plateformes FPGA par une approche méthodologique RVC (Reconfigurable Video Coding)." Rennes, INSA, 2012. http://www.theses.fr/2012ISAR0027.
Повний текст джерелаThe main purpose of this PhD is to contribute to the design and the implementation of a reconfigurable decoder using MPEGRVC standard. The standard MPEG-RVC is developed by MPEG. Lt aims at providing a unified high-level specification of current and future MPEG video coding technologies by using dataflow model named RVC-CAL. This standard offers the means to overcome the lack of interpretability between many video codecs deployed in the market. Ln this work, we propose a rapid prototyping methodology to provide an efficient and optimized implementation of RVC decoders in target hardware. Our design flow is based on using the dynamic partial reconfiguration (DPR) to validate reconfiguration approaches allowed by the MPEG-RVC. By using DPR technique, hardware module can be replaced by another one which has the same function or the same algorithm but a different architecture. This concept allows to the designer to configure various decoders according to the data inputs or her requirements (latency, speed, power consumption,. . ). The use of the MPEG-RVC and the DPR improves the development process and the decoder performance. But, DPR poses several problems such as the placement of tasks and the fragmentation of the FPGA area. These problems have an influence on the application performance. Therefore, we need to define methods for placement of hardware tasks on the FPGA. Ln this work, we propose an off-line placement approach which is based on using linear programming strategy to find the optimal placement of hardware tasks and to minimize the resource utilization. Application of different data combinations and a comparison with sate-of-the art method show the high performance of the proposed approach
Feki, Oussama. "Contribution à l'implantation optimisée de l'estimateur de mouvement de la norme H.264 sur plates-formes multi composants par extension de la méthode AAA." Thesis, Paris Est, 2015. http://www.theses.fr/2015PEST1009/document.
Повний текст джерелаMixed architectures containing programmable devices and reconfigurable ones can provide calculation performance necessary to meet constraints of real-time applications. But the implementation and optimization of these applications on this kind of architectures is a complex task that takes a lot of time. In this context, we propose a rapid prototyping tool for this type of architectures. This tool is based on our extension of the Adequacy Algorithm Architecture methodology (AAA). It allows to automatically perform optimized partitioning and scheduling of the application operations on the target architecture components and generation of correspondent codes. We used this tool for the implementation of the motion estimator of the H.264/AVC on an architecture composed of a Nios II processor and Altera Stratix III FPGA. So we were able to verify the correct running of our tool and validate our automatic generator of mixed code
Bruguier, Florent. "Méthodes de caractérisation et de surveillance des variations technologiques et environnementales pour systèmes reconfigurables adaptatifs." Phd thesis, Université Montpellier II - Sciences et Techniques du Languedoc, 2012. http://tel.archives-ouvertes.fr/tel-00965377.
Повний текст джерелаКниги з теми "Systèmes adaptatifs (informatique) – Réseaux logiques programmables par l'utilisateur"
Embedded SoPC system with Altera NIOSII processor and Verilog examples. Hoboken, N.J: Wiley, 2012.
Знайти повний текст джерелаGaillardon, Pierre-Emmanuel. Reconfigurable Logic: Architecture, Tools, and Applications. Taylor & Francis Group, 2018.
Знайти повний текст джерелаReconfigurable Logic: Architecture, Tools, and Applications. Taylor & Francis Group, 2015.
Знайти повний текст джерелаGaillardon, Pierre-Emmanuel. Reconfigurable Logic: Architecture, Tools, and Applications. Taylor & Francis Group, 2018.
Знайти повний текст джерелаGaillardon, Pierre-Emmanuel. Reconfigurable Logic: Architecture, Tools, and Applications. Taylor & Francis Group, 2018.
Знайти повний текст джерелаGaillardon, Pierre-Emmanuel. Reconfigurable Logic: Architecture, Tools, and Applications. Taylor & Francis Group, 2018.
Знайти повний текст джерелаEnergy Efficient Hardware - Software Co-Synthesis Using Reconfigurable Hardware (Chapman & Hall/Crc Computer & Information Science Series). Chapman & Hall/CRC, 2009.
Знайти повний текст джерелаIntroduction to Reconfigurable Computing: Architectures, Algorithms, and Applications. Springer, 2007.
Знайти повний текст джерелаBobda, Christophe. Introduction to Reconfigurable Computing: Architectures, Algorithms, and Applications. Springer, 2010.
Знайти повний текст джерелаBobda, Christophe. Introduction to Reconfigurable Computing: Architectures, Algorithms, and Applications. Springer London, Limited, 2007.
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