Дисертації з теми "System-on-chips"
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Ludewig, Ralf. "Integrierte Architektur für das Testen und Debuggen von System-on-Chips /." Aachen : Shaker, 2006. http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&doc_number=014632870&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA.
Повний текст джерелаAn, Xin. "High level design and control of adaptive multiprocessor system-on-chips." Thesis, Grenoble, 2013. http://www.theses.fr/2013GRENM023/document.
Повний текст джерелаThe design of modern embedded systems is getting more and more complex, as more func- tionality is integrated into these systems. At the same time, in order to meet the compu- tational requirements while keeping a low level power consumption, MPSoCs have emerged as the main solutions for such embedded systems. Furthermore, embedded systems are be- coming more and more adaptive, as the adaptivity can bring a number of benefits, such as software flexibility and energy efficiency. This thesis targets the safe design of such adaptive MPSoCs. First, each system configuration must be analyzed concerning its functional and non- functional properties. We present an abstract design and analysis framework, which allows for faster and cost-effective implementation decisions. This framework is intended as an intermediate reasoning support for system level software/hardware co-design environments. It can prune the design space at its largest, and identify candidate design solutions in a fast and efficient way. In the framework, we use an abstract clock-based encoding to model system behaviors. Different mapping and scheduling scenarios of applications on MPSoCs are analyzed via clock traces representing system simulations. Among properties of interest are functional behavioral correctness, temporal performance and energy consumption. Second, the reconfiguration management of adaptive MPSoCs must be addressed. We are specially interested in MPSoCs implemented on reconfigurable hardware architectures (i.e., FPGA fabrics), which provide a good flexibility and computational efficiency for adap- tive MPSoCs. We propose a general design framework based on the discrete controller syn- thesis (DCS) technique to address this issue. The main advantage of this technique is that it allows the automatic controller synthesis w.r.t. a given specification of control objectives. In the framework, the system reconfiguration behavior is modeled in terms of synchronous parallel automata. The reconfiguration management computation problem w.r.t. multiple objectives regarding e.g., resource usages, performance and power consumption is encoded as a DCS problem. The existing BZR programming language and Sigali tool are employed to perform DCS and generate a controller that satisfies the system requirements. Finally, we investigate two different ways of combining the two proposed design frame- works for adaptive MPSoCs. Firstly, they are combined to construct a complete design flow for adaptive MPSoCs. Secondly, they are combined to present how the designed run-time manager by the second framework can be integrated into the first framework so that high level simulations can be performed to assess the run-time manager
Bai, Xiaoliang. "Modeling and testing for signal integrity in nanometer system-on-chips /." Diss., Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2003. http://wwwlib.umi.com/cr/ucsd/fullcit?p3112828.
Повний текст джерелаChen, Li. "Software-based self-test and diagnosis for processors and system-on-chips /." Diss., Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2003. http://wwwlib.umi.com/cr/ucsd/fullcit?p3090436.
Повний текст джерелаRech, Paolo. "Soft Errors Induced By Neutrons and Alpha Particles in System on Chips." Doctoral thesis, Università degli studi di Padova, 2010. http://hdl.handle.net/11577/3421895.
Повний текст джерелаQuesta tesi presenta un innovativo setup a basso costo per effettuare dei test sotto radiazione di System on Chips in cui siano integrati moduli di diversa natura e con diverse funzionalità. In particolare sono stati svolti numerosi test sotto radiazione di memorie SRAM integrate, di moduli logici integrati e di microprocessori integrati, analizzando i diversi protocolli di test necessari per poter caratterizzare al meglio la loro sensibilità alla radiazione. Uno dei problemi maggiori che si riscontrano quando si deve testare un System on Chip è la ridotta accessibilità dei vari moduli integrati e i vincoli fisici che devono essere rispettati per effettuare il test stesso e che rendono le procedure di analisi molto difficili. I costruttori, per riuscire a verificare la funzionalità dei vari moduli integrati, usano molto spesso delle tecniche chiamate Design for Testability bastate su strutture di test integrate che permettono un’esaustiva verifica della funzionalità dei moduli minimizzando allo stesso tempo i costi del test. Durante gli esperimenti presentati in questo lavoro abbiamo riutilizzato alcune strutture integrate del tipo Design for Testability per caratterizzare nel dettaglio sia tutti i singoli moduli che compongono un System on Chip che il comportamento globale del dispositivo quando viene esposto a radiazione. La strategia che è proposta in questa tesi può essere generalizzata e applicata a qualunque tipo di modulo integrato e sono presentati anche alcuni suggerimenti sul come applicare le strutture di test DfT agli esperimenti di radiazione. Quando si effettua un esperimenti di radiazione tipicamente ci sono diversi vincoli che, in base al laboratorio in cui gli esperimenti vengono eseguiti, possono essere imposti al setup di test. La scheda di test che abbiamo sviluppato ha una forma monolitica, che la rende facile da posizionare nella maggior parte delle camere di irraggiamento degli acceleratori di particelle utilizzati per questo tipo di esperienze. Inoltre, grazie da un lato all’integrazione delle strutture di test nel System on Chip da caratterizzare e, dall’altro, ad una strategia d’interfaccia che si basa sia sul JTAG che sui Wrappers, i test possono essere eseguiti ad alta frequenza usando però solamente connessioni lente fra un PC e il dispositivo da testare, diminuendo così drasticamente il costo globale degli esperimenti. Questa tesi mostra e discute i risultati ottenuti da molte campagne di esperimenti di radiazione su un System on Chip costruito in tecnologia CMOS a 90 nm da STMicroelectronics. Tale dispositivo è stato pensato e realizzato per essere parte di un complesso progetto automotive; ci siamo dunque focalizzati sulle problematiche derivanti dall’impatto che la radiazione terrestre può avere in questo dispositivo. Abbiamo quindi esposto il chip sia a flussi di neutroni che di particelle alfa. Grazie ai dati ottenuti dagli esperimenti, abbiamo calcolato la sensibilità del modulo SRAM sia a particelle alfa che a neutroni, e abbiamo scoperto che quest’ultima è decisamente inferiore della prima. Abbiamo quindi caratterizzato il comportamento del microprocessore quando è esposto a particelle alfa. Il test statico ha dimostrato che i flip-flop che costituiscono i registri interni del microprocessore hanno un tasso di errore indotto da radiazione più elevato rispetto al modulo memoria utente e memoria codice. Questo risultato è di grande importanza e deve essere considerato, per esempio, quando si costruisce una piattaforma di fault-injection. Per effettuare il test dinamico del microprocessore abbiamo costruito due diversi codici di riferimento, in modo da capire come la corruzione delle riverse risorse di memorizzazione influenzi l’esecuzione del codice. I risultati ottenuti dimostrano che, in una tipica applicazione, gli errori nella memoria codice sono decisamente predominanti rispetto a quelli nei registri interni. Inoltre abbiamo visto che i bit di memoria codice e dei registri non sono sempre critici, e la loro corruzione non necessariamente si propaga all’uscita. Infine, abbiamo considerato l’efficacia e i costi di diverse tecniche di irrobustimento. In particolare, abbiamo studiato come l’ottimizzazione del layout proposta del Design For Manufacturing o la Triple Module Redundancy influenzino la sensibilità alla radiazione del microprocessore. Abbiamo considerato dei chip costruiti con diversi livelli di maturità del Design For Manufacturing e i risultati sperimentali dimostrano che un più alto livello di ottimizzazione aumenta la resistenza del dispositivo alla radiazione alfa. Le tecniche di irrobustimento, comunque, hanno un costo. La decisione su quale tecnica adottare quando si costruisce un dispositivo complesso è un trade-off fra costi, performance e, ovviamente, affidabilità. Le strategie da adottare per un particolare prodotto dipendono quindi dai suoi requisiti e dall’ambiente in cui dovrà essere impiegato.
Sunwoo, John Stroud Charles E. "Built-In Self-Test of programmable resources in microcontroller based System-on-Chips." Auburn, Ala., 2005. http://repo.lib.auburn.edu/2005%20Fall/Thesis/SUNWOO_JOHN_31.pdf.
Повний текст джерелаLudewig, Ralf [Verfasser]. "Integrierte Architektur für das Testen und Debuggen von System-on-Chips / Ralf Ludewig." Aachen : Shaker, 2006. http://d-nb.info/118658789X/34.
Повний текст джерелаSEU, GIOVANNI PIETRO. "Exploiting All-Programmable System on Chips for Closed-Loop Real-Time Neural Interfaces." Doctoral thesis, Università degli studi di Genova, 2019. http://hdl.handle.net/11567/943352.
Повний текст джерелаZhao, Yi. "Fault modeling and on-line testing for deep-submicron noise interference in system-on-chips /." Diss., Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2004. http://wwwlib.umi.com/cr/ucsd/fullcit?p3127634.
Повний текст джерелаLiu, Meng. "Real-Time Communication over Wormhole-Switched On-Chip Networks." Doctoral thesis, Mälardalens högskola, Inbyggda system, 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:mdh:diva-35316.
Повний текст джерелаVäyrynen, Mikael. "Fault-Tolerant Average Execution Time Optimization for General-Purpose Multi-Processor System-On-Chips." Thesis, Linköping University, Linköping University, Linköping University, Department of Computer and Information Science, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-17705.
Повний текст джерелаFault tolerance is due to the semiconductor technology development important, not only for safety-critical systems but also for general-purpose (non-safety critical) systems. However, instead of guaranteeing that deadlines always are met, it is for general-purpose systems important to minimize the average execution time (AET) while ensuring fault tolerance. For a given job and a soft (transient) no-error probability, we define mathematical formulas for AET using voting (active replication), rollback-recovery with checkpointing (RRC) and a combination of these (CRV) where bus communication overhead is included. And, for a given multi-processor system-on-chip (MPSoC), we define integer linear programming (ILP) models that minimize the AET including bus communication overhead when: (1) selecting the number of checkpoints when using RRC or a combination where RRC is included, (2) finding the number of processors and job-to-processor assignment when using voting or a combination where voting is used, and (3) defining fault tolerance scheme (voting, RRC or CRV) per job and defining its usage for each job. Experiments demonstrate significant savings in AET.
Parri, Jonathan. "A Framework for Selection and Integration of Custom Instructions for Hybrid System-on-Chips." Thesis, University of Ottawa (Canada), 2010. http://hdl.handle.net/10393/28739.
Повний текст джерелаQi, Ji. "System-level design automation and optimisation of network-on-chips in terms of timing and energy." Thesis, University of Southampton, 2015. https://eprints.soton.ac.uk/386210/.
Повний текст джерелаHuang, Jia [Verfasser], Alois [Akademischer Betreuer] Knoll, and Petru [Akademischer Betreuer] Eles. "Towards an Integrated Framework for Reliability-Aware Embedded System Design on Multiprocessor System-on-Chips / Jia Huang. Gutachter: Alois Knoll ; Petru Eles. Betreuer: Alois Knoll." München : Universitätsbibliothek der TU München, 2014. http://d-nb.info/1063724333/34.
Повний текст джерелаYang, Xiaokun. "A High Performance Advanced Encryption Standard (AES) Encrypted On-Chip Bus Architecture for Internet-of-Things (IoT) System-on-Chips (SoC)." FIU Digital Commons, 2016. http://digitalcommons.fiu.edu/etd/2477.
Повний текст джерелаJacob, Kabakci Nisha [Verfasser], Georg [Akademischer Betreuer] Sigl, Georg [Gutachter] Sigl, and Sebastian [Gutachter] Steinhorst. "Hardware Trojans and their Security Impact on Reconfigurable System-on-Chips / Nisha Jacob Kabakci ; Gutachter: Georg Sigl, Sebastian Steinhorst ; Betreuer: Georg Sigl." München : Universitätsbibliothek der TU München, 2020. http://d-nb.info/1220319899/34.
Повний текст джерелаHirmer, Katrin [Verfasser], Klaus [Akademischer Betreuer] Hofmann, and Dirk [Akademischer Betreuer] Killat. "Interference-Aware Integration of Mixed-Signal Designs and Ultra High Voltage Pulse Generators for System-on-Chips / Katrin Hirmer ; Klaus Hofmann, Dirk Killat." Darmstadt : Universitäts- und Landesbibliothek Darmstadt, 2019. http://d-nb.info/1199006408/34.
Повний текст джерелаHirmer, Katrin [Verfasser], Klaus Akademischer Betreuer] Hofmann, and Dirk [Akademischer Betreuer] [Killat. "Interference-Aware Integration of Mixed-Signal Designs and Ultra High Voltage Pulse Generators for System-on-Chips / Katrin Hirmer ; Klaus Hofmann, Dirk Killat." Darmstadt : Universitäts- und Landesbibliothek Darmstadt, 2019. http://d-nb.info/1199006408/34.
Повний текст джерелаSantos, André Flores dos. "Análise do uso de redundância em circuitos gerados por síntese de alto nível para FPGA programado por SRAM sob falhas transientes." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2017. http://hdl.handle.net/10183/178392.
Повний текст джерелаThis work consists of the study and analysis of the susceptibility to effects of radiation in circuits projects generated by High Level Synthesis tool for FPGAs Field Programmable Gate Array (FPGAs), that is, system-on-chip (SOC). Through an emulation fault injector using ICAP (Internal Configuration Access Port), located inside the FPGA, it is possible to inject single or accumulated failures of the type SEU (Single Event Upset), defined as disturbances that can affect the correct functioning of the device through the inversion of a bit by a charged particle. SEU is within the classification of SEEs (Single Event Effects), can occur due to the penetration of high energy particles from space and from the sun (cosmic and solar rays) in the Earth's atmosphere that collide with atoms of nitrogen and oxygen resulting in the production of charged particles, most of them neutrons. In this context, in addition to analyzing the susceptibility of projects generated by a High Level Synthesis tool, it becomes relevant to study redundancy techniques such as TMR (Triple Modular Redundancy) for detection, correction of errors and comparison with unprotected projects verifying the reliability. The results show that in the simple fault injection mode TMR redundant projects prove to be effective. In the case of accumulated fault injection, the multichannel design presented better reliability than the unprotected design and with single channel redundancy, tolerating a greater number of failures before its operation was compromised.
Feki, Anis. "Conception d’une mémoire SRAM en tension sous le seuil pour des applications biomédicales et les nœuds de capteurs sans fils en technologies CMOS avancées." Thesis, Lyon, INSA, 2015. http://www.theses.fr/2015ISAL0018/document.
Повний текст джерелаEmergence of large Systems-On-Chip introduces the challenge of power management. Of the various embedded blocks, static random access memories (SRAM) constitute the angrier contributors to power consumption. Scaling down the power supply is one way to act positively on power consumption. One aggressive target is to enable the operation of SRAMs at Ultra-Low-Voltage, i.e. as low as 300 mV (lower than the threshold voltage of standard CMOS transistors). The present work concerned the proposal of SRAM bitcells able to operate at ULV and for advanced technology nodes (either CMOS bulk 28 nm or FDSOI 28 nm). The benchmarking of published architectures as state-of-the-art has led to propose two flavors of 10-transitor bitcells, solving the limitations due to leakage current and parasitic power consumption. Segmented read-ports have been used along with the required synchronous peripheral circuitry including original replica assistance, a dedicated unbalanced sense amplifier for ULV operation and dynamic forward back-biasing of SOI boxes. Experimental test chips are provided in previously mentioned technologies. A complete memory cut of 32 kbits (1024x32) has been designed with an embedded BIST block, able to operate at ULV. After a general introduction, the manuscript proposes the state-of-the-art in chapter two. The new 10T bitcells are presented in chapter 3. The sense amplifier along with the replica assistance is the core of chapter 4. The memory cut in FDSOI 28 nm is detailed in chapter 5. Results of the PhD have been disseminated with 4 patent proposals, 2 papers in international conferences, a first paper accepted in an international journal and a second but only submitted paper in an international journal
Larsson, Anders. "Test Optimization for Core-based System-on-Chip." Doctoral thesis, Linköping : Department of Computer and Information Science, Linköpings universitet, 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-15182.
Повний текст джерелаTambara, Lucas Antunes. "Caracterização de circuitos programáveis e sistemas em chip sob radiação." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2013. http://hdl.handle.net/10183/86477.
Повний текст джерелаThis work consists in a study about the radiation effects in programmable circuits and System-on-Chips (SoCs) based on FPGAs (Field-Programmable Gate Arrays). Single Event Effects (SEEs) and Total Ionizing Dose (TID) are the two main effects caused by the radiation incidence, and both can imply in the occurrence of failures in integrated circuits. SEEs are due to the incidence of neutrons derived from the interaction of the cosmic rays with the terrestrial atmosphere, as well as heavy ions coming from the space and protons provided from the solar wind and the Van Allen belts. Total Ionizing Dose regards the prolonged exposure of an integrated circuit to the ionizing radiation, which deviates the standard electrical characteristics of the device due to radiation-induced electrical charges accumulated in the semiconductors’ interfaces. In this context, this work aims to describe in details the characterization of Microsemi’s mixed-signal SoC-FPGA SmartFusion A2F200-FG484 when exposed to radiation (SEEs and TID), using a Diverse Redundancy approach for error detection. As well, an architecture using a Diversified Triple Modular Redundancy scheme was tested (SEEs) through its implementation in a Xilinx’s Spartan-6 LX45 FPGA, aiming error detection and correction. The results obtained show that several functional blocks from SmartFusion have different radiation tolerance levels and that the use of the Triple Modular Redundancy together with Diversified Redundancy proved to be extremely efficient in terms of SEEs tolerance.
Samii, Soheil. "Power Modeling and Scheduling of Tests for Core-based System Chips." Thesis, Linköping University, Department of Computer and Information Science, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2863.
Повний текст джерелаThe technology today makes it possible to integrate a complete system on a single chip, called "System-on-Chip'' (SOC). Nowadays SOC designers use previously designed hardware modules, called cores, together with their user defined logic (UDL), to form a complete system on a single chip. The manufacturing process may result in defect chips, for instance due to the base material, and therefore testing chips after production is important in order to ensure fault-free chips.
The testing time for a chip will affect its final cost. Thus it is important to minimize the testing time for each chip. For core-based SOCs this can be done by testing several cores at the same time, instead of testing the cores sequentially. However, this will result in a higher activity in the chip, hence higher power consumption. Due to several factors in the manufacturing process there are limitations of the power consumption for a chip. Therefore, the power limitations should be carefully considered when planning the testing of a chip. Otherwise it can be damaged during test, due to overheating. This leads to the problem of minimizing testing time under such power constraints.
In this thesis we discuss test power modeling and its application to SOC testing. We present previous work in this area and conclude that current power modeling techniques in SOC testing are rather pessimistic. We therefore propose a more accurate power model that is based on the analysis of the test data. Furthermore, we present techniques for test pattern reordering, with the objective of partitioning the test power consumption into low parts and high parts.
The power model is included in a tool for SOC test architecture design and test scheduling, where the scheduling heuristic is designed for SOCs with fixed- width test bus architectures. Several experiments have been conducted in order to evaluate the proposed approaches. The results show that, by using the presented power modeling techniques in test scheduling algorithms, we will get lower testing times and thus lower test cost.
Andersson, Dickfors Robin, and Nick Grannas. "OBJECT DETECTION USING DEEP LEARNING ON METAL CHIPS IN MANUFACTURING." Thesis, Mälardalens högskola, Akademin för innovation, design och teknik, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:mdh:diva-55068.
Повний текст джерелаDIGICOGS
Peterson, Mackenzie. "The Effect of the Antecedent Dry Conditions on Nitrogen Removal for a Modified Bioretention System." Scholar Commons, 2016. http://scholarcommons.usf.edu/etd/6567.
Повний текст джерелаRajamanikkam, Chidhambaranathan. "Understanding Security Threats of Emerging Computing Architectures and Mitigating Performance Bottlenecks of On-Chip Interconnects in Manycore NTC System." DigitalCommons@USU, 2019. https://digitalcommons.usu.edu/etd/7453.
Повний текст джерелаChen, Yi-Jung, and 陳依蓉. "System Synthesis for Multi-Processor System-on-Chips." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/98033304483594207429.
Повний текст джерела國立臺灣大學
資訊工程學研究所
98
Multi-core architecture is attractive to applications with significant parallelism since multiple processing elements (PEs) are put on a single die to support parallel execution. However, multi-core architecture also stresses the memory system with concurrent memory accesses from different PEs. With the number of cores on a chip increases, the main memory bandwidth requirement also grows. Therefore, it is important to have a memory-aware design when designing Multi-Processor System-on-Chips (MPSoCs). In this thesis, we propose memory-aware MPSoC synthesis methods for MPSoCs with two different architectures: (a) MPSoCs with the traditional 2-Dimensional (2D) CPU-DRAM connection, and (b) MPSoCs with 3-Dimensional (3D) stacked DRAMs. For MPSoCs with the traditional 2D CPU-DRAM connection, the main memory bandwidth is limited due to pin limitations. To maximize system performance, it is important to simultaneously consider the PE and on-chip memory architecture design with limited on-chip resource. That is, on one hand, we want to allocate as many PEs as possible to fully utilize the available task parallelism in the target applications, and on the other hand, we need to incorporate a significant amount of on-chip memory to alleviate memory bottleneck. However, in a traditional MPSoC design flow, memory and computation components are often considered independently. To tackle this problem, we develop the first PE and memory co-synthesis framework for MPSoCs with 2D CPU-DRAM connections. The goal of the algorithm is to simultaneously synthesize the allocation of PE and on-chip memory modules so that system performance is maximized subject to the resource constraint. In MPSoCs with stacked DRAMs, the 3D die-stacking technology utilizes Though-Silicon Vias (TSVs) to integrate processing cores and DRAMs on the same chip. Moreover, the TSVs that can be placed densely provide high DRAM bandwidth for the system. Therefore, to utilize the high DRAM bandwdith, each PE can have a local DRAM memory controller (DMC) so that it can directly access the DRAM module stacked on top of the PE. This forms a distributed memory interface for CPU-DRAM connection in MPSoCs with stacked DRAMs. However, a DMC occupies a significant share of transistor budget, which can be traded for enlarging the capacity of high speed local SRAM. Moreover, TSVs need extra manufacturing cost and have adverse impact on chip yields. Therefore, the distributed memory interface, including the number of allocated DMCs and vertical bus width of each DMC, should be designed carefully. To tackle this problem, in this thesis, we propose the first algorithm to synthesize the DMC allocation and vertical bus allocation for MPSoCs with stacked DRAMs. The goal of the proposed algorithm is to find a proper distributed memory interface design for the given task set so that the total number of TSVs in the system is minimized while the user-defined performance constraint is met.
Wang, Shen-Min, and 王勝民. "Chips Pileup Cause Analysis System Based On Knowledge Integration." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/36219724414444598207.
Повний текст джерела中華大學
資訊工程學系碩士班
93
With the development of computer hardware, semi-conductor industry becomes one of mainstreams in the world. During the process of semi-conductor production, delivery of goods is often delayed due to materials piling-up in-between machines. That causes a great loss for semi-conductor manufacturers. In order to increase the competitiveness of the semi-conductor industry, pileup cause analysis is important. Nowadays, operations of production lines usually follow a fixed procedure and the pileup cause analysis was done by a set of rules that was predefined by a single experienced engineer. Exceptional conditions are hard to be detected on-line and the pileup analysis rules are also hard to be modified to reflect the change of operation status. In this thesis, a knowledge-based approach is proposed to analyze the pileup causes within semi-conductor production. A multi-expert knowledge acquisition tool is developed to extract pileup cause analysis rules from various experienced engineers. A knowledge-based Pileup Cause Analysis System (abbreviated as PICAS) that utilizes the extracted rules is also developed to analyze the pileup cause on-line. With knowledge extracted from multiple production-line experts, PICAS is more objective, avoiding problems that might be occurred from a single non-experienced engineer. And with knowledge-based approach, analysis rules are easy to be modified to reflect the on-line situations. That makes the pileup cause analysis more realistic and on-time. On-line experiments show that more satisfaction was gained with our new approach.
Malave-Bonet, Javier. "A Benchmarking Platform For Network-On-Chip (NOC) Multiprocessor System-On- Chips." Thesis, 2010. http://hdl.handle.net/1969.1/ETD-TAMU-2010-12-8662.
Повний текст джерела"Test architecture design and optimization for three-dimensional system-on-chips." 2010. http://library.cuhk.edu.hk/record=b5894366.
Повний текст джерела"October 2010."
Thesis (M.Phil.)--Chinese University of Hong Kong, 2010.
Includes bibliographical references (leaves 71-76).
Abstracts in English and Chinese.
Abstract --- p.i
Acknowledgement --- p.ii
Chapter 1 --- Introduction --- p.1
Chapter 1.1 --- Three Dimensional Integrated Circuit --- p.1
Chapter 1.1.1 --- 3D ICs --- p.1
Chapter 1.1.2 --- Manufacture --- p.3
Chapter 1.2 --- Test Architecture Design and Optimization for SoCs --- p.4
Chapter 1.2.1 --- Test Wrapper --- p.4
Chapter 1.2.2 --- Test Access Mechanism --- p.6
Chapter 1.2.3 --- Test Architecture Optimization and Test Scheduling --- p.7
Chapter 1.3 --- Thesis Motivation and Organization --- p.9
Chapter 2 --- On Test Time and Routing Cost --- p.12
Chapter 2.1 --- Introduction --- p.12
Chapter 2.2 --- Preliminaries and Motivation --- p.13
Chapter 2.3 --- Problem Formulation --- p.17
Chapter 2.3.1 --- Test Cost Model --- p.17
Chapter 2.3.2 --- Routing Model --- p.17
Chapter 2.3.3 --- Problem Definition --- p.19
Chapter 2.4 --- Proposed Algorithm --- p.22
Chapter 2.4.1 --- Outline of The Proposed Algorithm --- p.22
Chapter 2.4.2 --- SA-Based Core Assignment --- p.24
Chapter 2.4.3 --- Heuristic-Based TAM Width Allocation --- p.25
Chapter 2.4.4 --- Fast routing Heuristic --- p.28
Chapter 2.5 --- Experiments --- p.29
Chapter 2.5.1 --- Experimental Setup --- p.29
Chapter 2.5.2 --- Experimental Results --- p.31
Chapter 2.6 --- Conclusion --- p.34
Chapter 3 --- Pre-bond-Test-Pin Constrained Test Wire Sharing --- p.37
Chapter 3.1 --- Introduction --- p.37
Chapter 3.2 --- Preliminaries and Motivation --- p.38
Chapter 3.2.1 --- Prior Work in SoC Testing --- p.38
Chapter 3.2.2 --- Prior Work in Testing 3D ICs --- p.39
Chapter 3.2.3 --- Test-Pin-Count Constraint in 3D IC Pre-Bond Testing --- p.40
Chapter 3.2.4 --- Motivation --- p.41
Chapter 3.3 --- Problem Formulation --- p.43
Chapter 3.3.1 --- Test Architecture Design under Pre-Bond Test-Pin-Count Constraint --- p.44
Chapter 3.3.2 --- Thermal-aware Test Scheduling for Post-Bond Test --- p.45
Chapter 3.4 --- Layout-Driven Test Architecture Design and Optimization --- p.46
Chapter 3.4.1 --- Scheme 1: TAM Wire Reuse with Fixed Test Architectures --- p.46
Chapter 3.4.2 --- Scheme 2: TAM Wire Reuse with Flexible Pre-bond Test Architecture --- p.52
Chapter 3.5 --- Thermal-Aware Test Scheduling for Post-Bond Test --- p.53
Chapter 3.5.1 --- Thermal Cost Function --- p.54
Chapter 3.5.2 --- Test Scheduling Algorithm --- p.55
Chapter 3.6 --- Experimental Results --- p.56
Chapter 3.6.1 --- Experimental Setup --- p.56
Chapter 3.6.2 --- Results and Discussion --- p.58
Chapter 3.7 --- Conclusion --- p.59
Chapter 3.8 --- Acknowledgement --- p.60
Chapter 4 --- Conclusion and Future Work --- p.69
Bibliography --- p.70
Barnes, Christopher J. "A Dynamically Configurable Discrete Event Simulation Framework for Many-Core System-on-Chips." 2010. http://hdl.handle.net/1805/2222.
Повний текст джерелаIndustry trends indicate that many-core heterogeneous processors will be the next-generation answer to Moore's law and reduced power consumption. Thus, both academia and industry are focused on the challenges presented by many-core heterogeneous processor designs. In many cases, researchers use discrete event simulators to research and validate new computer architecture innovations. However, there is a lack of dynamically configurable discrete event simulation environments for the testing and development of many-core heterogeneous processors. To fulfill this need we present Mhetero, a retargetable framework for cycle-accurate simulation of heterogeneous many-core processors along with the cycle-accurate simulation of their associated network-on-chip communication infrastructure. Mhetero is the result of research into dynamically configurable and highly flexible simulation tools with which users are free to produce custom instruction sets and communication methods in a highly modular design environment. In this thesis we will discuss our approach to dynamically configurable discrete event simulation and present several experiments performed using the framework to exemplify how Mhetero, and similarly constructed simulators, may be used for future innovations.
Chung, I.-Chun, and 鍾逸駿. "The Study on Intelligent Control of a Cervical-Lumbar Traction System by DSP Chips." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/32559762311692654642.
Повний текст джерела國立成功大學
系統及船舶機電工程學系碩博士班
92
The purpose of this study is to propose an intelligent cervical- lumbar traction system for rehabilitation because the population of the chronic skeletal neuromuscular disease is dramatically increasing. There are two major shortcomings for traditional traction systems. One is traction control is based on an open-loop manual structure. The other is only one set of fixed EMG applies to therapeutic services for all patients. In this study, a learning ENG knowledge base is constructed and will auto-renew patient’s data after each therapy. To achieve intelligent control, two fuzzy controllers by DSP chips are designed. An EMG fuzzy controller is used to deduce more suitable EMG from the constructed EMG knowledge base. According to the deduced EMG, the traction weight will be different for different patient rehabilitation. A traction fuzzy controller is used to accurately control a DC motor to achieve a safe and comfortable therapy. The system not only combines myoelectric signal feedback and autocontrol of traction weight avoiding muscle harm or causing more pain after traction because of the improper manipulation, but also provides a graphic user interface for more convenient. However, it will be increasing the value of product itself, but also give a great deal of inspirations to the future related researches.
LIU, CHIA-YIN, and 劉佳音. "Thermal-aware Memory System Design Automation Method for Multi-Processor System-on-Chips with 3D-stacked Hybrid Memories." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/kzn2cx.
Повний текст джерела國立暨南國際大學
資訊工程學系
106
Stacking memories on Multi-Processor System-on-Chips (MPSoCs) by Through-Silicon Vias (TSVs) provides high speed and wide bandwidth to overcome the memory wall problem and supply heterogeneous integration to integrate resources vertically. However, it is prone to face a thermal management problem because of the stacked power density. In terms of the resource allocation, using stacked-DRAM and TSVs bundles occupying areas in the logic layer can be traded for local memories to improve the system performance. In this paper, we propose a thermal-aware hardware and software co-design synthesis algorithm to optimize the performance in the limited resources under thermal constraint by considering stacked DRAM or SRAM, allocation of DRAM memory controllers(DMCs) if choosing DRAM, configuration of TSV bundles, the resource trade-off in the logic layer, and thermalaware task and data co-allocation. Compared to stacked-SRAM only configuration, applying thermal-aware software-only method, the proposed method can achieve 149% performance improvement on the average. And achieve 138% improvement on the average compared to stacked-DRAM one. The system temperature of the proposed method are all well kept under the given thermal constraint, 85◦C.
Nahvi, Yawar M. "Transmission-gate based variation tolerant active clock deskewing for deep submicron system on chips (SoCs)." 2007. http://proquest.umi.com/pqdweb?did=1240710771&sid=7&Fmt=2&clientId=39334&RQT=309&VName=PQD.
Повний текст джерелаTitle from PDF title page (viewed on July 06, 2007) Available through UMI ProQuest Digital Dissertations. Thesis adviser: Ramalingam, Sridhar. Includes bibliographical references.
蔡宜璋. "Fast FPGA prototyping of block-matching operations for video coding using system-on-programmable chips." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/20185273350619798693.
Повний текст джерелаHirmer, Katrin. "Interference-Aware Integration of Mixed-Signal Designs and Ultra High Voltage Pulse Generators for System-on-Chips." Phd thesis, 2019. https://tuprints.ulb.tu-darmstadt.de/9118/1/2019-10-21_Hirmer_Katrin.pdf.
Повний текст джерелаCheng, Adriel. "Verification of systems-on-chips using genetic evolutionary test techniques from a software applications perspective." Thesis, 2010. http://hdl.handle.net/2440/62335.
Повний текст джерелаThesis (Ph.D.) -- University of Adelaide, School of Electrical and Electronic Engineering, 2010
Lee, Chang Joo 1975. "DRAM-aware prefetching and cache management." Thesis, 2010. http://hdl.handle.net/2152/ETD-UT-2010-12-2492.
Повний текст джерелаtext
WU, CHENG-EN, and 吳承恩. "Thermal-aware Task and Data Placement for Optimizing the Performance of Multi-Processor System-on-Chips with 3D-stacked Memories Architecture." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/ft7bs9.
Повний текст джерела國立暨南國際大學
資訊工程學系
105
The architecture of Multi-Processor Systems-on-Chips (MPSoCs) with 3D-stakced memories is considered as one of the most promising way to mitigate the memory wall problem of an MPSoC. However, the increasing power density of a 3D IC makes the MPSoC more likely to be in the thermal emergent condition. Studies also show that, devices that are vertically aligned in the 3D IC have strong thermal correlation, and devices that are farther from the heat sink have more difficulties in thermal dissipation. To ease the thermal emergent problem of an 3D IC, the power consumption of each vertically aligned device should be managed to avoid overheating. The management of power consumption can be achieved by software design techniques, such as thermal-aware task scheduling and data placement, or hardware design techniques, such as allocating SRAM and DRAM layers according to the thermal limit. In this paper, we focus on the design of the software architecture, and propose a thermal-aware task and data placement synergistically method for the target architecture. Different form the existing thermal-aware task scheduling and data placement methods that consider the stacked cores or stacked memories only, the synergistically method designed in this paper considers the heterogeneity of cores and memory elements to optimize system performance given the thermal constraint. In experimental results, compare to performance-aware method, our method only loss 10% system performance below thermal constraint. Compare to data-only placement and task-only placement, our method have respectively improved 5% and 5.3% system performance.
Cheng, Cheng-Hsiang, and 鄭丞翔. "The Design of CMOS System-on-Chips (SoCs) and Closed-Loop Neuromodulation Systems for Human Epileptic Seizure and Parkinson’s Disease Control." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/x4655k.
Повний текст джерелаChen, Po-Lin, and 陳柏霖. "Fast Test Integration: Toward Plug-and-Play Embedded At-speed Test Framework for Multiple Clock Domains in System-On-Chips Based on IEEE Standard 1500." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/68087992473847969806.
Повний текст джерела國立清華大學
電機工程學系
99
隨著製程技術的不斷提升,晶片速度持續攀高,與時序(timing)相關的延遲缺陷(delay defects),例如電阻短路、電阻斷路或者是訊號完整性問題,也逐漸了主宰晶片測試的品質(test quality)。然而,以傳統偵測定值錯誤(Stuck-at fault)為主流的測試方法並無法有效的檢測出時序相關的延遲缺陷,因此無法驗證晶片是否能夠操作在設計規格(design specifications)所規範的功能時脈速度(functional clock speed) 。單單依靠傳統定值錯誤測試不僅僅降低測試效率也額外增加測試負擔與成本(test cost)。因此,為解決時序相關的延遲缺陷所導致的後段測試的困難,半導體業界發展出相對應單一時脈域(single clock domain)延遲錯誤測試(delay fault test)或者稱全速測試(at-speed test)來針對單一頻率待測電路的延遲錯誤測試。然而,製程技術的快速發展也促使系統晶片(System-on-Chip)的設計策略得以整合多顆具有高效能、多重時脈(multiple clock domain)的設計於其中。跨頻域CDC (Clock Domain Crossing)的資料傳輸模式也促使延遲錯誤測試必須從原本單一時脈域的延遲測試延伸至多重時脈域且跨時脈域的延遲錯誤測試,以確保整體延遲錯誤測試的品質。 然而,針對高速且多重時脈域的系統晶片的延遲錯誤測試已非傳統低階自動測試機台(Automatic Test Equipment)所能支援,因此,內嵌式可支援延遲錯誤測試的可測性設計(Design-for-Testability)變得相當重要與熱門,尤其在SOC設計模式的考量下,所有的邏輯電路皆內嵌在其中,無法由chip level的I/Os所控制與觀察,如何在chip內部執行多重時脈域的延遲錯誤測試,變得困難重重。雖然由美國電子電機工程師學會(Institute of Electrical and Electronic Engineers, IEEE)所提出模組化的系統晶片測試標準(IEEE Standard 1500)來對SOC中內嵌的邏輯電路(embedded cores)作有效的測試,但是並無提供任延遲測試相關之解決方案。因此,如何針對現有IEEE 1500所規範的測試標準之下,提出具有低面積開銷(low area overhead)、強健性(robustness)、且具有支援多重時脈域延遲錯誤測試的內嵌可測性設計來提升整體延遲錯誤測試的測試品質及可靠度並且降低測試成本為現階段提升系統晶片測試品質非常重要的部份。
Surendran, Sudhakar. "A Systematic Approach To Synthesis Of Verification Test-Suites For Modular SoC Designs." Thesis, 2006. http://hdl.handle.net/2005/397.
Повний текст джерелаNarayanasetty, Bhargavi. "Analysis of high performance interconnect in SoC with distributed switches and multiple issue bus protocols." Thesis, 2011. http://hdl.handle.net/2152/ETD-UT-2011-05-3325.
Повний текст джерелаtext
Runge, Armin. "Advances in Deflection Routing based Network on Chips." Doctoral thesis, 2017. https://nbn-resolving.org/urn:nbn:de:bvb:20-opus-149700.
Повний текст джерелаDie Fortschritte der letzten Jahre bei der Fertigung von Halbleiterchips ermöglichen eine Vielzahl an Rechenkernen auf einem einzelnen Chip. Die in diesem Zusammenhang immer weiter sinkenden Strukturgrößen führen jedoch dazu, dass Fehlertoleranz und Energieverbrauch zentrale Herausforderungen darstellen werden. Aufgrund der hohen Parallelität in solchen Systemen, ist außerdem eine leistungsfähige Kommunikationsinfrastruktur unabdingbar. Das in diesen hochgradig parallelen Systemen überwiegend eingesetzte System zur Datenübertragung ist ein Netzwerk auf einem Chip (engl. Network on Chip (NoC)). Der Fokus dieser Dissertation liegt auf NoCs, die auf dem Prinzip des sog. Deflection Routing basieren. In diesem Kontext wurden Beiträge zu zwei Bereichen geleistet, der Fehlertoleranz und der Dimensionierung der optimalen Breite von Verbindungen. Beide Aspekte sind für den Einsatz zuverlässiger, energieeffizienter, Deflection Routing basierter NoCs essentiell. Es ist davon auszugehen, dass zukünftige Halbleiter-Systeme mit einer hohen Fehlerwahrscheinlichkeit zurecht kommen müssen. Die hohe Konnektivität, die in den meisten NoC Topologien inhärent gegeben ist, kann ausgenutzt werden, um den Ausfall von Verbindungen und anderen Komponenten zu tolerieren. Im Rahmen dieser Arbeit wurde vor diesem Hintergrund eine fehlertolerante Router-Architektur entwickelt, die sich durch das eingesetzte Verbindungsnetzwerk und das Verfahren zur Überwindung komplexer Fehlersituationen auszeichnet. Die präsentierten Simulations-Ergebnisse zeigen, dass selbst bei sehr hohen Fehlerwahrscheinlichkeiten alle Datenpakete ihr Ziel erreichen. Im Vergleich zu Router-Architekturen die auf Routing-Tabellen basieren, sind die Hardware-Kosten der hier vorgestellten Router-Architektur gering und insbesondere unabhängig von der Anzahl an Komponenten im Netzwerk, was den Einsatz in sehr großen Netzen ermöglicht. Neben der Fehlertoleranz sind die Hardware-Kosten sowie die Energieeffizienz von NoCs von großer Bedeutung. Einen entscheidenden Einfluss auf diese Aspekte hat die verwendete Breite der Verbindungen des NoCs. Insbesondere bei Deflection Routing basierten NoCs führt eine Über- bzw. Unterdimensionierung der Breite der Verbindungen zu unnötig hohen Hardware-Kosten bzw. schlechter Performanz. Im zweiten Teil dieser Arbeit wird die optimale Breite der Verbindungen eines Deflection Routing basierten NoCs untersucht. Außerdem wird ein Verfahren zur Reduzierung der Breite dieser Verbindungen vorgestellt. Simulations- und Synthese-Ergebnisse zeigen, dass dieses Verfahren eine erhebliche Reduzierung der Hardware-Kosten bei ähnlicher Performanz ermöglicht
Basavaraj, T. "NoC Design & Optimization of Multicore Media Processors." Thesis, 2013. http://etd.iisc.ernet.in/2005/3296.
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