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Статті в журналах з теми "System-on-chips"
Koyanagi, M., H. Kurino, Kang Wook Lee, K. Sakuma, N. Miyakawa, and H. Itani. "Future system-on-silicon LSI chips." IEEE Micro 18, no. 4 (1998): 17–22. http://dx.doi.org/10.1109/40.710867.
Повний текст джерелаMiller, Chris P., Woojung Shin, Eun Hyun Ahn, Hyun Jung Kim, and Deok-Ho Kim. "Engineering Microphysiological Immune System Responses on Chips." Trends in Biotechnology 38, no. 8 (August 2020): 857–72. http://dx.doi.org/10.1016/j.tibtech.2020.01.003.
Повний текст джерелаThomas, Anitta, and Shinoj J Vattakuzhi. "Simulation Results for a Crosstalk Avoidance and Low Power Coding Scheme for System on Chips." Bonfring International Journal of Research in Communication Engineering 6, no. 1 (February 29, 2016): 01–05. http://dx.doi.org/10.9756/bijrce.10444.
Повний текст джерелаLi, Chun Guang, Xiao Ming Ma, and Hai Jun Tang. "Experimental Research on Energy Spectrum Analysis on Chips from Aeroengine Oil System." Applied Mechanics and Materials 635-637 (September 2014): 957–61. http://dx.doi.org/10.4028/www.scientific.net/amm.635-637.957.
Повний текст джерелаLiu, Kan, and Hao You. "Real-Time Micro-Fluidic Chip Pressure Control System Base on the Optical Interference." Applied Mechanics and Materials 494-495 (February 2014): 1274–77. http://dx.doi.org/10.4028/www.scientific.net/amm.494-495.1274.
Повний текст джерелаXiao, Hao, Huajuan Zhang, Fen Ge, and Ning Wu. "A MapReduce architecture for embedded multiprocessor system-on-chips." IEICE Electronics Express 13, no. 2 (2016): 20151025. http://dx.doi.org/10.1587/elex.13.20151025.
Повний текст джерелаPIONTECK, THILO, CARSTEN ALBRECHT, ROMAN KOCH, and ERIK MAEHLE. "ADAPTIVE COMMUNICATION ARCHITECTURES FOR RUNTIME RECONFIGURABLE SYSTEM-ON-CHIPS." Parallel Processing Letters 18, no. 02 (June 2008): 275–89. http://dx.doi.org/10.1142/s0129626408003387.
Повний текст джерелаJavaid, Haris, Aleksander Ignjatovic, and Sri Parameswaran. "Performance Estimation of Pipelined MultiProcessor System-on-Chips (MPSoCs)." IEEE Transactions on Parallel and Distributed Systems 25, no. 8 (August 2014): 2159–68. http://dx.doi.org/10.1109/tpds.2013.268.
Повний текст джерелаRavi, Srivaths, Rubin Parekhji, and Jayashree Saxena. "Low Power Test for Nanometer System-on-Chips (SoCs)." Journal of Low Power Electronics 4, no. 1 (April 1, 2008): 81–100. http://dx.doi.org/10.1166/jolpe.2008.155.
Повний текст джерелаBrekling, Aske, Michael R. Hansen, and Jan Madsen. "Models and formal verification of multiprocessor system-on-chips." Journal of Logic and Algebraic Programming 77, no. 1-2 (September 2008): 1–19. http://dx.doi.org/10.1016/j.jlap.2008.05.002.
Повний текст джерелаДисертації з теми "System-on-chips"
Ludewig, Ralf. "Integrierte Architektur für das Testen und Debuggen von System-on-Chips /." Aachen : Shaker, 2006. http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&doc_number=014632870&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA.
Повний текст джерелаAn, Xin. "High level design and control of adaptive multiprocessor system-on-chips." Thesis, Grenoble, 2013. http://www.theses.fr/2013GRENM023/document.
Повний текст джерелаThe design of modern embedded systems is getting more and more complex, as more func- tionality is integrated into these systems. At the same time, in order to meet the compu- tational requirements while keeping a low level power consumption, MPSoCs have emerged as the main solutions for such embedded systems. Furthermore, embedded systems are be- coming more and more adaptive, as the adaptivity can bring a number of benefits, such as software flexibility and energy efficiency. This thesis targets the safe design of such adaptive MPSoCs. First, each system configuration must be analyzed concerning its functional and non- functional properties. We present an abstract design and analysis framework, which allows for faster and cost-effective implementation decisions. This framework is intended as an intermediate reasoning support for system level software/hardware co-design environments. It can prune the design space at its largest, and identify candidate design solutions in a fast and efficient way. In the framework, we use an abstract clock-based encoding to model system behaviors. Different mapping and scheduling scenarios of applications on MPSoCs are analyzed via clock traces representing system simulations. Among properties of interest are functional behavioral correctness, temporal performance and energy consumption. Second, the reconfiguration management of adaptive MPSoCs must be addressed. We are specially interested in MPSoCs implemented on reconfigurable hardware architectures (i.e., FPGA fabrics), which provide a good flexibility and computational efficiency for adap- tive MPSoCs. We propose a general design framework based on the discrete controller syn- thesis (DCS) technique to address this issue. The main advantage of this technique is that it allows the automatic controller synthesis w.r.t. a given specification of control objectives. In the framework, the system reconfiguration behavior is modeled in terms of synchronous parallel automata. The reconfiguration management computation problem w.r.t. multiple objectives regarding e.g., resource usages, performance and power consumption is encoded as a DCS problem. The existing BZR programming language and Sigali tool are employed to perform DCS and generate a controller that satisfies the system requirements. Finally, we investigate two different ways of combining the two proposed design frame- works for adaptive MPSoCs. Firstly, they are combined to construct a complete design flow for adaptive MPSoCs. Secondly, they are combined to present how the designed run-time manager by the second framework can be integrated into the first framework so that high level simulations can be performed to assess the run-time manager
Bai, Xiaoliang. "Modeling and testing for signal integrity in nanometer system-on-chips /." Diss., Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2003. http://wwwlib.umi.com/cr/ucsd/fullcit?p3112828.
Повний текст джерелаChen, Li. "Software-based self-test and diagnosis for processors and system-on-chips /." Diss., Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2003. http://wwwlib.umi.com/cr/ucsd/fullcit?p3090436.
Повний текст джерелаRech, Paolo. "Soft Errors Induced By Neutrons and Alpha Particles in System on Chips." Doctoral thesis, Università degli studi di Padova, 2010. http://hdl.handle.net/11577/3421895.
Повний текст джерелаQuesta tesi presenta un innovativo setup a basso costo per effettuare dei test sotto radiazione di System on Chips in cui siano integrati moduli di diversa natura e con diverse funzionalità. In particolare sono stati svolti numerosi test sotto radiazione di memorie SRAM integrate, di moduli logici integrati e di microprocessori integrati, analizzando i diversi protocolli di test necessari per poter caratterizzare al meglio la loro sensibilità alla radiazione. Uno dei problemi maggiori che si riscontrano quando si deve testare un System on Chip è la ridotta accessibilità dei vari moduli integrati e i vincoli fisici che devono essere rispettati per effettuare il test stesso e che rendono le procedure di analisi molto difficili. I costruttori, per riuscire a verificare la funzionalità dei vari moduli integrati, usano molto spesso delle tecniche chiamate Design for Testability bastate su strutture di test integrate che permettono un’esaustiva verifica della funzionalità dei moduli minimizzando allo stesso tempo i costi del test. Durante gli esperimenti presentati in questo lavoro abbiamo riutilizzato alcune strutture integrate del tipo Design for Testability per caratterizzare nel dettaglio sia tutti i singoli moduli che compongono un System on Chip che il comportamento globale del dispositivo quando viene esposto a radiazione. La strategia che è proposta in questa tesi può essere generalizzata e applicata a qualunque tipo di modulo integrato e sono presentati anche alcuni suggerimenti sul come applicare le strutture di test DfT agli esperimenti di radiazione. Quando si effettua un esperimenti di radiazione tipicamente ci sono diversi vincoli che, in base al laboratorio in cui gli esperimenti vengono eseguiti, possono essere imposti al setup di test. La scheda di test che abbiamo sviluppato ha una forma monolitica, che la rende facile da posizionare nella maggior parte delle camere di irraggiamento degli acceleratori di particelle utilizzati per questo tipo di esperienze. Inoltre, grazie da un lato all’integrazione delle strutture di test nel System on Chip da caratterizzare e, dall’altro, ad una strategia d’interfaccia che si basa sia sul JTAG che sui Wrappers, i test possono essere eseguiti ad alta frequenza usando però solamente connessioni lente fra un PC e il dispositivo da testare, diminuendo così drasticamente il costo globale degli esperimenti. Questa tesi mostra e discute i risultati ottenuti da molte campagne di esperimenti di radiazione su un System on Chip costruito in tecnologia CMOS a 90 nm da STMicroelectronics. Tale dispositivo è stato pensato e realizzato per essere parte di un complesso progetto automotive; ci siamo dunque focalizzati sulle problematiche derivanti dall’impatto che la radiazione terrestre può avere in questo dispositivo. Abbiamo quindi esposto il chip sia a flussi di neutroni che di particelle alfa. Grazie ai dati ottenuti dagli esperimenti, abbiamo calcolato la sensibilità del modulo SRAM sia a particelle alfa che a neutroni, e abbiamo scoperto che quest’ultima è decisamente inferiore della prima. Abbiamo quindi caratterizzato il comportamento del microprocessore quando è esposto a particelle alfa. Il test statico ha dimostrato che i flip-flop che costituiscono i registri interni del microprocessore hanno un tasso di errore indotto da radiazione più elevato rispetto al modulo memoria utente e memoria codice. Questo risultato è di grande importanza e deve essere considerato, per esempio, quando si costruisce una piattaforma di fault-injection. Per effettuare il test dinamico del microprocessore abbiamo costruito due diversi codici di riferimento, in modo da capire come la corruzione delle riverse risorse di memorizzazione influenzi l’esecuzione del codice. I risultati ottenuti dimostrano che, in una tipica applicazione, gli errori nella memoria codice sono decisamente predominanti rispetto a quelli nei registri interni. Inoltre abbiamo visto che i bit di memoria codice e dei registri non sono sempre critici, e la loro corruzione non necessariamente si propaga all’uscita. Infine, abbiamo considerato l’efficacia e i costi di diverse tecniche di irrobustimento. In particolare, abbiamo studiato come l’ottimizzazione del layout proposta del Design For Manufacturing o la Triple Module Redundancy influenzino la sensibilità alla radiazione del microprocessore. Abbiamo considerato dei chip costruiti con diversi livelli di maturità del Design For Manufacturing e i risultati sperimentali dimostrano che un più alto livello di ottimizzazione aumenta la resistenza del dispositivo alla radiazione alfa. Le tecniche di irrobustimento, comunque, hanno un costo. La decisione su quale tecnica adottare quando si costruisce un dispositivo complesso è un trade-off fra costi, performance e, ovviamente, affidabilità. Le strategie da adottare per un particolare prodotto dipendono quindi dai suoi requisiti e dall’ambiente in cui dovrà essere impiegato.
Sunwoo, John Stroud Charles E. "Built-In Self-Test of programmable resources in microcontroller based System-on-Chips." Auburn, Ala., 2005. http://repo.lib.auburn.edu/2005%20Fall/Thesis/SUNWOO_JOHN_31.pdf.
Повний текст джерелаLudewig, Ralf [Verfasser]. "Integrierte Architektur für das Testen und Debuggen von System-on-Chips / Ralf Ludewig." Aachen : Shaker, 2006. http://d-nb.info/118658789X/34.
Повний текст джерелаSEU, GIOVANNI PIETRO. "Exploiting All-Programmable System on Chips for Closed-Loop Real-Time Neural Interfaces." Doctoral thesis, Università degli studi di Genova, 2019. http://hdl.handle.net/11567/943352.
Повний текст джерелаZhao, Yi. "Fault modeling and on-line testing for deep-submicron noise interference in system-on-chips /." Diss., Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2004. http://wwwlib.umi.com/cr/ucsd/fullcit?p3127634.
Повний текст джерелаLiu, Meng. "Real-Time Communication over Wormhole-Switched On-Chip Networks." Doctoral thesis, Mälardalens högskola, Inbyggda system, 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:mdh:diva-35316.
Повний текст джерелаКниги з теми "System-on-chips"
Fokin, Sergey. Improvement of technical means for processing waste from logging operations for fuel chips in felling conditions. ru: INFRA-M Academic Publishing LLC., 2017. http://dx.doi.org/10.12737/24135.
Повний текст джерелаManfred, Glesner, ed. VLSI-SOC, from systems to chips: IFIP TC 10/ WG 10.5 Twelfth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2003), December 1-3, 2003, Darmstadt, Germany. New York: Springer, 2006.
Знайти повний текст джерелаIndrusiak, Leandro, Hans Eveking, Ricardo Reis, Manfred Glesner, and Vincent Mooney. VLSI-SOC : from Systems to Chips: IFIP TC 10/WG 10. 5, Twelfth International Conference on Very Large Scale Ingegration of System on Chip , December 1-3, 2003, Darmstadt, Germany. Springer, 2006.
Знайти повний текст джерелаIndrusiak, Leandro, Hans Eveking, Ricardo Reis, Manfred Glesner, and Vincent Mooney. VLSI-SOC : from Systems to Chips: IFIP TC 10/WG 10. 5, Twelfth International Conference on Very Large Scale Ingegration of System on Chip , December 1-3, 2003, Darmstadt, Germany. Springer, 2010.
Знайти повний текст джерела(Editor), Manfred Glesner, Ricardo Reis (Editor), Leandro Indrusiak (Editor), Vincent Mooney (Editor), and Hans Eveking (Editor), eds. VLSI-SOC: From Systems to Chips: IFIP TC 10/WG 10.5, Twelfth International Conference on Very Large Scale Ingegration of System on Chip (VLSI-SoC 2003), ... Federation for Information Processing). Springer, 2006.
Знайти повний текст джерелаCameron, James. Collapse of the Consensus and the Struggle for Coherence, 1969–1970. Oxford University Press, 2017. http://dx.doi.org/10.1093/oso/9780190459925.003.0005.
Повний текст джерелаLow-Power NoC for High-Performance SoC Design (System-on-Chip Design and Technologies). CRC, 2008.
Знайти повний текст джерелаЧастини книг з теми "System-on-chips"
Basu, Kanad. "Security Verification of System-on-Chips (SoCs)." In Encyclopedia of Cryptography, Security and Privacy, 1–3. Berlin, Heidelberg: Springer Berlin Heidelberg, 2021. http://dx.doi.org/10.1007/978-3-642-27739-9_1647-1.
Повний текст джерелаBromberger, Michael, Steffen Ehrle, Michael Scharrer, Lukas Erlinghagen, and Jens Schick. "OpenCL-Based 6D-Vision on Heterogeneous System on Chips." In Architecture of Computing Systems - ARCS 2017, 33–46. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-54999-6_3.
Повний текст джерелаLiu, Feng, and Vipin Chaudhary. "A Practical OpenMP Compiler for System on Chips." In OpenMP Shared Memory Parallel Programming, 54–68. Berlin, Heidelberg: Springer Berlin Heidelberg, 2003. http://dx.doi.org/10.1007/3-540-45009-2_5.
Повний текст джерелаEsposito, Stefano, and Massimo Violante. "Mitigating Soft Errors in Processors Cores Embedded in System-on Programmable-Chips." In FPGAs and Parallel Architectures for Aerospace Applications, 219–38. Cham: Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-14352-1_15.
Повний текст джерелаStefanov, Todor, Andy Pimentel, and Hristo Nikolov. "DAEDALUS: System-Level Design Methodology for Streaming Multiprocessor Embedded Systems on Chips." In Handbook of Hardware/Software Codesign, 983–1018. Dordrecht: Springer Netherlands, 2017. http://dx.doi.org/10.1007/978-94-017-7267-9_30.
Повний текст джерелаStefanov, Todor, Andy Pimentel, and Hristo Nikolov. "Daedalus: System-Level Design Methodology for Streaming Multiprocessor Embedded Systems on Chips." In Handbook of Hardware/Software Codesign, 1–36. Dordrecht: Springer Netherlands, 2016. http://dx.doi.org/10.1007/978-94-017-7358-4_30-1.
Повний текст джерелаChakravarthi, Veena S., and Shivananda R. Koteshwar. "Introduction to Design of System on Chips and Future Trends in VLSI." In SoC Physical Design, 1–20. Cham: Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-030-98112-9_1.
Повний текст джерелаHan, Peicen, Zhaohui Ye, and Shiyuan Yang. "The Design and Implementation of Network Video Surveillance System Based on Davinci Chips." In Communications in Computer and Information Science, 296–302. Berlin, Heidelberg: Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-22418-8_41.
Повний текст джерелаSalehi, Mohammad, Florian Kriebel, Semeen Rehman, and Muhammad Shafique. "Power-Aware Fault-Tolerance for Embedded Systems." In Dependable Embedded Systems, 565–88. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-52017-5_24.
Повний текст джерелаKirchner, Aljoscha. "Einleitung." In Entwicklung von Methoden zur abstrakten Modellierung von Automotive Systems-on-Chips, 1–5. Wiesbaden: Springer Fachmedien Wiesbaden, 2022. http://dx.doi.org/10.1007/978-3-658-38437-1_1.
Повний текст джерелаТези доповідей конференцій з теми "System-on-chips"
Joseph, Jan Moritz, Dominik Ermel, Lennart Bamberg, Alberto Garcia Oritz, and Thilo Pionteck. "System-Level Optimization of Network-on-Chips for Heterogeneous 3D System-on-Chips." In 2019 IEEE 37th International Conference on Computer Design (ICCD). IEEE, 2019. http://dx.doi.org/10.1109/iccd46524.2019.00064.
Повний текст джерелаTshagharyan, G., G. Harutyunyan, S. Shoukourian, and Y. Zorian. "Securing test infrastructure of system-on-chips." In 2016 IEEE East-West Design & Test Symposium (EWDTS). IEEE, 2016. http://dx.doi.org/10.1109/ewdts.2016.7807696.
Повний текст джерелаEjnioui, Abdel. "Runtime Adaptation in Reconfigurable System-on-Chips." In 2009 International Conference on Parallel Processing Workshops (ICPPW). IEEE, 2009. http://dx.doi.org/10.1109/icppw.2009.53.
Повний текст джерелаYi Ni, Wai Sum Mong, and Jianwen Zhu. "On virtual prototyping of embedded system-on-chips." In 2011 IEEE 9th International Conference on ASIC (ASICON 2011). IEEE, 2011. http://dx.doi.org/10.1109/asicon.2011.6157402.
Повний текст джерелаMeinhardt, Cristina, Ricardo Reis, Massimo Violante, and Matteo Sonza Reorda. "Recovery scheme for hardening system on programmable chips." In 2009 10th Latin American Test Workshop. IEEE, 2009. http://dx.doi.org/10.1109/latw.2009.4813816.
Повний текст джерелаEychenne, Ch, and Y. Zorian. "An effective functional safety infrastructure for system-on-chips." In 2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS). IEEE, 2017. http://dx.doi.org/10.1109/iolts.2017.8046235.
Повний текст джерелаTenentes, Vasileios, Daniele Rossi, and Bashir M. Al-Hashimi. "Collective-Aware System-on-Chips for Dependable IoT Applications." In 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS). IEEE, 2018. http://dx.doi.org/10.1109/iolts.2018.8474172.
Повний текст джерелаYousuf, Shaon, Adam Jacobs, and Ann Gordon-Ross. "Partially reconfigurable system-on-chips for adaptive fault tolerance." In 2011 International Conference on Field-Programmable Technology (FPT). IEEE, 2011. http://dx.doi.org/10.1109/fpt.2011.6132708.
Повний текст джерелаGharehbaghi, Amir Masoud, and Masahiro Fujita. "Transaction-based debugging of system-on-chips with patterns." In 2009 IEEE International Conference on Computer Design (ICCD 2009). IEEE, 2009. http://dx.doi.org/10.1109/iccd.2009.5413157.
Повний текст джерелаArda, Samet E., Anish NK, A. Alper Goksoy, Joshua Mack, Nirmal Kumbhare, Anderson L. Sartor, Ali Akoglu, Radu Marculescu, and Umit Y. Ogras. "A simulation framework for domain-specific system-on-chips." In CODES/ISSS '19: International Conference on Hardware/Software Codesign and System Synthesis. New York, NY, USA: ACM, 2019. http://dx.doi.org/10.1145/3349567.3351719.
Повний текст джерела