Дисертації з теми "SUBMICRON TECHNOLOGIES"

La reducción de los dispositivos MEMS hasta la nano escala (NEMS) ha permitido el acceso a nuevos dominios de la física y promete revolucionar las aplicaciones de sensado. Sin embargo esta miniaturización ha sido conseguida a costa de procesos de fabicración complicados y no reproducibles. Es por ello que esta tesis trata de obtener dichos dispositivos NEMS a partir de una tecnologia CMOS comercial (ST 65nm). Con este objetivo un estudio en detalle de la tecnología ST 65nm es llevado a cabo para posteriormente definir en ella estructuras NEMS en sus diferentes capas (en polysilicio con un grosor y ancho de 60 nm x 100 nm y en metal 1, cobre , con unas dimensiones de 90nm x 100nm). Un nuevo post proceso de liberación es presentado que nos permite liberar las estructuras, demostrando así su correcta fabricación. Sin embargo, fruto de esta miniaturización las señales eléctricas usadas para sensar su movimiento se reducen también. Como alternativa a un sensado capacitivo estudiamos la viabilidad de adaptar a nuestro proceso de fabricación CMOS-MEMS a un método de transducción basado en un transistor cuyo puerta resuena, su movimiento modula las cargas del canal y dicho desplazamiento puede ser leído en la corriente del puerta del transistor. Mediante dicho método de transducción la respuesta en frecuencia de un resonador de polysilicio a 24 MHz fue leída y su funcionamiento como interruptor a bajos voltajes (2.25 V pull-in) fue validado. Además, proponemos el uso de interruptores mecánicos no solo como memorias o en aplicaciones lógicas (gracias a su eficiencia energética) sino como el elemento base para la implementación de un oscilador en anillo, completamente mecánico. Con este oscilador ampliamos el rango de aplicación de los interruptores N/MEMS a nuevos campos como el sensado de masa pero con el valor añadido de tener una señal digital. Para implementar esta nueva configuración presentamos un modelo y desarrollamos interruptores mecánicos en diferentes tecnologías CMOS intentando siempre reducir sus dimensiones. Con estos interruptores mecánicos CMOS hemos conseguido voltajes de operación bajos (5V), respuestas abruptas (4.3 mV/decada) y una buena relación ION/IOFF (1.104).
The reduction of MEMS devices dimensions to the nano scale (NEMS) has allowed them to access a host of new physics and promise to revolutionize sensing applications. However this miniaturization has been obtained at an expense of dedicated, difficult and non reproducible fabrication processes. This thesis deals with the miniaturization of MEMS structures following a CMOS-MEMS approach. In order to it a small pitch CMOS technology (ST 65nm) is studied in depth, NEMS structures are defined using its available layers (width= 60 nm, thickness= 100nm in polysilicon and width= 90nm, thickness= 180nm in metal 1 based on copper) and a post-CMOS releasing process is developed in order to release them. Successful integration of NEMS devices is demostrated with the added value of a robust, reproducible fabrication and an easy integration with additional circuitry. However this aggressive scaling has a main drawback, small output signals. As an alternative to capacitive read-out, the implementation of a resonant gate transduction, based on the idea of modulate the charge of a transistor by the movement of a mechanical structure, is studied and implemented. The frequency response of a polysilicon resonator implemented in AMS 0.35um CMOS technology (24 MHz) has been successfully characterized and its operation as a low voltage switch (2.25 V pull-in) is demonstrated. In addition, we propose the use of mechanical switches not only as memory or logic devices (due to its energy efficiency), but also as the building blocks of a ring oscillator configuration composed exclusively by mechanical switches. This new approach extends their use to other application as mass sensing but with the added value of a digital output signal. In order to implement this new configuration a model to simulate its behavior is developed and mechanical switches are built using different CMOS technologies, trying always to reduce their dimensions. Low operating voltages (5 V, MIM approach), abrupt response (4.3 mV/decade, ST Metal 1) and good ION/IOFF ratio (1.104, MIM approach) are obtained.

With the aggressive scaling of MOS devices hot carrier degradation continues to be a major reliability concern. The LDD technologies, which have been used to minimise the hot carrier damage in MOS devices, suffer from the spacer damage causing the drain series resistance degradation, along with the channel mobility degradation. Therefore, in order to optimise the performance and reliability of these technologies it is necessary to quantify the roles of spacer and channel damages in determining their degradation behaviour. In this thesis the hot carrier degradation behaviour of different generations of graded drain (lightly doped, mildly doped and highly doped) n-MOS technologies, designed for 5V, 3V and 2V operation is investigated. The stress time beginning from microseconds is investigated to study how the damage initiates and evolves over time. A technology dependent two-stage degradation behaviour in the measured transconductance with an early stage deviating from conventionally observed power law behaviour is reported. A methodology based on conventional extraction procedure using the L-array method is first developed to analyse the drain series resistance and the mobility degradation. For 5V technologies the analysis of the damage using this methodology shows a two-stage drain series resistance degradation with early stage lasting about lOOms. However, it is seen that the conventional series resistance and mobility degradation methodology fails to satisfactorily predict degradation behaviour of 3V and 2V technologies, resulting in unphysical decreasing extracted series resistance. It is shown that after the hot carrier stress a change in the universal mobility behaviour for channel lengths approaching quarter micron regime has a significant effect on the parameter extraction. A modified universal mobility model incorporating the effect of the interface charge is developed using the FN stress experiments. A new generalised extraction methodology modelling hot carrier stressed device as series combination of undamaged and damaged channel regions, along with the series source drain resistance is developed, incorporating the modified universal model in the damaged channel region. The new methodology has the advantage of being single device based and serves as an effective tool in evaluating. the roles of series resistance and mobility degradations for technology qualification. This is especially true for the deep submicron regime where the conventional extraction procedures are not applicable. Further, the new extraction method has the potential of being integrated into commercial device simulation tools, to accurately analyse the device degradation behaviour in deep submicron regime.

Sun’s radiation, coronal mass ejections, electromagnetic storms, galactic cosmic rays, the Van Allen radiation belts, or artificial radiation environments expose microelectronics circuits to serious conditions in space as well as on Earth. Nowadays, a lot of human activities rely on satellites orbiting around the Earth such as the GPS system, video and audio communications, surveillance systems, meteorological forecasts, military applications, etc., and they must operate reliably. Civil air traffic is extremely intense around the world and of course everybody wants to land safely each time they fly. Moreover, nuclear power plants that furnish energy to most of the advanced countries on the planet must operate securely in order not to contaminate the environment around, provoking natural and social disasters. Each of these aspects is strongly dependent on electronics that manage and control every activity, permitting us to live our life peacefully. The main challenge for engineers and scientists that work in this sometimes unknown field is to manufacture and design safe electronics able to operate in those environments even for very long times. The scaling of CMOS technology toward deep-submicron feature sizes plays a fundamental role, regardless of ionizing radiation effects. In fact, as the CMOS devices shrink, featuring ultra-thin gate oxides, the reliability of MOSFETs is affected due to the increase of the operating fields that enhance the natural aging mechanisms. Hot carriers injection from the channel is one of the most important effects, especially in advanced devices because the carrier energy is directly correlated with the electric fields. This thesis in part covers this reliability aspect, both in standard open layout transistors and enclosed layout ones designed to be total-dose hard. A vast literature is available concerning hot carrier mechanisms but this work is one of the only to show the synergies with X-ray induced defects (Total Ionizing Dose, or TID). Indeed, CMOS transistors with feature size equal or below the 130-nm technological node exhibit these kinds of effects, introducing new and interesting aspects. As a result, a different approach must be followed when evaluating the suitability of devices intended for rad-applications since hot-carrier degradation for example can decrease or increase due to previous irradiation. Furthermore, the prediction of oxide lifetime is one of the main types of analysis in the field of CMOS reliability, extremely important to evaluate the quality of the dielectrics. This thesis proves that exposure to TID may affect reliability predictions due to interplay between defects, traps, and trapped charge generated by both accelerated tests. Without these aspects in mind the results can be conservative (when lucky), or can even underestimate the phenomena leading to misleading and dangerous conclusions. Total dose enhancement effects due to interconnects is also a new source of uncertainty in scaled technologies subjected to X-ray irradiation. In fact, the need to have high device density leads to an increase in the number of metal layers as well as a decrease in the inter-metal dielectric thickness, permitting secondary electrons generated by the interaction of X rays with metal tracks to reach the transistors’ active area. This aspect is studied in this thesis through the use of dedicated test structures with different metal layer layouts. The experimental results, coupled with device simulations, give radiation-IC designers some guidelines to avoid systematic criticality and better total dose results. Combined total dose and ageing related effects is not the only focus of this thesis since single events produced by charged particles have become the main source of errors in scaled technologies. Electronics mounted on spacecraft, satellites, aircraft and even at ground level are affected by single event effects, sometimes destructive, sometimes not. In particular, this thesis covers the single event gate rupture (SEGR) phenomenon induced by heavy ions, which is the most risky event during long-term missions. Various aspects have been analyzed in order to fill some gaps present in the literature, starting from the impact of device layout, the influence of the bias applied during accelerated tests and the effects of previous X-ray irradiation. The results presented here demonstrate that different sources of interplay may exist during SEGR tests. Moreover, the provided data strongly indicate use of test structures as close as possible to real scaled transistors instead of large area capacitors to have a straightforward assessment of gate rupture in modern CMOS technologies. In conclusion, this thesis wants to be the first strong contribution for combined radiation and long-term reliability studies in advanced CMOS technologies implemented in harsh radiation environments.
I processi termonucleari che si verificano all’interno del sole danno origine a radiazioni ionizzanti, tempeste elettromagnetiche ed emissioni di masse di plasma coronarico ionizzato che possono raggiungere l’atmosfera terrestre. Inoltre gli effetti indotti dai raggi cosmici, la presenza delle fasce di Van Allen, nonché gli ambienti radioattivi artificiali costruiti dall’uomo, espongono i circuiti microelettronici a condizioni di funzionamento estremo nello spazio e sulla terra. Al giorno d’oggi molte attività umane si basano su satelliti geostazionari che devono rimanere funzionanti ed affidabili per lungo tempo: sistemi GPS, comunicazioni audio e video, sistemi di sorveglianza, satelliti meteorologici, applicazioni per la difesa, etc. Inoltre il traffico aereo civile ad alta quota, anch’esso esposto a radiazioni, è sempre in maggiore espansione e naturalmente ogni passeggero si augura di atterrare sano e salvo ogni volta che necessiti di volare. Non da meno le centrali nucleari che forniscono il fabbisogno energetico alle nazioni più avanzate devono assolutamente operare in sicurezza evitando tremendi disastri naturali e sociali. Ognuna di queste applicazioni è tuttavia fortemente dipendente dall’elettronica che gestisce e controlla ogni attività in modo trasparente rispetto all’utente. La sfida principale per ingegneri e scienziati che lavorano in questo ambito, è quella di studiare e progettare microelettronica in grado di operare in ambienti ostili per lungo tempo e in modo affidabile. Il progresso tecnologico dei dispositivi CMOS verso dimensioni sub-micrometriche gioca un ruolo fondamentale in termini di affidabilità. Infatti, a prescindere dagli effetti delle radiazioni, la riduzione delle dimensioni dei dispositivi e l’implementazione di ossidi ultra sottili influiscono sull’affidabilità dei transistor MOS a causa dell’aumento intrinseco dei campi elettrici che accelerano i naturali processi di degradazione. Per esempio, l’iniezione di portatori caldi è una delle cause più importanti di degradazione in quanto l’energia che gli elettroni possono acquisire è correlata al campo elettrico accelerante. Questa tesi sviluppa questa problematica sia su transistor standard (Open Layout Transistor, OLT) che su transistor ad anello (Enclosed layout Transistor, ELT), questi ultimi progettati per essere immuni dagli effetti di dose totale (Total Ionizing Dose, TID). Sebbene i meccanismi e gli effetti legati ai portatori caldi siano ben documentati nella letteratura di settore, questa tesi è uno dei pochi lavori che si propone di investigare le sinergie con gli effetti indotti dai raggi X, introducendo nuovi e interessanti aspetti legati all’affidabilità. Inoltre la previsione del tempo di vita dell’ossido di gate è una delle informazioni più importanti da tenere in considerazione quando si intende pianificare una missione a lungo termine. Questa tesi dimostra che l’esposizione ai raggi X può alterare i successivi test di affidabilità a causa dell’interazione tra i difetti generati dalle radiazioni e dagli stress elettrici. Di conseguenza, un approccio nuovo va seguito quando si intende valutare l’adeguatezza dei dispositivi da implementare in applicazioni ove siano presenti radiazioni ionizzanti. Senza considerare questi aspetti le previsioni che emergono dai test sperimentali possono in alcuni casi fortunati essere conservative, in altri meno fortunati sottostimare i fenomeni portando a conclusioni fuorvianti e addirittura pericolose per il buon esito di una missione. Una nuova fonte di incertezza e di sinergia per le tecnologie CMOS avanzate esposte a raggi X riguarda il diverso assorbimento di dose totale indotto dalle interconnessioni metalliche. Infatti la necessità di integrazione sempre più spinta obbliga i progettisti ad incrementare il numero di strati di interconnessione nel back-end del dispositivo nonché la riduzione dello spessore dei dielettrici isolanti. Di conseguenza, a fronte di una esposizione ai raggi X, gli elettroni secondari generati dall’interazione con gli strati metallici possono raggiungere più facilmente l’area attiva del transistor degradandolo in modo non uniforme. In questa tesi questo effetto viene studiato grazie all’uso di strutture appositamente progettate, contribuendo cosi allo sviluppo di dispositivi il più possibile immuni da tale fenomeno. D’altro canto gli effetti indotti da particelle cariche (Single Event Effect, SEE) nelle moderne tecnologie stanno diventando la principale fonte di errore. L’elettronica implementata a bordo di navicelle spaziali, satelliti, aerei civili e militari, e perfino al livello del suolo terrestre è affetta da SEEs, a volte distruttivi, a volte no. In particolare questa tesi si focalizza sulla rottura istantanea e permanente dell’ossido di gate causata dal passaggio di uno ione pesante in presenza di alti campi elettrici (Single Event Gate Rupture, SEGR) che, a causa delle sue caratteristiche, lo pone tra gli eventi più rischiosi. In questa tesi vengono studiati diversi fattori: l’influenza del tipo di struttura di test, della polarizzazione mantenuta durante gli esperimenti e l’influenza dei raggi X. Anche in questo caso si dimostra l’esistenza di diverse forme di sinergia tra radiazioni e stress elettrico, fornendo indicazioni circa le metodologie di test e l’uso di strutture che possano fornire risultati realistici riguardo l’incidenza di questo fenomeno nei moderni transistor utilizzati per l’elettronica spaziale. In conclusione questa tesi vuole essere il primo forte contributo scientifico per lo studio degli effetti sinergici tra radiazione ionizzante e test di vita accelerati su dispositivi CMOS avanzati, da implementare in ambienti radioattivi quali lo spazio o gli esperimenti di fisica delle alte energie.

Thesis (Ph. D.)--University of California, San Diego, 2007.
Title from first page of PDF file (viewed October 3, 2007). Available via ProQuest Digital Dissertations. Vita. Includes bibliographical references (p. 256-271).

Advances in wireless technology have recently led to the potential for higher data rates and greater functionality. Wireless home and business networks and 3G and 4G cellular phone systems are promising technologies striving for market acceptance, requiring low-cost, low-power, and compact solutions. One approach to meet these demands is system-on-a-chip (SoC) integration, where RF/analog and digital circuitry reside on the same chip, creating a mixed-signal environment. Concurrently, there is tremendous incentive to utilize Si-based technologies to leverage existing fabrication and design infrastructure and the corresponding economies of scale. While the SoC approach is attractive, it presents major challenges for circuit designers, particularly in the design of monolithic voltage controlled oscillators (VCOs). VCOs are important components in the up or downconversion of RF signals in wireless transceivers. VCOs must have very low phase noise and spurious emissions, and be extremely power efficient to meet system requirements. To meet these specifications, VCOs require high-quality factor (Q) tank circuits and reduction of noise from active devices; however, the lack of high-quality monolithic inductors, along with low noise transistors in traditional Si technologies, has been a limiting factor. This thesis presents the design, characterization, and comparison of three monolithic 3-4 GHz VCOs and an integrated 5-6 GHz VCO with tunable polyphase outputs. Each VCO is designed around a differential -G_{M} core with an LC tank circuit. The circuits exploit two Si-based device technologies: Silicon Germanium (SiGe) Heterojunction Bipolar Transistors (HBTs) for a cross-coupled collectors circuit and Graded-Channel MOS (GC-MOS) transistors for a complementary (CMOS) implementation. The circuits were fabricated using the Motorola 0.4 μm CDR1 SiGe BiCMOS process, which consists of four interconnected metal layers and a thick copper (10 μm) metal bump layer for improved inductive components. The VCO implementations are targeted to meet the stringent phase noise specifications for the GSM/EGSM 3G cellular standard. The specifications state that the VCO output cannot exceed -162 dBc/Hz sideband noise at 20 MHz offset from the carrier. Simultaneously, oscillators must be designed to address other system level effects, such as feed-through of the local oscillator (LO). LO feed-through directly results in self-mixing in direct conversion receivers, which gives rise to unwanted corrupting DC offsets. Therefore, a system-level strategy is employed to avoid such issues. For example, multiplying the oscillator frequency by two or four times can help avoid self-mixing during downconversion by moving the LO out of the bandwidth of the RF front-end. Meanwhile, direct conversion or low-IF (intermediate frequency) receiver architectures utilize in-phase and quadrature (I/Q) downconversion signal recovery and image rejection. Any imbalance between the I and Q channels can result in an increase in bit-error-rate (BER) and/or decrease in the image rejection ratio (IRR). To compensate for such an imbalance, an integrated tunable polyphase filter is implemented with a VCO. Control voltages between the differential I and Q channels can be individually controlled to help compensate for I/Q mismatches. This thesis includes an introduction to design flow and layout strategies for oscillator implementations. A detailed comparison of the advantages and disadvantages of the SiGe HBTs and GC-MOS device in 3-4 GHz VCOs is presented. In addition, an overview of full-wave electromagnetic characterization of differential dual inductors is given. The oscillators are characterized for tuning range, output power, and phase noise. Finally, new measurement techniques for the 5-6 GHz VCO with a tunable polyphase filter are explored. A comparison between the time and frequency approaches is also offered.
Master of Science

Dissertação apresentada para obtenção do Grau de Doutor em Engenharia Electrotécnica e de Computadores pela Universidade Nova de Lisboa, Faculdade de Ciências e Tecnologia
Switches presenting high linearity are more and more required in switched-capacitor circuits,namely in 12 to 16 bits resolution analog-to-digital converters. The CMOS technology evolves continuously towards lower supply voltages and, simultaneously, new design techniques are necessary to fulfill the realization of switches exhibiting a high dynamic range and a distortion compatible with referred resolutions. Moreover, with the continuously downing of the sizes, the physic constraints of the technology must be considered to avoid the excessive stress of the devices when relatively high voltages are applied to the gates. New switch-linearization techniques, with high reliability, must be necessarily developed and demonstrated in CMOS integrated circuits. Also, the research of new structures of circuits with switched-capacitor is permanent. Simplified and efficient structures are mandatory, adequate to the new demands emerging from the proliferation of portable equipments, necessarily with low energy consumption while assuring high performance and multiple functions. The work reported in this Thesis comprises these two areas. The behavior of the switches under these new constraints is analyzed, being a new and original solution proposed, in order to maintain the performance. Also, proposals for the application of simpler clock and control schemes are presented, and for the use of open-loop structures and amplifiers with localfeedback. The results, obtained in laboratory or by simulation, assess the feasibility of the presented proposals.

Le transistor a base permeable est constitue d'une grille metallique enterree dans un monocristal semiconducteur. Mais pour que ce transistor deviennent interessant d'un point de vue performance, il faut que les distances entre les doigts metalliques soient inferieures qu micron (submicron). Discussion sur la faisabilite d'un tel dispositif et des techniques lithographiques permettant de le realiser

Des transistors nmos submicroniques ont ete realises et caracterises par la mesure de leurs parametres s a haute frequence afin d'evaluer les performances limites apportees par des longueurs inferieures au micron

Thesis (M.S.)--University of Wisconsin--Madison, 2002.
Typescript. eContent provider-neutral record in process. Description based on print version record. Includes bibliographical references (leaves 42-43).

One of the main concerns of modern cryptographic devices is related to the possibility of stealing the secret information, which is processed or stored inside (e.g. personal data, PIN, passwords, payment details, ...). In the scientific community many efforts have been spent in the last decades, with the purpose to develop cryptographic algorithms, which are robust enough against any attempt to detect the cryptographic key of the algorithm itself. In the last years a new class of attacks, aimed at attacking one device at the physical level, gained even more importance. Their efficacy consists in the possibility to exploit the physical emissions of the device (e.g. power consumption, light, noise, electromagnetic radiation, ...), instead that trying to break the algorithm from a mathematical point of view. This class of attacks is known as Side Channel Attacks (SCAs) and their danger resides in the fact that they allow to steal the information leaking from the device, without leaving any trace of their activity, so that the victim of the attack (e.g. the owner of a smart card) could be completely unaware of them. Many countermeasures have been presented at each design level, in order to protect electronic circuits, which are the hardware basis of any cryptographic device, against them. In this work we focus on a particular class of SCAs: Power Analysis Attacks (PAAs). PAAs are able to find correlation between the power consumption of a digital circuit and the electrically internally processed data, exploiting the fact that with the reduction of the dimensions of the commercial electronic technologies this dependance becomes even more relevant. Therefore the new challenge of the semiconductor companies is to design and manufacture devices which are proven against this class of attacks, already from a hardware point of view, in order to provide the customer with reliable and optimized products. The main contributions of this work are below summarized: Present a new concept for the design of digital cryptographic circuits, whose purpose is to increase the level of securiy of crypto-devices against hardware attacks, in particulat against PAAs. - Discuss the most known state-of-the-art security metrics and present a new methodology, as an improvement of the former ones, which should be considered in order to properly validate sub-micron cryptographic circuits. - Design a new digital standard cell library, using a commercial sub-micron technology node, which has been characterized with extensive simulations using commercial EDA tools and has been evaluated using the most common security metrics. - Define a new design flow, using the proposed standard cell library, which has been adopted for the design of a cryptographic test-chip; the design phases and the security evaluation of the test-chip are widely described and allow to prove the level of robustness of the new design style. - Discuss a new class of Power Analysis Attacks, based on the leakage coming from the static power, which is becoming predominant in scaled sub-micron technologies, and prove through extensive simulations that the most known countermeasures against PAAs are not robust enough and therefore new metrics and design styles would be necessary.

Three main analog circuit building blocks that are important for a mixed-signal system are investigated in this work. New building blocks with emphasis on power efficiency and compatibility with deep-submicron technology are proposed and experimental results from prototype integrated circuits are presented. Firstly, a 1.1GHz, 5th order, active-LC, Butterworth wideband equalizer that controls inter-symbol interference and provides anti-alias filtering for the subsequent analog to digital converter is presented. The equalizer design is based on a new series LC resonator biquad whose power efficiency is analytically shown to be better than a conventional Gm-C biquad. A prototype equalizer is fabricated in a standard 0.18μm CMOS technology. It is experimentally verified to achieve an equalization gain programmable over a 0-23dB range, 47dB SNR and -48dB IM3 while consuming 72mW of power. This corresponds to more than 7 times improvement in power efficiency over conventional Gm-C equalizers. Secondly, a load capacitance aware compensation for 3-stage amplifiers is presented. A class-AB 16W headphone driver designed using this scheme in 130nm technology is experimentally shown to handle 1pF to 22nF capacitive load while consuming as low as 1.2mW of quiescent power. It can deliver a maximum RMS power of 20mW to the load with -84.8dB THD and 92dB peak SNR, and it occupies a small area of 0.1mm2. The power consumption is reduced by about 10 times compared to drivers that can support such a wide range of capacitive loads. Thirdly, a novel approach to design of ADC in deep-submicron technology is described. The presented technique enables the usage of time-to-digital converter (TDC) in a delta-sigma modulator in a manner that takes advantage of its high timing precision while noise-shaping the error due to its limited time resolution. A prototype ADC designed based on this deep-submicron technology friendly architecture was fabricated in a 65nm digital CMOS technology. The ADC is experimentally shown to achieve 68dB dynamic range in 20MHz signal bandwidth while consuming 10.5mW of power. It is projected to reduce power and improve speed with technology scaling.

博士
國立成功大學
微電子工程研究所碩博士班
93
Solid-state image sensors, such as the CMOS image sensor (CIS) and the charge-coupled device (CCD), have been applied widely in various machines. In the past several years, a great deal of attention have been paid to the CIS for its superior advantages over CCD in areas such as lower voltage and lower power consumption, compatible with the standard CMOS logic process, and especially providing the integration solution for the SOC. Simultaneously, the CIS has been considered as a viable alternative to the CCD in many applications, such as the digital still camera, the optical mouse and the mobile phone. However, several disadvantages of the logic compatible CIS were found, for example, higher device driving current caused the higher dark signal and the white pixel, thicker backend thickness enlarged optical crosstalk and the degraded photosensitivity from using multi-dielectric films, including SiON, SiO2 and SiN. On the other hand, the pixel size is shrunk continuously for the strong demand of the higher resolution and smaller chip size. But accompany the shrinking of pixel size, several challenges were found. Two major of them are the sensitivity degradation caused by the less fill factor, and the pixel crosstalk enhancement induced by the smaller geometry. In this thesis, we propose some effective approaches to improve the pixel performance of the deep sub-micron CIS. 　　Firstly, we propose to use the thinner epitaxial (Epi) wafer to reduce the electrical crosstalk, especially for longer wavelength light. Because the light with different wavelengths generates the photoelectron at different depth in a Si substrate i.e., the longer wavelength, the deeper penetration depth is. Therefore, adopting the thinner Epi wafer can reduce the electrical crosstalk. With proper process design, the electrical crosstalk of a smaller pixel size can be good enough as the previous larger pixel size. 　　Secondly, we suggest using the thinner backend (TB) scheme to reduce the optical crosstalk as shrinking the pixel size. In order to be compatible with the CMOS logic technology, large inter-metal thickness for lower capacitance is adopted in the CIS process. However, if we scale the device horizontal dimension without thinning the vertical thickness, the optical crosstalk would be enhanced due to the oblique incident light would easily illuminate on the nearby pixel. Hence, thinning down the backend thickness is necessary while shrinking the pixel size. Furthermore, thinning down the backend thickness not only reduces the crosstalk but also suppresses the sensitivity degradation as increase of incident light angles. 　　Thirdly, we develop three advanced backend structures, i.e., Light Guide (LG), Air-Gap-Guard-Ring (AGGR) and Air-Gap-in-situ-MicroLens (AGML), to reduce the optical of the CIS. As continually shrinking the sensor pixel size and adopting multi-layer metal in deep sub-micron process, the crosstalk issue and sensitivity degradation are getting worse for the severe optical scattering. To find out more power solutions for improving the optical performance of the CIS becomes necessary. Based on the Snall’s law, using the refractive index (RI) difference between different dielectric films and the air make the light total reflection occur in the backend of the CIS, thus effectively suppressing the optical crosstalk. Consequently, by using the TB+AGML structure, the pixel size can be further downscaled to smaller geometry with good optical performance. 　　Fourthly, a novel dielectric structure by removing the shallow trench isolation (STI) from the photodiode area and then forming a deposition of SiON was proposed to improve the CIS sensitivity. In the advanced CIS technology, both silicide and borderless contact (BLC) processes have been adopted, thus the photodiode must be placed below the STI SiO2, with SiON film on its surface, in order to enhance the sensitivity. However, as the incident light passes through the dielectric film with abrupt changes of (refractive index) RI, such as low RI (1.46) / high RI (2.15) / low RI (1.46) / high RI (3.44) for ILD_SiO2 / SiON / STI_SiO2 / Si, a destructive interference occurs between these interfaces, thus degrading the sensitivity of the CIS. By using the proposed structure, experimental results show better quantum efficiency (QE) compared to conventional structure, especially illuminated at the blue light. Therefore, we show that the photodiode under Si surface would provide better spectral response than the photodiode under the STI. On the other hand, QE of the photodiode with different dielectric film thickness is simulated. We find that the SiON film is another key layer that might degrade the QE of the photodiode. Consequently, proper choice of the dielectric film structure and the thickness can result in higher quantum efficiency for CMOS image sensors. 　　Finally, we proposed an effective method to evaluate the degradation, thus a guideline has been provided for designers to prevent the performance degradation of CIS from hot carriers effect. For the active pixel sensor (APS) operated at some special conditions, hot carriers generated at the source follower (SF) transistor have been found to degrade the pixel performance such as the increase of dark signal and the decrease of operation range. We study the degradation mechanism of the pixel output signal induced by hot carriers with overall useful bias conditions. And based on the studies, an effective method was proposed to evaluate the degradation. Thus, a guideline has been provided for designers to prevent the performance degradation of APS from hot carriers.

M.TECH
With the evolution of submicron technologies such as 0.18 micron and 0.13 micron, the supply voltages have been reduced to 1.5 volts and lower. This makes it difficult to design a voltage mode CMOS circuit with high linearity and wide dynamic range. Also as signal processing extends to higher frequencies, the traditional design methods based on voltage operational amps are no longer adequate. To overcome these problems circuits operating in current mode are preferred. Various analog building blocks operating in the current mode are available. Operational Trans-Resistance Amplifier (OTRA) is one of them. OTRA is a current controlled voltage source. Both its input and output terminals are characterized by low impedance, therefore eliminating response limitations incurred by capacitive time constants. Its bandwidth is independent of closed loop voltage gain. Thus using the OTRA as the active building block various signal processing and generating circuits can be realized with more flexibility in controlling the frequencies of waveforms. The Operational Trans-Resistance Amplifier (OTRA) is though not available as a single IC but various CMOS circuit realizations are available in literature and can also be implemented using two standard CFOAs. One such CFOA that can be used is the commercially available AD844AN IC 5 manufactured by Analog Devices Inc., US. The AD844AN has current feedback architecture. In this project Operational Trans-Resistance Amplifier (OTRA) based different analog signal processing and generating circuits such as Filters, Multiphase Sinusoidal Oscillators (MSO), Voltage Controlled Oscillator (VCO) and LC oscillator based on active realization of inductor have been realized. The theoretical results have been verified through PSPICE simulations and experimental work by assembling practical circuits of the above and testing them to give near theoretical results. For practical circuits the OTRA has been realized using the AD844AN CFOA ICs manufactured by Analog Devices.

碩士
國立成功大學
微電子工程研究所碩博士班
94
Part 1 Effect of silicon surface micro-roughness and stress caused by hot DI water rinse on the electrical properties of deep-submicron CMOS transistors and MOS capacitors such as threshold voltage, saturation current, leakage current and breakdown voltage (VBD) and charge to breakdown (QBD) have been studied systematically. It shows that the hot DI water rinse can lead to micro-roughness causing the wider distribution of the saturation current as well as threshold voltage and degrading the breakdown voltage of devices. Additionally, increase of surface roughness could induce higher interface trap charge. The micro-roughness of silicon surface is evaluated by the atomic force microscope (AFM) while the density of interface trap charges is measured by the C-V measurement. Part 2 The impact of different silicide technologies on the gate oxide integrity (GOI) in the metal-oxide-semiconductor (MOS) has been studied in detail. We found that the in situ doped polysilicon results in lower breakdown voltage and more interface trap charges due to the penetration of phosphorus atoms. The implant-polysilicon was found to improve the gate oxide integrity (GOI) under the 800oC, 20 minutes furnace anneal. But the GOI become worse for higher temperature and longer anneal time due to the thermal process caused dopants diffusing into the gate oxide film results in more traps in the oxide, then degrades the gate oxide integrity.