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Опубліковано: 11 вересня 2023

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Статті в журналах з теми "SUB MICRON TECHNOLOGIES"

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DESPOTULI, ALEXANDER, and ALEXANDRA ANDREEVA. "A SHORT REVIEW ON DEEP-SUB-VOLTAGE NANOELECTRONICS AND RELATED TECHNOLOGIES." International Journal of Nanoscience 08, no. 04n05 (August 2009): 389–402. http://dx.doi.org/10.1142/s0219581x09006328.

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The decrease of energy consumption per 1 bit processing (ε) and power supply voltage (V dd ) of integrated circuits (ICs) are long-term tendencies in micro- and nanoelectronics. In this framework, deep-sub-voltage nanoelectronics (DSVN), i.e., ICs of ~1011–1012 cm-2 component densities operating near the theoretical limit of ε, is sure to find application in the next 10 years. In nanoelectronics, the demand on high-capacity capacitors of micron sizes sharply increases with a decrease of technological norms, ε and V dd . Creation of high-capacity capacitors of micron size to meet the challenge of DSVN and related technologies is considered. The necessity of developing all-solid-state impulse micron-sized supercapacitors on the basis of advanced superionic conductors (nanoionic supercapacitors) is discussed. Theoretical estimates and experimental data on prototype nanoionic supercapacitors with capacity density δC ≈ 100 μF/cm2 are presented. Future perspectives of nanoionic devices are briefly discussed.
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Yamazaki, T., K. Imai, H. Yoshida, Y. Kinoshita, and H. Suzuki. "Process integration technologies for sub-half micron BiCMOS LSls." Electrical Engineering 79, no. 5 (October 1996): 329–33. http://dx.doi.org/10.1007/bf01235873.

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3

Bude, J. D., and M. Mastrapasqua. "Impact ionization and distribution functions in sub-micron nMOSFET technologies." IEEE Electron Device Letters 16, no. 10 (October 1995): 439–41. http://dx.doi.org/10.1109/55.464810.

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4

Manolopoulos, Spyros, K. Mathieson, and R. Turchetta. "Simulation of monolithic active pixels in deep sub-micron technologies." Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 487, no. 1-2 (July 2002): 181–87. http://dx.doi.org/10.1016/s0168-9002(02)00963-4.

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5

Boyes, E. D. "LVEDS For Advanced Materials and Semiconductor Technologies." Microscopy and Microanalysis 5, S2 (August 1999): 314–15. http://dx.doi.org/10.1017/s1431927600014896.

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The need to analyze bulk samples containing features with submicron dimensions has driven revaluation of the processes controlling the interaction of electron beams with inorganic, polymer and semiconductor materials, and to development of LVEDS analysis at lower beam energies of E0 <5kV (1,2).It has previously been shown (1,2) that the physics is much as expected with the vertical penetration range (R) along the beam direction in many cases predicted quite accurately for beam energy E0 by the simple Bethe (e.g. in 3) power law with R = F(E0)5/3. These same factors are effective to varying degrees in all three dimensions. The strong dependence of the range on energy has practical importance for the identification of sub-micron particles, including to help to determine the root cause of a defect Fig. 1 is an example of the sequential analysis of the exact same sub-micron particle, with the very real potential for a processing disaster, on the surface of a silicon wafer. When this feature is analyzed with a 3kV electron beam we learn it is alumina (A12O3). The analysis comes only from the target particle and the data have a simple relationship to the chemistry and the sensitivity for the light element (O) is excellent, providing simple and direct qualitative identification of the oxide compound.
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Duruk, Alper, Ece Olcay Güneş, and Hakan Kuntman. "A new low voltage CMOS differential OTRA for sub-micron technologies." AEU - International Journal of Electronics and Communications 61, no. 5 (May 2007): 291–99. http://dx.doi.org/10.1016/j.aeue.2006.05.009.

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Kaloyeros, Alain E., and Michael A. Fury. "Chemical Vapor Deposition of Copper for Multilevel Metallization." MRS Bulletin 18, no. 6 (June 1993): 22–29. http://dx.doi.org/10.1557/s0883769400047291.

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Since the birth of integrated circuitry about thirty five years ago, microelectronics design and manufacturing technologies have evolved toward higher integration density with smaller design rules. As the semiconductor industry moves into ultra-large-scale integration (ULSI), device geometries continue to shrink into the sub-half-micron region while circuit densities increase to optimize reliability and improve performance. The resulting demands on interconnect technologies necessitate the exploitation of all development avenues: design, materials, and manufacturing.Emerging sub-half-micron technologies require multilevel metallization (MLM) design schemes that reduce interconnection lengths and lead to lower signal transmission delays and enhanced device speeds. MLM schemes also permit increased device density, due to the ability to use the third (vertical) dimension, and easier signal routing because of higher flexibility in architectural design. These schemes, in turn, demand interconnect metals that can handle the higher current densities resulting from the decreasing size of device features, without the loss of electrical and structural integrity, and deliver the sheet resistance needed to meet performance demands. They also require reliable deposition techniques to successfully fabricate the increasingly complex architectures as lateral feature sizes are scaled down more rapidly than conductor or insulator thicknesses.
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Bude, Jeff D. "Monte Carlo Simulations of Impact Ionization Feedback in MOSFET Structures." VLSI Design 8, no. 1-4 (January 1, 1998): 13–19. http://dx.doi.org/10.1155/1998/10649.

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Although impact ionization feedback is recognized as an important current multiplication mechanism, its importance as a carrier heating mechanism has been largely overlooked. This work emphasizes the inclusion of impact ionization feedback in Monte Carlo device simulations, and its implications for carrier heating in sub-micron CMOS and EEPROM technologies.
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9

Vishnoi, U., and T. G. Noll. "Area- and energy-efficient CORDIC accelerators in deep sub-micron CMOS technologies." Advances in Radio Science 10 (September 18, 2012): 207–13. http://dx.doi.org/10.5194/ars-10-207-2012.

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Abstract. The COordinate Rotate DIgital Computer (CORDIC) algorithm is a well known versatile approach and is widely applied in today's SoCs for especially but not restricted to digital communications. Dedicated CORDIC blocks can be implemented in deep sub-micron CMOS technologies at very low area and energy costs and are attractive to be used as hardware accelerators for Application Specific Instruction Processors (ASIPs). Thereby, overcoming the well known energy vs. flexibility conflict. Optimizing Global Navigation Satellite System (GNSS) receivers to reduce the hardware complexity is an important research topic at present. In such receivers CORDIC accelerators can be used for digital baseband processing (fixed-point) and in Position-Velocity-Time estimation (floating-point). A micro architecture well suited to such applications is presented. This architecture is parameterized according to the wordlengths as well as the number of iterations and can be easily extended for floating point data format. Moreover, area can be traded for throughput by partially or even fully unrolling the iterations, whereby the degree of pipelining is organized with one CORDIC iteration per cycle. From the architectural description, the macro layout can be generated fully automatically using an in-house datapath generator tool. Since the adders and shifters play an important role in optimizing the CORDIC block, they must be carefully optimized for high area and energy efficiency in the underlying technology. So, for this purpose carry-select adders and logarithmic shifters have been chosen. Device dimensioning was automatically optimized with respect to dynamic and static power, area and performance using the in-house tool. The fully sequential CORDIC block for fixed-point digital baseband processing features a wordlength of 16 bits, requires 5232 transistors, which is implemented in a 40-nm CMOS technology and occupies a silicon area of 1560 μm2 only. Maximum clock frequency from circuit simulation of extracted netlist is 768 MHz under typical, and 463 MHz under worst case technology and application corner conditions, respectively. Simulated dynamic power dissipation is 0.24 uW MHz−1 at 0.9 V; static power is 38 uW in slow corner, 65 uW in typical corner and 518 uW in fast corner, respectively. The latter can be reduced by 43% in a 40-nm CMOS technology using 0.5 V reverse-backbias. These features are compared with the results from different design styles as well as with an implementation in 28-nm CMOS technology. It is interesting that in the latter case area scales as expected, but worst case performance and energy do not scale well anymore.
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Gul, Waqas, Maitham Shams, and Dhamin Al-Khalili. "SRAM Cell Design Challenges in Modern Deep Sub-Micron Technologies: An Overview." Micromachines 13, no. 8 (August 17, 2022): 1332. http://dx.doi.org/10.3390/mi13081332.

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Microprocessors use static random-access memory (SRAM) cells in the cache memory design. As a part of the central computing component, their performance is critical. Modern system-on-chips (SoC) escalate performance pressure because only 10–15% of the transistors accounts for logic, while the remaining transistors are for the cache memory. Moreover, modern implantable, portable and wearable electronic devices rely on artificial intelligence (AI), demanding an efficient and reliable SRAM design for compute-in-memory (CIM). For performance benchmark achievements, maintaining reliability is a major concern in recent technological nodes. Specifically, battery-operated applications utilize low-supply voltages, putting the SRAM cell’s stability at risk. In modern devices, the off-state current of a transistor is becoming comparable to the on-state current. On the other hand, process variations change the transistor design parameters and eventually compromise design integrity. Furthermore, sensitive information processing, environmental conditions and charge emission from IC packaging materials undermine the SRAM cell’s reliability. FinFET-SRAMs, with aggressive scaling, have taken operation to the limit, where a minute anomaly can cause failure. This article comprehensively reviews prominent challenges to the SRAM cell design after classifying them into five distinct categories. Each category explains underlying mathematical relations followed by viable solutions.
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Дисертації з теми "SUB MICRON TECHNOLOGIES"

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Oey, James Boe-Kian 1980. "Cell-based array for deep sub-micron technologies." Thesis, Massachusetts Institute of Technology, 2003. http://hdl.handle.net/1721.1/18030.

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Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2003.
Includes bibliographical references (p. 161).
In this thesis I explore transistor topologies for high density cell-based arrays that allows for dense computation blocks, small memory cells, and strong signal drivers. This involves simulating different circuit types with HSPICE to determine ideal transistor sizes. Using Magic and the results of the HSPICE simulations, I explore transistor topologies with different ratios of nFets to pFets. An analysis on the technology shows important characteristics for digital systems and how they relate to the explored transistor topologies.
by James Boe-Kian Oey.
M.Eng.
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2

Sotiriadis, Paul Peter P. (Paul Peter Peter-Paul) 1973. "Interconnect modeling and optimization in deep sub-micron technologies." Thesis, Massachusetts Institute of Technology, 2002. http://hdl.handle.net/1721.1/29230.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2002.
Includes bibliographical references.
Interconnect will be a major bottleneck for deep sub-micron technologies in the years to come. This dissertation addresses the communication aspect from a power consumption and transmission speed perspective. A model for the energy consumption associated with data transmission through deep sub-micron technology buses is derived. The capacitive and inductive coupling between the bus lines as well as the distributed nature of the wires is taken into account. The model is used to estimate the power consumption of the bus as a function of the Transition Activity Matrix, a quantity generalizing the transition activity factors of the individual lines. An information theoretic framework has been developed to study the relation between speed (number of operations per time unit) and energy consumption per operation in the case of synchronous digital systems. The theory provides us with the fundamental minimum energy per input information bit that is required to process or communicate information at a certain rate. The minimum energy is a function of the information rate, and it is, in theory, asymptotically achievable using coding. This energy-information theory combined with the bus energy model result in the derivation of the fundamental performance limits of coding for low power in deep sub-micron buses. Although linear, block linear and differential coding schemes are favorable candidates for error correction, it is shown that they only increase power consumption in buses. Their resulting power consumption is related to structural properties of their generator matrices. In some cases the power is calculated exactly and in other cases bounds are derived.
(cont.) Both provide intuition about how to re-structure a given linear (block linear, etc.) code so that the energy is minimized within the set of all equivalent codes. A large class of nonlinear coding schemes is examined that leads to significant power reduction. This class contains all encoding schemes that have the form of connected Finite State Machines. The deep sub-micron bus energy model is used to evaluate their power reduction properties. Mathematical analysis of this class of coding schemes has led to the derivation of two coding optimization algorithms. Both algorithms derive efficient coding schemes taking into account statistical properties of the data and the particular structure of the bus. This coding design approach is generally applicable to any discrete channel with transition costs. For power reduction, a charge recycling technique appropriate for deep sub-micron buses is developed. A detailed mathematical analysis provides the theoretical limits of power reduction. It is shown that for large buses power can be reduced by a factor of two. An efficient modular circuit implementation is presented that demonstrates the practicality of the technique and its significant net power reduction. Coding for speed on the bus is introduced. This novel idea is based on the fact that coupling between the lines in a deep sub-micron bus implies that different transitions require different amounts of time to complete. By allowing only "fast" transitions to take place, we can increase the clock frequency of the bus. The combinatorial capacity of such a constrained bus ...
by Paul Peter P. Sotiriadis.
Ph.D.
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3

Xu, Hao. "Runtime Leakage Control in Deep Sub-micron CMOS Technologies." University of Cincinnati / OhioLINK, 2010. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1289235760.

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4

Henzler, Stephan. "Power management of digital circuits in deep sub-micron CMOS technologies /." [New York, NY] : Springer, 2007. http://www.gbv.de/dms/ilmenau/toc/511998031.PDF.

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SANT, LUCA. "Design of MEMS microphone front-ends in deep sub-micron CMOS technologies." Doctoral thesis, Università degli Studi di Milano-Bicocca, 2022. http://hdl.handle.net/10281/374735.

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Анотація:
I microfoni sono sempre piu' diffusi nei dispositivi elettronici che utilizziamo quotidianamente. L'importanza di una interazione piu' naturale ed immediata ha spinto l'utilizzo del riconoscimento vocale anche in prodotti a basso costo e di larghissima diffusione. Di conseguenza e' aumentata la richiesta di microfoni sempre piu' performanti, con package miniaturizzati e costi ridotti. Questa tesi, svolta presso Infineon Technologies, illustra il processo di sviluppo di un microfono ad elevate prestazioni capace di ottenere un rapporto segnale/rumore (SNR) di 72dB(A) con un livello di saturazione acustica (AOP) di 130dB SPL. Il sistema si basa su un sensore MEMS di ultima generazione unito ad un circuito di interfaccia (ASIC) riprogettato per sfruttare le peculiarita' del trasduttore. L'ASIC e' caratterizzato da un amplificatore d'ingresso di tipo current-feedback che permette di minimizzare il rapporto segnale/rumore e da un convertirore analogico/digitale riconfigurabile per adattare il consumo di potenza alle prestazioni richieste dal sistema.
Microphone systems are extremely widespread in today's consumer electronics, the urge of a more natural interaction with our devices has heavily pushed voice recognition even in portable devices, forcing industry to create suitable products. This thesis describes the development of a new digital read-out ASIC that paired with Infineon Technologies latest sealed-dual membrane (SDM) MEMS transducer forms a prototype for a new high-end microphone product. State-of-the-art noise performance is achieved thanks to significant optimizations both on the MEMS as well as on the ASIC side. The ASIC features an unconventional read-out amplifier based on a power-scalable current-feedback architecture as well as a reconfigurable ΔΣ modulator allowing to trade-off signal-to-noise ratio (SNR) versus power consumption. The microphone system achieves an SNR of 72dB(A) supporting an acoustical overload point (AOP) of 130dB SPL. This represents a significant improvement to current state-of-the-art digital microphones.
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Fuard, david. "Etude et caractérisation avancées des procédés plasma pour les technologies sub - 0.1 µm." Phd thesis, Université d'Orléans, 2003. http://tel.archives-ouvertes.fr/tel-00006610.

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Les interconnexions des circuits intégrés sub-0.25µm nécessitent l'intégration d'isolants «low-K» à plus faible permittivité diélectrique que SiO2 (~ 4.4) tel que le SiLK™ (~ 2.65), un matériau organique prometteur. Mais sa gravure plasma conduit à l'obtention de structures en forme de tonneau («bow»), alors que les profils gravés doivent rester anisotropes pour les étapes ultérieures d'intégration. Afin de réduire le bow, cette étude montre que la passivation des flancs des structures gravées est nécessaire, et fortement corrélée à la dégradation («graphitisation») du SiLK et à la présence de résidus carbonés peu volatils dans le plasma. La présence de sources carbonées autres que le SiLK™ permet aussi d'améliorer la passivation. L'étude du phénomène à l'origine du bow montre enfin que les charges électrostatiques jouent un rôle majoritaire dans la déflexion des ions sur les flancs. Ces résultats intéressent également tous les low-Ks à faible seuil de gravure ionique réactive.
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7

Greenup, Phillip John. "Development of Novel Technologies for Improved Natural Illumination of High Rise Office Buildings." Thesis, Queensland University of Technology, 2004. https://eprints.qut.edu.au/15936/1/Philip_Greenup_Thesis.pdf.

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Effective daylighting can substantially reduce the energy use and greenhouse gas emissions of commercial buildings. Daylight is also healthy for building occupants, and contributes to occupant satisfaction. When productivity improvements are considered, effective daylighting is also highly attractive financially. However, successful daylighting of sub-tropical buildings is a very difficult task, due to high direct irradiances and excessive solar shading. A device was created that combined effective solar shading and efficient daylight redirection. The micro-light guiding shade panel achieves all objectives of an optimal daylighting device placed on the façade of a sub-tropical, high rise office building. Its design is based on the principles of non-imaging optics. This provides highly efficient designs offering control over delivered illumination, within the constraints of the second law of thermodynamics. Micro-light guiding shade panels were constructed and installed on a test building. The tested devices delivered daylight deep into the building under all conditions. Some glare was experienced with a poorly chosen translucent material. Glare was eliminated by replacing this material. Construction of the panels could be improved by application of mass-manufacturing techniques including metal pressing. For the micro-light guiding shade panel to be utilised to its full potential, building designers must understand its impact on building performance early in the design process. Thus, the device must be modelled with lighting simulation software currently in use by building design firms. The device was successfully modelled by the RADIANCE lighting simulator. RADIANCE predictions compared well with measurements, providing bias generally less than 10%. Simulations greatly aided further development of the micro-light guiding shade panel. Several new RADIANCE algorithms were developed to improve daylight simulation in general.
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Greenup, Phillip John. "Development of Novel Technologies for Improved Natural Illumination of High Rise Office Buildings." Queensland University of Technology, 2004. http://eprints.qut.edu.au/15936/.

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Анотація:
Effective daylighting can substantially reduce the energy use and greenhouse gas emissions of commercial buildings. Daylight is also healthy for building occupants, and contributes to occupant satisfaction. When productivity improvements are considered, effective daylighting is also highly attractive financially. However, successful daylighting of sub-tropical buildings is a very difficult task, due to high direct irradiances and excessive solar shading. A device was created that combined effective solar shading and efficient daylight redirection. The micro-light guiding shade panel achieves all objectives of an optimal daylighting device placed on the façade of a sub-tropical, high rise office building. Its design is based on the principles of non-imaging optics. This provides highly efficient designs offering control over delivered illumination, within the constraints of the second law of thermodynamics. Micro-light guiding shade panels were constructed and installed on a test building. The tested devices delivered daylight deep into the building under all conditions. Some glare was experienced with a poorly chosen translucent material. Glare was eliminated by replacing this material. Construction of the panels could be improved by application of mass-manufacturing techniques including metal pressing. For the micro-light guiding shade panel to be utilised to its full potential, building designers must understand its impact on building performance early in the design process. Thus, the device must be modelled with lighting simulation software currently in use by building design firms. The device was successfully modelled by the RADIANCE lighting simulator. RADIANCE predictions compared well with measurements, providing bias generally less than 10%. Simulations greatly aided further development of the micro-light guiding shade panel. Several new RADIANCE algorithms were developed to improve daylight simulation in general.
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9

Ille, Adrien. "Fiabilité des oxydes de grille ultra-minces sous décharges électrostatiques dans les technologies CMOS fortement sub-microniques." Phd thesis, Université de Provence - Aix-Marseille I, 2008. http://tel.archives-ouvertes.fr/tel-00407545.

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Les décharges électrostatiques (ESD) constituent un problème majeur de fiabilité pour les entreprises de semi-conducteurs. Pour enrayer les défauts générés par les ESD sur les circuits intégrés (ICs), des éléments de protection sont implantés directement dans les puces. La constante poussée de l'intégration des circuits a pour conséquence la réduction des dimensions des cellules technologiques élémentaires ainsi que l'accroissement du nombre d'applications supportées par les ICs. Les conditions restrictives imposées par les procédés technologiques et par la complexité croissante des systèmes entraînent un défi considérablement accru pour le développement de produits robustes aux ESD. Dans ce travail de recherche, le problème émergeant des défaillances des couches d'oxydes minces d'épaisseur Tox = 8 à 1.1nm sous contraintes ESD est adressé dans les technologies CMOS les plus avancées, par une contribution à la compréhension des mécanismes de dégradation de la fiabilité du diélectrique et des dispositifs sous contraintes ESD. Une nouvelle approche de caractérisation des oxydes minces sous des stress à pulses ultra-courts (20 ns) est décrite jusqu'à la modélisation complète de la dépendance temporelle du claquage du diélectrique. Basé sur un ensemble cohérent de modélisations, une nouvelle méthodologie est proposée pour ajuster la détermination de la fenêtre ESD de façon mieux adaptée aux intervalles de tension et d'épaisseur d'oxyde de grille pour l'ingénierie des concepts de protection. Ceci a permis d'améliorer la prise en compte des problèmes ESD pour une meilleure fiabilité et robustesse des produits conçus en technologies CMOS fortement sub-microniques vis-à-vis des décharges électrostatiques.
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10

Fleury, Dominique. "Contribution à l'étude expérimentale du transport dans les transistors de dimensions déca-nanométriques des technologies CMOS sub-45nm." Phd thesis, Grenoble INPG, 2009. http://tel.archives-ouvertes.fr/tel-00461948.

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Анотація:
La miniaturisation des composants électroniques qui permet aujourd'hui une intégration à grande échelle a été possible grâce aux innovations des procédés de fabrication. Ces modifications affectent profondément le comportement électrique des transistors MOS lorsque la longueur de grille devient inférieure à 100nm, altérant notre compréhension physique de ce dispositif. Ce travail de thèse se situe dans le domaine de l'étude des performances des transistors fabriqués dans les filières avancées (technologies sub-45nm) et l'analyse de leur réponse électrique. Il propose d'améliorer les méthodologies existantes et apporte de nouvelles techniques d'extraction qui permettent une analyse des paramètres électriques valide dans un environnement industriel, sur des transistors courts. L'utilisation des ces nouvelles techniques permet une compréhension physique plus juste, utile pour prédire les performances des technologies futures.
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Книги з теми "SUB MICRON TECHNOLOGIES"

1

Power management of digital circuits in deep sub-micron CMOS technologies. [Dordrecht]: Springer, 2007.

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2

Charles, Miller. Microcomputer and LAN security =: La sécurité des micro-ordinateurs et des réseaux locaux. Hull, Qué: Minister of Government Services Canada = Ministre des services gouvernementaux Canada, 1993.

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3

Henzler, Stephan. Power Management of Digital Circuits in Deep Sub-Micron CMOS Technologies. Henzler Stephan, 2010.

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4

Power Management of Digital Circuits in Deep Sub-Micron CMOS Technologies. Springer Netherlands, 2006. http://dx.doi.org/10.1007/1-4020-5081-x.

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5

Henzler, Stephan. Power Management of Digital Circuits in Deep Sub-Micron CMOS Technologies. Springer, 2006.

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6

Henzler, Stephan. Power Management of Digital Circuits in Deep Sub-Micron CMOS Technologies. Springer, 2007.

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Частини книг з теми "SUB MICRON TECHNOLOGIES"

1

Packan, P. "Simulating Deep Sub-Micron Technologies: An Industrial Perspective." In Simulation of Semiconductor Devices and Processes, 34–41. Vienna: Springer Vienna, 1995. http://dx.doi.org/10.1007/978-3-7091-6619-2_8.

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2

Ye, Yan, and Lin Sen Chen. "Light Guide Plate Based on Sub-Micron Gratings." In Optics Design and Precision Manufacturing Technologies, 1061–65. Stafa: Trans Tech Publications Ltd., 2007. http://dx.doi.org/10.4028/0-87849-458-8.1061.

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Jose, Philip C., S. Karthikeyan, K. Batri, and S. Sivanantham. "An Efficient Algorithm for Tracing Minimum Leakage Current Vector in Deep-Sub Micron Circuits." In Advanced Computing and Communication Technologies, 59–69. Singapore: Springer Singapore, 2016. http://dx.doi.org/10.1007/978-981-10-1023-1_6.

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Ting, Chia Jen, Hung Yin Tsai, and Chang Pin Chou. "Fabrication of Large-Area Imprint Mold with High-Aspect-Ratio Nanotip Arrays of Sub-Micron Diameter." In Optics Design and Precision Manufacturing Technologies, 607–12. Stafa: Trans Tech Publications Ltd., 2007. http://dx.doi.org/10.4028/0-87849-458-8.607.

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Javaheri, Reza, and Reza Sedaghat. "A Novel Delay Fault Testing Methodology for Resistive Faults in Deep Sub-micron Technologies." In Communications in Computer and Information Science, 653–60. Berlin, Heidelberg: Springer Berlin Heidelberg, 2008. http://dx.doi.org/10.1007/978-3-540-89985-3_80.

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van Gurp, J. F. C., Marcel Tichem, and U. Staufer. "Design, Fabrication and Testing of Assembly Features for Enabling Sub-micron Accurate Passive Alignment of Photonic Chips on a Silicon Optical Bench." In Precision Assembly Technologies and Systems, 17–27. Berlin, Heidelberg: Springer Berlin Heidelberg, 2012. http://dx.doi.org/10.1007/978-3-642-28163-1_3.

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Herkersdorf, Andreas, Michael Engel, Michael Glaß, Jörg Henkel, Veit B. Kleeberger, Johannes M. Kühn, Peter Marwedel, et al. "RAP Model—Enabling Cross-Layer Analysis and Optimization for System-on-Chip Resilience." In Dependable Embedded Systems, 1–27. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-52017-5_1.

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AbstractThe Resilience Articulation Point (RAP) model aims to provision a probabilistic fault abstraction and error propagation concept for various forms of variability related faults in deep sub-micron CMOS technologies at the semiconductor material or device levels. RAP assumes that each of such physical faults will eventually manifest as a single- or multi-bit binary signal inversion or out-of-specification delay in a signal transition between bit values. When probabilistic error functions for specific fault origins are known at the bit or signal level, knowledge about the unit of design and its environment allow the transformation of the bit-related error functions into characteristic higher layer representations, such as error functions for data words, finite state machine (FSM) states, IP macro-interfaces, or software variables. Thus, design concerns can be investigated at higher abstraction layers without the necessity to further consider the full details of lower levels of design. This chapter introduces the ideas of RAP based on examples of particle strike, noise and voltage drop induced bit errors in SRAM cells. Furthermore, we show by different examples how probabilistic bit flips are systematically abstracted and propagated towards instruction and data vulnerability at MPSoC architecture level, and how RAP can be applied for dynamic testing and application-level optimizations in an autonomous robot scenario.
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Reczek, W., and H. Terletzki. "Zuverlässigkeitsaspekte Dynamischer Speicher in Sub-Micron CMOS Technologie." In Mikroelektronik 89, 267–72. Vienna: Springer Vienna, 1989. http://dx.doi.org/10.1007/978-3-7091-9073-9_38.

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Yang, Xiaoliang, Xuequan Wang, Zhe Pan, Jie Liu, and Jiandong Luo. "Preliminary Application of CT Technology in Non-destructive Testing of Nuclear Fuel Elements." In Springer Proceedings in Physics, 98–106. Singapore: Springer Nature Singapore, 2023. http://dx.doi.org/10.1007/978-981-99-1023-6_10.

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AbstractWith the emergence of various novel fuel elements, traditional X-ray test technologies refer to national standards that have gradually been unable to meet the non-destructive testing (NDT) requirements for these novel fuel elements. As a new NDT technology, industrial computed tomography (CT) has great potential for NDT of nuclear fuel elements. In this paper, through a personalized transformation of self-developed X-ray equipment, we carried out CT scanning imaging experiments up to more than 400 kV on pellet-shell gap in rod-shaped fuel elements, a high-density annular component, and a tungsten-based workpiece. Not only that, after three-dimensional reconstruction and image analysis, it was found that sub-millimeter internal void defects could be detected. Furthermore, size measurements were carried out through image analysis which achieved a relative error of 5%. A conservative conclusion can be drawn from this research: industrial CT, including but not limited to micro-CT, high-energy X-ray CT, etc., has an optimistic future in testing internal defects and measuring internal dimensions of novel fuel elements.
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Behjati, Mohammadreza, and John Cosmas. "Self-Organizing Network Solutions." In Advances in Wireless Technologies and Telecommunication, 241–53. IGI Global, 2017. http://dx.doi.org/10.4018/978-1-5225-2342-0.ch011.

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Quality of service (QoS) and network capacity are being insisted as the two dominant factors for the utmost network satisfaction within any mobile network contracts. On the other hand, the heterogeneous network (HetNets), which are constructed based on sub-network layers' cooperation between macrocell and shorter-range applications like micro, femto and relay nodes, are also introduced as an open door to the recent researches towards the desired network satisfaction for the recently upgraded networks like LTE-Advanced (LTE-A). Nevertheless, since any network cooperation is expected to include a number of challenges; this cooperation is not excluded of dealing with degrading effects, such as interference, among the sub-network elements. This chapter presents a detailed discussion in self-organizing network (SON) methodology, as a novel solution to deal with network challenges, e.g. inter-cell interference coordination (ICIC), mobility, power control, etc. to improve the network quality and capacity.
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Тези доповідей конференцій з теми "SUB MICRON TECHNOLOGIES"

1

Krishna, R. S. S. M. R., and Ashis Kumar Mal. "Performance analysis of parallel adders in sub-micron and deep sub-micron technologies." In 2016 International Conference on Microelectronics, Computing and Communications (MicroCom). IEEE, 2016. http://dx.doi.org/10.1109/microcom.2016.7522464.

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Booth, Heather. "Techniques and Applications of Laser Micro-Processing at the Micron and Sub-Micron Level." In Photonic Applications Systems Technologies Conference. Washington, D.C.: OSA, 2006. http://dx.doi.org/10.1364/phast.2006.pwb2.

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Chueng, Kwang-Ting, Sujit Dey, Mike Rodgers, and Kaushik Roy. "Test challenges for deep sub-micron technologies." In the 37th conference. New York, New York, USA: ACM Press, 2000. http://dx.doi.org/10.1145/337292.337353.

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Liou, Fu-Tai. "Manufacturing challenges for sub-half-micron technologies." In Microelectronic Manufacturing '95, edited by Anant G. Sabnis and Ivo J. Raaijmakers. SPIE, 1995. http://dx.doi.org/10.1117/12.221320.

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Liou, Fu-Tai. "Manufacturing challenges for sub-half-micron technologies." In Microelectronic Manufacturing '95. SPIE, 1995. http://dx.doi.org/10.1117/12.221435.

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Liou, Fu-Tai. "Manufacturing challenges for sub-half micron technologies." In Microelectronic Manufacturing '95, edited by Ih-Chin Chen, Girish A. Dixit, Trung T. Doan, and Nobuo Sasaki. SPIE, 1995. http://dx.doi.org/10.1117/12.221147.

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Liou, Fu-Tai. "Manufacturing challenges for sub-half micron technologies." In Microelectronic Manufacturing '95, edited by John K. Lowell, Ray T. Chen, and Jagdish P. Mathur. SPIE, 1995. http://dx.doi.org/10.1117/12.221210.

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Kittl, Jorge A., Michael A. Gribelyuk, Donald Miles, Chih-Ping Chao, Mark Rodder, Qi-Zhong Hong, Hong Yang, Sunil Hattangady, and Ning Yu. "Salicide Technologies for Deep-Sub-Micron-CMOS." In 1998 International Conference on Solid State Devices and Materials. The Japan Society of Applied Physics, 1998. http://dx.doi.org/10.7567/ssdm.1998.a-7-1.

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Becht, J. G. M., B. A. Bauer, P. J. van der Put, J. Schoonman, and B. Scarlett. "Laser Excited Synthesis Of Sub-Micron Powders." In Laser Technologies in Industry. SPIE, 1988. http://dx.doi.org/10.1117/12.968919.

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Fino, Maria. "Modeling High Frequency VCOs for Sub-micron Technologies." In 2006 International Caribbean Conference on Devices, Circuits and Systems. IEEE, 2006. http://dx.doi.org/10.1109/iccdcs.2006.250879.

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Звіти організацій з теми "SUB MICRON TECHNOLOGIES"

1

Coyner, Kelley, and Jason Bittner. Automated Vehicles and Infrastructure Enablers: Electrification. 400 Commonwealth Drive, Warrendale, PA, United States: SAE International, December 2022. http://dx.doi.org/10.4271/epr2022029.

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<div class="section abstract"><div class="htmlview paragraph">Highly automated vehicles are being developed alongside a variety of novel, disruptive technologies and a global focus on reducing greenhouse gas emissions from transportation. ADS can reduce emissions and improve fuel efficiency for vehicles powered by traditional internal combustion engines. Electric motors can further raise the bar for both those areas, especially if the power used to charge an electric vehicle is generated from renewable sources. However, implementing electrified AVs requires a viable charging infrastructure. </div><div class="htmlview paragraph"><b>Automated Vehicles and Infrastructure Enablers: Electrification</b> covers issues concerning infrastructure and the electrification of all forms of vehicles: heavy-duty vehicles like trucks and buses, light-duty vehicles like cars and vans, micro-mobility, and new form factors. </div><div class="htmlview paragraph"><a href="https://www.sae.org/publications/edge-research-reports" target="_blank">Click here to access the full SAE EDGE</a><sup>TM</sup><a href="https://www.sae.org/publications/edge-research-reports" target="_blank"> Research Report portfolio.</a></div></div>
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