Дисертації з теми "Space exploration systems"
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Künzli, Simon. "Efficient design space exploration for embedded systems /." Aachen : Shaker Verlag, 2006. http://e-collection.ethbib.ethz.ch/show?type=diss&nr=16589.
Повний текст джерелаÖzlük, Ali Cemal. "Design Space Exploration for Building Automation Systems." Doctoral thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2013. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-130600.
Повний текст джерелаArney, Dale Curtis. "Rule-based graph theory to enable exploration of the space system architecture design space." Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/44840.
Повний текст джерелаWatkinson, Emily Jane. "Space nuclear power systems : enabling innovative space science and exploration missions." Thesis, University of Leicester, 2017. http://hdl.handle.net/2381/40461.
Повний текст джерелаXypolitidis, Benard, and Rudin Shabani. "Architectural Design Space Exploration of Heterogeneous Manycores." Thesis, Högskolan i Halmstad, Akademin för informationsteknologi, 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:hh:diva-29528.
Повний текст джерелаJoshi, Prachi. "Design Space Exploration for Embedded Systems in Automotives." Diss., Virginia Tech, 2018. http://hdl.handle.net/10919/82839.
Повний текст джерелаPh. D.
Sanchez, Net Marc. "Support of latency-sensitive space exploration applications in future space communication systems." Thesis, Massachusetts Institute of Technology, 2017. http://hdl.handle.net/1721.1/112458.
Повний текст джерелаCataloged from PDF version of thesis.
Includes bibliographical references (pages 283-300).
Latency, understood as the total time it takes for data acquired by a remote platform (e.g. satellite, rover, astronaut) to be delivered to the final user in an actionable format, is a primary requirement for several near Earth and deep space exploration activities. Some applications such as real-time voice and videoconferencing can only be satisfied by providing continuous communications links to the remote platform and enforcing hard latency requirements on the system. In contrast, other space exploration applications set latency requirements because their data's scientific value is dependent on the timeliness with which it is delivered to the final user. These applications, henceforth termed latency-sensitive, are the main focus of this thesis, as they typically require large amounts of data to be returned to Earth in a timely manner. To understand how current space communication systems induce latency, the concept of network centrality is first introduced. It provides a systematic process for quantifying the relative importance of heterogeneous latency contributors, ranking them, and rapidly identifying bottlenecks when parts of the communication infrastructure are modified. Then, a custom-designed centrality measure is integrated within the system architecture synthesis process. It serves as a heuristic function that prioritizes parts of the system for further in-depth analysis and renders the problem of analyzing end-to-end latency requirements manageable. The thesis includes two primary case studies to demonstrate the usefulness of the proposed approach. The first one focuses on return of satellite-based observations for accurate weather forecasting, particularly how latency limits the amount of data available for assimilation at weather prediction centers. On the other hand, the second case study explores how human science operations on the surface of Mars dictate the end-to-end latency requirement that the infrastructure between Mars and Earth has to satisfy. In the first case study, return of satellite observations for weather prediction during the 2020-2030 decade is analyzed based on future weather satellite programs. Recommendations on how to implement their ground segment are also presented as a function of cost, risk and weather prediction spatial resolution. This case study also serves as proof of concept for the proposed centrality measure, as ranking of latency contributors and network implementations can be compared to current and proposed systems such as JPSS' Common Ground Infrastructure and NPOESS' SafetyNet. The second case study focuses on supporting human science exploration activities on the surface of Mars during the 2040's. It includes astronaut activity modeling, quantification of Mars Proximity and Mars-to-Earth link bandwidth requirements, Mars relay sizing and ground infrastructure costing as a function of latency requirements, as well as benchmarking of new technologies such as optical communications over deep space links. Results indicate that levying tight latency requirements on the network that support human exploration activities at Mars is unnecessary to conduct effective science and incurs in significant cost for the Mars Relay Network, especially when no optical technology is present in the system. When optical communications are indeed present, mass savings for the relay system are also possible, albeit trading latency vs. infrastructure costs is less effective and highly dependent on the performance of the deep space optical link.
by Marc Sanchez Net.
Ph. D.
Rabbah, Rodric Michel. "Design Space Exploration and Optimization of Embedded Memory Systems." Diss., Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/11605.
Повний текст джерелаKünzli, Simon [Verfasser]. "Efficient Design Space Exploration for Embedded Systems / Simon Künzli." Aachen : Shaker, 2006. http://d-nb.info/1170533213/34.
Повний текст джерелаSharma, Jonathan. "STASE: set theory-influenced architecture space exploration." Diss., Georgia Institute of Technology, 2014. http://hdl.handle.net/1853/52330.
Повний текст джерелаKernstine, Kemp H. "Design space exploration of stochastic system-of-systems simulations using adaptive sequential experiments." Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/44799.
Повний текст джерелаWessen, Randii. "Market-based systems for solving space exploration resource allocation problems." Thesis, University of South Wales, 2002. https://pure.southwales.ac.uk/en/studentthesis/marketbased-systems-for-solving-space-exploration-resource-allocation-problems(074a1185-dcb1-4e7d-b771-988b34529722).html.
Повний текст джерелаHamann, Arne. "Iterative design space exploration and robustness optimization for embedded systems." Göttingen Cuvillier, 2008. http://d-nb.info/992301777/04.
Повний текст джерелаTierno, Antonio. "Automatic Design Space Exploration of Fault-tolerant Embedded Systems Architectures." Doctoral thesis, Università degli studi di Trento, 2023. https://hdl.handle.net/11572/364571.
Повний текст джерелаLa, Tour Paul A. (Paul Alexis). "Combining tradespace exploration with system dynamics to explore future space architectures." Thesis, Massachusetts Institute of Technology, 2016. http://hdl.handle.net/1721.1/106593.
Повний текст джерелаSome pages printed landscape orientation. Cataloged from PDF version of thesis.
Includes bibliographical references (pages 342-351).
This work proposes a merger of Tradespace Exploration with System Dynamics modeling techniques in a complementary approach. It tests the value of this mixed method for modeling the multiplicity of inputs and complexity of feedback loops that affect the cost, schedule and performance of satellite constellations within the Department of Defense. The resulting simulation enables direct comparison of the effect of changing architectural design points and policy choices with respect to satellite acquisitions and fielding. A generation-over-generation examination of policy choices is made possible through the application of soft systems modeling of experience and learning effects. The resulting model enables examination of possible futures given variations in assumptions about both internal and external forces on a satellite production pipeline. This thesis performs a policy analysis examining the current path of the Global Positioning System acquisition and compares it to equivalent position navigation and timing capability delivered through a variety of disaggregated options while varying: design lives, production quantities, non-recurring engineering and time between generations. The extensibility of this technique is investigated by adapting the model to the mission area of Weather and Climate Sensing. This thesis then performs a policy analysis examining different disaggregated approaches for the Joint Polar Satellite, focusing on the impact of complexity. Discussion of factors such as design choices, context variables, tuning variables, model execution and construction is also included.
by Paul A. La Tour.
Ph. D. in Engineering Systems
Jones, Adam T. (Adam Thomas). "Design space exploration and optimization using modern ship design tools." Thesis, Massachusetts Institute of Technology, 2014. http://hdl.handle.net/1721.1/92124.
Повний текст джерелаThesis: Nav. E., Massachusetts Institute of Technology, Department of Mechanical Engineering, 2014.
Cataloged from PDF version of thesis.
Includes bibliographical references (pages 163-164).
Modern Naval Architects use a variety of computer design tools to explore feasible options for clean sheet ship designs. Under the Naval Sea Systems Command (NAVSEA), the Naval Surface Warfare Center, Carderock Division (NSWCCD) has created computer tools for ship design and analysis purposes. This paper presents an overview of some of these tools, specifically the Advanced Ship and Submarine Evaluation Tool (ASSET) version 6.3 and the Integrated Hull Design Environment (IHDE). This paper provides a detailed explanation of a ship design using these advanced tools and presents methods for optimizing the performance of the hullform, the selection of engines for fuel efficiency, and the loading of engines for fuel efficiency. The detailed ship design explores the design space given a set of specific requirements for a cruiser-type naval vessel. The hullform optimization technique reduces a ships residual resistance by using both ASSET and IHDE in a Design of Experiments (DoE) approach to reaching an optimum solution. The paper will provide a detailed example resulting in a 12% reduction in total ship drag by implementing this technique on a previously designed hullform. The reduction of drag results in a proportional reduction in the amount of fuel used to push the ship through the water. The engine selection optimization technique uses MATLAB to calculate the ideal engines to use for fuel minimization. For a given speed-time or power-time profile, the code will evaluate hundreds of combinations of engines and provide the optimum engine combination and engine loading for minimizing the total fuel consumption. This optimization has the potential to reduce fuel consumption of current naval warships by upwards of 30%.
by Adam T. Jones.
S.M.
Nav. E.
Oliveira, Marcio Ferreira da Silva. "Model driven engineering methodology for design space exploration of embedded systems." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2013. http://hdl.handle.net/10183/102694.
Повний текст джерелаAtualmente dispositivos contendo hardware e software são encontrados em todos os lugares. Estes dispositivos prestam suporte a uma varieadade de domínios, como telecomunicações, automotivo e outros. Eles são chamados “sistemas embarcados”, pois são sistemas de processamento montados dentro de produtos, cujo sistema de processamento não faz parte da funcionalidade principal do produto. O acréscimo de funções nestes sistemas implica no aumento da complexidade de seu projeto, o qual deve ser adequadamente gerenciado, pois além de requisitos rigorosos em relação à dissipação de potência, desempenho e custos, a pressão sobre o prazo para introdução de um produto no mercado também dificulta seu projeto. Exploração do espaço de projeto (DSE) é a atividade sistemática de gerar e avaliar alternativas de projetos, com o objetivo de otimizar suas propriedades. No desenvolvimento de sistemas embarcados, especialmente em Projeto Baseado em Plataformas (PBD), metodologias de DSE atuais são desafiadas pelo crescimento do número de decisões de projeto, o qual implica na explosão da combinação de alternativas. Porém, somente algumas destas resultam em projetos que atedem os requisitos nãofuncionais. Além disso, as decisões influenciam umas às outras, de forma que a ordem em que estas são tomadas alteram a implementação final do sistema. Outro desafio é o balanço entre flexibilidade da metodologia e seu desempenho, pois métodos globais de otimização são flexíveis, mas apresentam baixo desempenho. Já heurísticas especialmente desenvolvidas para o cenário de DSE em questão apresentam melhor desempenho, porém dificilmente são aplicáveis a diferentes cenários. Com o intuito de superar os desafios é proposta uma metodologia de projeto dirigido por modelos (MDE) adquada para DSE. Um metamodelo do domínio de DSE é definido para representar conceitos como espaço de projeto, métodos de avaliação e restrições. O metamodelo também representa diferentes problemas de DSE aprimorando a flexibilidade da metodologia. Regras de transformações de modelos implementam as regras de DSE, as quais são utilizadas para restringir e guiar a geração de projetos alternativos. Restringindo-se ao mapeamento entre camadas no PBD é proposta uma abstração para representar o espaço de projeto. Ela representa múltiplas decisões de projeto envolvidas no mapeamento como um único problema de DSE. Esta representação é adequada para a implementação em ferramentas automática de DSE e pode beneficiar o processo de DSE com uma abordagem de MDE, aprimorando a especificação de cenários de DSE e sua integração no processo de desenvolvimento.
Nowadays we are surrounded by devices containing hardware and software components. These devices support a wide spectrum of different domains, such as telecommunication, avionics, automobile, and others. They are found anywhere, and so they are called Embedded Systems, as they are information processing systems embedded into enclosing products, where the processing system is not the main functionality of the product. The ever growing complexity in modern embedded systems requires the utilization of more components to implement the functions of a single system. Such an increasing functionality leads to a growth in the design complexity, which must be managed properly, because besides stringent requirements regarding power, performance and cost, also time-to-market hinders the design of embedded systems. Design Space Exploration (DSE) is the systematic generation and evaluation of design alternatives, in order to optimize system properties and fulfill requirements. In embedded system development, specifically in Platform-Based Design (PBD), current DSE methodologies are challenged by the increasing number of design decisions at multiple abstraction levels, which leads to an explosion of combination of alternatives. However, only a reduced number of these alternatives leads to feasible designs, which fulfill non-functional requirements. Moreover, each design decision influences subsequent decisions and system properties, hence there are inter-dependencies between design decisions, so that the order decisions are made matters to the final system implementation. Furthermore, there is a trade-off between heuristics for specific DSE, which improves the optimization results, and global optimizers, which improve the flexibility to be applied in different DSE scenarios. In order to overcome the identified challenges an MDE methodology for DSE is proposed. For this methodology a DSE Domain metamodel is proposed to represent relevant DSE concepts such as design space, design alternatives, evaluation method, constraints and others. Moreover, this metamodel represents different DSE problems, improving the flexibility of the proposed framework. Model transformations are used to implement DSE rules, which are used to constrain, guide, and generate design candidates. Focusing on the mapping between layers in a PBD approach, a novel design space abstraction is provided to represent multiple design decisions involved in the mapping as a single DSE problem. This abstraction is based on Categorical Graph Product, decoupling the exploration algorithm from the design space and being well suited to be implemented in automatic exploration tools. Upon this abstraction, the DSE method can benefit from the MDE methodology, opening new optimization opportunities, and improving the DSE integration into the development process and specification of DSE scenarios.
Holschuh, Bradley Thomas. "Space exploration challenges : characterization and enhancement of space suit mobility and planetary protection policy analysis." Thesis, Massachusetts Institute of Technology, 2010. http://hdl.handle.net/1721.1/62036.
Повний текст джерелаThis electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Cataloged from student-submitted PDF version of thesis.
Includes bibliographical references (p. 189-193).
This thesis addresses two challenges associated with advanced space and planetary exploration: characterizing and improving the mobility of current and future gas pressurized space suits; and developing effective domestic Planetary Protection policies for the emerging private space industry. Gas-pressurized space suits are known to be highly resistive to astronaut movement. As NASA seeks to return to planetary exploration, there is a critical need to improve full body space suit mobility for planetary exploration. Volume effects (the torque required to displace gas due to internal volume change during movement) and structural effects (the additional torque required to bend the suit materials in their pressurized state) are cited as the primary contributors to suit rigidity. Constant volume soft joints have become the design goal of space suit engineers, and simple joints like the elbow are believed to have nearly achieved such performance. However, more complex joints like the shoulder and waist have not yet achieved comparable optimization. As a result, it is hypothesized that joints like the shoulder and waist introduce a third, and not well studied, contributor to space suit rigidity: pressure effects (the additional work required to compress gas in the closed operating volume of the suit during movement). This thesis quantifies the individual contributors to space suit rigidity through modeling and experimentation. An Extravehicular Mobility Unit (EMU) space suit arm was mounted in a -30kPa hypobaric chamber, and both volume and torque measurements were taken versus elbow angle. The arm was tested with both open and closed operating volumes to determine the contribution of pressure effects to total elbow rigidity. These tests were then repeated using a full EMU volume to determine the actual impact of elbow pressure effects on rigidity when connected to the full suit. In both cases, structural and volume effects were found to be primary contributors to elbow joint rigidity, with structural effects dominating at low flexion angles and volume effects dominating at high flexion angles; pressure effects were detected in the tests that used only the volume of the arm, but were found to be a secondary contributor to total rigidity (on average < 5%). These pressure effects were not detected in the tests that used the volume representative of a full EMU. Unexpected structural effects behavior was also measured at high (> 75°) flexion angles, suggesting that the underlying mechanisms of these effects are not yet fully understood, and that current models predicting structural effects behavior do not fully represent the actual mechanisms at work. The detection of pressure effects in the well-optimized elbow joint, even if only in a limited volume, suggests that these effects may prove significant for sub-optimized, larger, multi-axis space suit joints. A novel, fast-acting pressure control system, developed in response to these findings, was found to be capable of mitigating pressure spikes due to volume change (and thus, pressure effects). Implementation of a similar system in future space suit designs could lead to improvements in overall suit mobility. A second study, which focused on the implications of the development of the US private space industry on domestic Planetary Protection policy, is also presented. As signatories of the 1967 Treaty on Principles Governing the Activities of States in the Exploration and Use of Outer Space (commonly known as the Outer Space Treaty), the United States is responsible for implementing Planetary Protection procedures designed to prevent biological contamination of the Solar System, as well as contamination of the Earth by any samples returned from extra-terrestrial bodies. NASA has established policies and procedures to comply with this treaty, and has successfully policed itself independently and autonomously since the signing of the treaty. However, for the first time in the history of the American space program, private entities outside of NASA have developed the capability and interest to send objects into space and beyond Earth orbit, and no current protocol exists to guarantee these profit-minded entities comply with US Planetary Protection obligations (a costly and time-consuming process). This thesis presents a review of US Planetary Protection obligations, including NASA's procedures and infrastructure related to Planetary Protection, and based on these current protocols provides policy architecture recommendations for the emerging commercial spaceflight industry. It was determined that the most effective policy architecture for ensuring public and private compliance with Planetary Protection places NASA in control of all domestic Planetary Protection matters, and in this role NASA is charged with overseeing, supporting, and regulating the private spaceflight industry. The underlying analysis and architecture tradeoffs that led to this recommendation are presented and discussed.
by Bradley Thomas Holschuh.
S.M.in Technology and Policy
S.M.
Erbaş, Çaǧkan. "System-level modeling and design space exploration for multiprocessor embedded system-on-chip architectures." Amsterdam : Amsterdam : Vossiuspers ; Universiteit van Amsterdam [Host], 2006. http://dare.uva.nl/document/38007.
Повний текст джерелаSilva, Jeferson Santiago da. "Architectural exploration of digital systems design for FPGAs using C/C++/SystemC specification languages." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2015. http://hdl.handle.net/10183/119082.
Повний текст джерелаThe increasing demand for high computational performance and massive data processing has driven the development of systems-on-chip. One implementation target for complex digital systems are FPGA (Field-programmable Gate Array) devices, heavily used for prototyping systems or complex and fast time-to-market electronic products development. Certain inefficient aspects of FPGA devices relate to performance and power degradation with respect to custom hardware design. In this context, this master thesis proposes a survey on FPGA optimization techniques. This work presents a literature review on methods of power and area reduction applied to FPGA designs. Techniques for performance increasing and design speedup enhancing will be presented based on classic and state-of-the-art academic works. The main focus of this work is to discuss high-level design techniques and to present the results obtained in synthesis examples we developed, comparing with hand-coded HDL (Hardware Description Language) designs. In this work we present our methodology for fast digital design development using High-Level Synthesis (HLS) environments. Our methods include efficient high-level code partitioning for proper synthesis directives exploration in HLS tools. However, a non-guided HLS flow showed poor synthesis results when compared to hand-coded HDL designs. To fill this gap, we developed an iterative design space exploration method aiming at improving the area results. Our method is described in a high-level script language and it is compatible with the Xilinx VivadoTM HLS compiler. Our method is capable of detecting optimization checkpoints, automatic synthesis directives insertion, and check the results aiming at reducing area consumption. Our Design Space Exploration (DSE) experimental results proved to be more efficient than non-guided HLS design flow by at least 50% for a VLIW (Very Long Instruction Word) processor and 62% for a 12th-order FIR (Finite Impulse Response) filter implementation. Our area results in terms of flip-flops were up to 4X lower compared to a non-guided HLS flow, while the performance overhead was around 38%, for the VLIW processor compilation. In the FIR filter example, the flip-flops reduction were up to 3X, with no relevant LUTs and performance overhead.
Briao, Eduardo Wenzel. "Métodos de Exploração de Espaço de Projeto em Tempo de Execução em Sistemas Embarcados de Tempo Real Soft baseados em Redes-Em-Chip." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2008. http://hdl.handle.net/10183/13157.
Повний текст джерелаThe complexity of electronic systems design has been increasing due to the technological evolution, which now allows the inclusion of a complete system on a single chip (SoC – System-on-Chip). In order to cope with the corresponding design complexity and reduce design costs and time-to-market, systems are built by assembling pre-designed and pre-verificated functional modules, called IP (Intellectual Property) cores. IP cores can be reused from previous designs or acquired from third-party vendors. However, an adequate communication architecture is required to interconnect these IP cores. Current communication architectures (busses) are unsuitable for the communication requirements of future SoCs (sharing of bandwidth, lack of scalability). Networks-on-Chip (NoC) arise as one of the solutions to fulfill these requirements. While developing NoC-based embedded systems, the NoC customization is mandatory to fulfill design constraints. This design space exploration (DSE), according to most approaches in the literature, is achieved at compile-time (off-line DSE), assuming the profiles of the tasks that will be executed in the embedded system are known a priori. However, nowadays, embedded systems are becoming more and more similar to generic processing devices (such as palmtops), where the tasks to be executed are not completely known a priori. Due to the dynamic modification of the workload of the embedded system, the fulfillment of requirements can be accomplished by using adaptive mechanisms that implement dynamically the DSE (run-time DSE or on-line DSE). In the scope of this work, DSE is on-line. In other words, when the system is running, adaptive mechanisms will be executed to fulfill the requirements of the system. Consequently, on-line DSE can achieve better results than off-line DSE alone, especially considering embedded systems with tight constraints. It is thus possible to maximize the lifetime of the battery that feeds an embedded system, or even to decrease the deadline miss ratio in a soft real-time system, for example by relocating tasks dynamically in order to generate less communication among the processors, provided that the system runs for enough execution time in order to amortize the migration overhead.In this work, a combination of allocation heuristics from the domain of Distributed Computing Systems is applied, for instance bin-packing and linear clustering algorithms. Results shows that applying task reallocation using the Worst-Fit and Linear Clustering combination reduces the energy consumption and deadline miss ratio by 17% and 37%, respectively, using the copy task migration model.
Lafleur, Jarret Marshall. "A Markovian state-space framework for integrating flexibility into space system design decisions." Diss., Georgia Institute of Technology, 2011. http://hdl.handle.net/1853/43749.
Повний текст джерелаZentner, John Marc. "A Design Space Exploration Process for Large Scale, Multi-Objective Computer Simulations." Diss., Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/11572.
Повний текст джерелаPapavramidis, Konstantinos. "Evaluation of Potential Propulsion Systems for a Commercial Micro Moon Lander." Thesis, KTH, Skolan för industriell teknik och management (ITM), 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-263954.
Повний текст джерелаI tillkomsten av Space 4.0 era med kommersialisering och ökad tillgänglighet av rymden, en kravanalys, avvägningsalternativ, utvecklingsstatus och kritiska områden av ett framdrivningssystem för en kommersiell mikro månlandare bärs ut. En undersökning av ett lämpligt system för det aktuella uppdraget genomförs inom ramen för ASTRI-projektet för OHB System AG och Blue Horizon. Olika strategier för banor undersöks och simuleringar utförs för att extrahera ΔV-kraven. Topp-nivå krav definieras och ger den första inputen för designen av framdrivningssystemet. En utvärdering av framdrivningskraven implementeras och belyser de viktigaste faktorer som driver design av framdrivningssystemet. En avvägningsanalys utförs för olika typer av framdrivningssystem och ett preliminärt urval av ett framdrivningssystem som är lämpligt för uppdraget beskrivs. En arkitektur för framdrivningen, ADCS och GNC-delsystem presenteras såväl som en komponentlista. Ett första tillvägagångssätt av landningsfasen beskrivs och en uppskattning av den nödvändiga dragkraften beräknas. Ett enhetligt Bi-propellant framdrivningssystem föreslås som uppfyller ut de flesta uppdragskraven. Analysen visar dock att summan av månlandarens massa, inklusive alla marginaler, överstiger massbegränsningarna men inte de volymbegränsningarna uppsatta i projektet. Resultaten visar att en minskning av nyttolastkapaciteten eller genomförandet av en annan banstrategi kan minska den totala massan då den inom gränsvärdena. Dessutom, ytterligare iterationer i månlandarens koncept som kommer att ge en mer detaljerad design, vilket resulterar i inga extra marginaler, kan leda till att den uppskattade massan minskar ytterligare. Slutligen förs en diskussion om resultaten, med hänsyn till de begränsningarna och de viktigaste faktorerna som måste beaktas för uppdraget. Lönsamheten hos uppdraget på grund av sin kommersiella aspekt är ifrågasatt och vidare utredning föreslås utförs på ”mikro” månlandare konceptet.
Oliveira, Marcio Ferreira da Silva [Verfasser]. "Model-driven engineering methodology for design space exploration of embedded systems / Marcio Ferreira da Silva Oliveira." Paderborn : Universitätsbibliothek, 2014. http://d-nb.info/1051024463/34.
Повний текст джерелаNoll, Jochen [Verfasser]. "Conceptual Design of Modular Space Transportation and Infrastructure Systems for Future Human Exploration Missions / Jochen Noll." München : Verlag Dr. Hut, 2012. http://d-nb.info/1025821092/34.
Повний текст джерелаAksaray, Derya. "Formulation of control strategies for requirement definition of multi-agent surveillance systems." Diss., Georgia Institute of Technology, 2014. http://hdl.handle.net/1853/53121.
Повний текст джерелаMUKHERJEE, MADHUBANTI. "ALGORITHMS FOR COUPLING CIRCUIT AND PHYSICAL SYNTHESIS WITH HIGH-LEVEL DESIGN-SPACE EXPLORATION FOR 2D AND 3D SYSTEMS." University of Cincinnati / OhioLINK, 2004. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1112670784.
Повний текст джерелаMattos, Julio Carlos Balzano de. "Design space exploration of SW and HW IP based on object oriented methodology for embedded system applications." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2007. http://hdl.handle.net/10183/13484.
Повний текст джерелаSoftware is increasingly becoming the major cost factor for embedded devices. Nowadays, with the growing complexity of embedded systems, it is necessary to use techniques and methodologies that can, at the same time, increase software productivity and manipulate embedded systems constraints - like memory footprint, real-time behavior, performance and energy. Object-oriented modeling and design is a widely known methodology in software engineering. This paradigm may satisfy software portability and maintainability requirements, but it presents overhead in terms of memory, performance and code size. This thesis introduces a methodology and a set of tools that can deal, at the same time, with object orientation and di erent embedded systems requirements. To achieve this goal, the thesis presents a methodology to explore object-oriented embedded software improving di erent levels in the software design based on di erent implementations with the same processor. The results of the methodology are presented based on an MP3 player application.
Mukherjee, Madhubanti. "Algorithms for coupling circuit and physical synthesis with high-level design-space exploration of 2D and 3D systems." Cincinnati, Ohio : University of Cincinnati, 2004. http://www.ohiolink.edu/etd/view.cgi?acc%5Fnum=ucin1112670784.
Повний текст джерелаÖzlük, Ali Cemal [Verfasser], Klaus [Akademischer Betreuer] Kabitzsch, and Alexander [Akademischer Betreuer] Fay. "Design Space Exploration for Building Automation Systems / Ali Cemal Özlük. Gutachter: Klaus Kabitzsch ; Alexander Fay. Betreuer: Klaus Kabitzsch." Dresden : Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2013. http://d-nb.info/1068154799/34.
Повний текст джерелаGiroudot, Frédéric. "NoC-based Architectures for Real-Time Applications : Performance Analysis and Design Space Exploration." Thesis, Toulouse, INPT, 2019. https://oatao.univ-toulouse.fr/25921/1/Giroudot_Frederic.pdf.
Повний текст джерелаMonoprocessor architectures have reached their limits in regard to the computing power they offer vs the needs of modern systems. Although multicore architectures partially mitigate this limitation and are commonly used nowadays, they usually rely on intrinsically non-scalable buses to interconnect the cores. The manycore paradigm was proposed to tackle the scalability issue of bus-based multicore processors. It can scale up to hundreds of processing elements (PEs) on a single chip, by organizing them into computing tiles (holding one or several PEs). Intercore communication is usually done using a Network-on-Chip (NoC) that consists of interconnected onchip routers allowing communication between tiles. However, manycore architectures raise numerous challenges, particularly for real-time applications. First, NoC-based communication tends to generate complex blocking patterns when congestion occurs, which complicates the analysis, since computing accurate worst-case delays becomes difficult. Second, running many applications on large Systems-on-Chip such as manycore architectures makes system design particularly crucial and complex. On one hand, it complicates Design Space Exploration, as it multiplies the implementation alternatives that will guarantee the desired functionalities. On the other hand, once a hardware architecture is chosen, mapping the tasks of all applications on the platform is a hard problem, and finding an optimal solution in a reasonable amount of time is not always possible. Therefore, our first contributions address the need for computing tight worst-case delay bounds in wormhole NoCs. We first propose a buffer-aware worst-case timing analysis (BATA) to derive upper bounds on the worst-case end-to-end delays of constant-bit rate data flows transmitted over a NoC on a manycore architecture. We then extend BATA to cover a wider range of traffic types, including bursty traffic flows, and heterogeneous architectures. The introduced method is called G-BATA for Graph-based BATA. In addition to covering a wider range of assumptions, G-BATA improves the computation time; thus increases the scalability of the method. In a second part, we develop a method addressing design and mapping for applications with real-time constraints on manycore platforms. It combines model-based engineering tools (TTool) and simulation with our analytical verification technique (G-BATA) and tools (WoPANets) to provide an efficient design space exploration framework. Finally, we validate our contributions on (a) a serie of experiments on a physical platform and (b) two case studies taken from the real world: an autonomous vehicle control application, and a 5G signal decoder application
Oliveira, Marcio Ferreira da Silva. "Exploração do espaço de projeto em sistemas embarcados baseados em plataformas através de estimativas extraídas de modelos UML." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2006. http://hdl.handle.net/10183/8303.
Повний текст джерелаIn order to quickly implement an embedded system that is mainly based on software, two orthogonal approaches have been proposed: Platform-based Design, which maximizes the reuse of components; and Model Driven Development, which rises the abstraction level by using object-oriented concepts and UML for modeling an application. However, with this increasing of the abstraction level, software engineers do not have an exact idea of the impact of their modeling decisions on important issues such as performance, energy, and memory footprint for a given embedded platform. This work proposes to estimate data and program memory, performance, and energy directly from UML model specifications to explore the design space in the early steps of development process. Experimental results show a very small estimation error when platform components are reused and their costs on the target platform are already known. Real-life applications are modeled in different ways and demonstrate the effectiveness of the estimates in an early design space exploration, allowing the designer to evaluate and compare different modeling solutions. The estimated values used in the design space exploration can achieve errors as low as 5%.
Blocher, Andrew Gene. "Alternative Mission Concepts for the Exploration of Outer Planets Using Small Satellite Swarms." DigitalCommons@CalPoly, 2017. https://digitalcommons.calpoly.edu/theses/1820.
Повний текст джерелаCota, Erika Fernandes. "Reuse-based test planning for core-based systems-on-chip." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2003. http://hdl.handle.net/10183/4180.
Повний текст джерелаElectronic applications are currently developed under the reuse-based paradigm. This design methodology presents several advantages for the reduction of the design complexity, but brings new challenges for the test of the final circuit. The access to embedded cores, the integration of several test methods, and the optimization of the several cost factors are just a few of the several problems that need to be tackled during test planning. Within this context, this thesis proposes two test planning approaches that aim at reducing the test costs of a core-based system by means of hardware reuse and integration of the test planning into the design flow. The first approach considers systems whose cores are connected directly or through a functional bus. The test planning method consists of a comprehensive model that includes the definition of a multi-mode access mechanism inside the chip and a search algorithm for the exploration of the design space. The access mechanism model considers the reuse of functional connections as well as partial test buses, cores transparency, and other bypass modes. The test schedule is defined in conjunction with the access mechanism so that good trade-offs among the costs of pins, area, and test time can be sought. Furthermore, system power constraints are also considered. This expansion of concerns makes it possible an efficient, yet fine-grained search, in the huge design space of a reuse-based environment. Experimental results clearly show the variety of trade-offs that can be explored using the proposed model, and its effectiveness on optimizing the system test plan. Networks-on-chip are likely to become the main communication platform of systemson- chip. Thus, the second approach presented in this work proposes the reuse of the on-chip network for the test of the cores embedded into the systems that use this communication platform. A power-aware test scheduling algorithm aiming at exploiting the network characteristics to minimize the system test time is presented. The reuse strategy is evaluated considering a number of system configurations, such as different positions of the cores in the network, power consumption constraints and number of interfaces with the tester. Experimental results show that the parallelization capability of the network can be exploited to reduce the system test time, whereas area and pin overhead are strongly minimized. In this manuscript, the main problems of the test of core-based systems are firstly identified and the current solutions are discussed. The problems being tackled by this thesis are then listed and the test planning approaches are detailed. Both test planning techniques are validated for the recently released ITC’02 SoC Test Benchmarks, and further compared to other test planning methods of the literature. This comparison confirms the efficiency of the proposed methods.
Bunuan, Paul F. "FIDOE: A Proof-of-concept Martian Robotic Support Cart." Digital WPI, 1999. https://digitalcommons.wpi.edu/etd-theses/906.
Повний текст джерелаMEDARDONI, Simone. "Driving the Network-on-Chip Revolution to Remove the Interconnect Bottleneck in Nanoscale Multi-Processor Systems-on-Chip." Doctoral thesis, Università degli studi di Ferrara, 2009. http://hdl.handle.net/11392/2389197.
Повний текст джерелаSakai, Tadashi. "A Study of Variable Thrust, Variable Specific Impulse Trajectories for Solar System Exploration." Diss., Georgia Institute of Technology, 2004. http://hdl.handle.net/1853/4904.
Повний текст джерелаLi, Letitia. "Approche orientée modèles pour la sûreté et la sécurité des systèmes embarqués." Thesis, Université Paris-Saclay (ComUE), 2018. http://www.theses.fr/2018SACLT002/document.
Повний текст джерелаThe presence of communicating embedded systems/IoTs in our daily lives have brought a myriad of benefits, from adding conveniences and entertainment, to improving the safety of our commutes and health care. However, the flaws and vulnerabilities in these devices expose their users to risks of property damage, monetary losses, and personal injury. For example, consumer vehicles, both connected and conventional, have succumbed to a variety of design flaws resulting in injuries and death. At the same time, as vehicles are increasingly connected (and in the near future, autonomous), researchers have demonstrated possible hacks on their sensors or internal control systems, including direct injection of messages on the CAN bus.Ensuring the safety of users or bystanders involves considering multiple factors. Conventional safety suggests that a system should not contain software and hardware flaws which can prevent it from correct function. `Safety of the Intended Function' involves avoiding the situations which the system or its components cannot handle, such as adverse extreme environmental conditions. Timing can be critical for certain real-time systems, as the system will need to respond to certain events, such as obstacle avoidance, within a set period to avoid dangerous situations. Finally, the safety of a system depends on its security. An attacker who can send custom commands or modify the software of the system may change its behavior and send it into various unsafe situations. Various safety and security countermeasures for embedded systems, especially connected vehicles, have been proposed. To place these countermeasures correctly requires methods of analyzing and verifying that the system meets all safety, security, and performance requirements, preferably at the early design phases to minimize costly re-work after production. This thesis discusses the safety and security considerations for embedded systems, in the context of Institut Vedecom's autonomous vehicle. Among the proposed approaches to ensure safety and security in embedded systems, Model-Driven Engineering is one such approach that covers the full design process, from elicitation of requirements, design of hardware and software, simulation/formal verification, and final code generation. This thesis proposes a modeling-based methodology for safe and secure design, based on the SysML-Sec Methodology, which involve new modeling and verification methods. Security modeling is generally performed in the last phases of design. However, security impacts the early architecture/mapping and HW/SW partitioning decisions should be made based on the ability of the architecture to satisfy security requirements. This thesis proposes how to model the security mechanisms and the impact of an attacker as relevant to the HW/SW Partitioning phase. As security protocols negatively impact performance, it becomes important to measure both the usage of hardware components and response times of the system. Overcharged components can result in unpredictable performance and undesired delays. This thesis also discusses latency measurements of safety-critical events, focusing on one critical to autonomous vehicles: braking as after obstacle detection. Together, these additions support the safe and secure design of embedded systems
Scannell, Peter. "Three-dimensional Information Space : An Exploration of a World Wide Web-based, Three-dimensional, Hierarchical Information Retrieval Interface Using Virtual Reality Modeling Language." Thesis, University of North Texas, 1997. https://digital.library.unt.edu/ark:/67531/metadc278715/.
Повний текст джерелаPhan, Leon L. "A methodology for the efficient integration of transient constraints in the design of aircraft dynamic systems." Diss., Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/34750.
Повний текст джерелаAnil, Vijay Sankar. "Mission-based Design Space Exploration and Traffic-in-the-Loop Simulation for a Range-Extended Plug-in Hybrid Delivery Vehicle." The Ohio State University, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=osu1587663664531601.
Повний текст джерелаKlicker, Laura. "A Method for Standardization within the Payload Interface Definition of a Service-Oriented Spacecraft using a Modified Interface Control Document." Thesis, KTH, Rymdteknik, 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-217971.
Повний текст джерелаFör en ökad tillgång till rymden finns det behov av standardisering för en förbättrad service. Utvecklingen av standardiserade rymdfarkostgränsytor för flera och olika nyttolaster har undersökts via ett dokumentet för gränssnittskontroll (ICD) inom projektet Peregrine Lunar Lander för Astrobotic Technologies, Inc. Proceduren är enkel, transparent och anpassningbar; dess användning för andra liknande projekt har värderats.
Specht, Emilena. "An approach for embedded software generation based in declarative alloy models." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2008. http://hdl.handle.net/10183/22812.
Повний текст джерелаThis work proposes a new approach for embedded software development, by combining the abstraction and model verification properties of the Alloy declarative language with the broad acceptance in industry of Java. The approach comes into play since software automation in the embedded domain has become a major need, as currently most of the development time is spent designing software for such hardconstrained resources products. Design automation tools for embedded systems must meet the demand for productivity and maintainability, but constraints such as memory, power and performance must still be considered. Design automation tools deal with productivity and maintainability by allowing high-level specifications, which is hard to accomplish on the embedded domain due to the mixed behavior nature of many embedded applications. Approaches that provide means for formal verification are also attractive, but their usage is usually not straightforward, and for this reason they are not that helpful in dealing with time-tomarket constraints. By using Alloy, based in first-order logic, it is possible to obtain high-level specifications and formal model verification with a single language. This work shows the powerful abstraction provided by the Alloy language for embedded applications, as well as rules for obtaining automatically Java code from Alloy models. The Java source code generation from Alloy models, combined with an estimation tool, provides design space exploration to match tight embedded software design constraints, what is usually not taken into account by standard software engineering techniques.
Alcantara, de Lima Otavio Junior. "Emulation platform synthesis and NoC evaluation for embedded systems : towards next generation networks." Thesis, Saint-Etienne, 2015. http://www.theses.fr/2015STET4001/document.
Повний текст джерелаThe ever-increasing complexity of many-core embedded system applications demands a flexible communication structure capable of supporting different traffics requirements at run-time. The Networks-on-Chip (NoCs) emerge as the most promising communication technology for the modern many-cores SoC (System-on-Chip), whereby they have greater scalability than other solutions such as buses and point to point connections. As NoCs become de facto standard for on chip systems, NoC performance evaluation tools become critical for SoCs design. The FPGA based emulation platforms accelerate NoC benchmarking as well as design space exploration. Those platforms have high accuracy and low execution time in relation to NoC simulators. An FPGA-based emulation platform is composed by tens or hundreds of distributed components. These components should be timely managed in order to execute an evaluation scenario. There is a lack of standard protocols to drive FPGA-based NoC emulators. Such protocols could ease the integration of emulation components developed by different designers, as well as they could enable the configuration of the emulation nodes without FPGA re-synthesis and the extraction of emulation results. The NoC hardware emulation is quite challenging. It is important to validate new NoC architectures with realistic workloads, because they provide much more accurate results. The generation of applications traffic patterns is a key concern for NoC emulation. The dependency aware traces are an appealing solution for the generation of realistic traffic workloads. They are more accurate than ordinary traces for a broad range of NoC architectures because they contain packets dependencies information. However, they tend to be bigger than the original ones what demands more FPGA resources. This thesis aims the synthesis of FPGA-based NoC emulation platforms for the future multi-core embedded systems. We are interested in investigating strategies to generate realistic traffic patterns for NoCs emulated on FPGAs, as well as the management of the emulation platform using standard protocols inspired by the computer networks protocols. One contribution of this thesis is a trace analysis framework which addresses the packets dependencies extraction problem. The proposed framework analyzes traces from a message passing application in order to build a Model of Computation (MoC). This MoC reproduces the communicative behavior of an application node. A dependency-aware Traffic Generator (TG) is created from the proposed MoC. This TG generates the application traffic pattern during an FPGA-based NoC emulation. Another contribution is a light version of SNMP (Simple Network Management Protocol) to manage an FPGA-based NoC emulation platform. An FPGA-based emulation platform architecture is proposed based on the principles of SNMP protocol. This platform has a high-level interface to the emulation components provided by that protocol, which also eases the integration of emulation components created by different designers. The emulation platform and the protocol capacities are evaluated during a task mapping and mesh topology design space exploration. A prospective analysis of future NoCs architectures is also a contribution of this thesis. In this analysis, a conceptual architecture of a future multi-core embedded system is used as model to extract these networks requirements. From this analysis, it is proposed some networking mechanisms. The first mechanism is a congestion-aware routing algorithm, which is an adaptive routing algorithm that selects the output path for a given packet based on a simple prioritized scheme of sets of rules. It is also proposed a congestion-control mechanisms for the vertical links interconnecting the layers of a 3D NoC. This mechanism is based upon the diffusion of congestion information by a piggyback protocol
Souza, Junior Adao Antonio de. "Digital approach for the design of statistical analog data acquisition on SoCs." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2005. http://hdl.handle.net/10183/11491.
Повний текст джерелаMarcus, Ventovaara, and Hasanbegović Arman. "A Method for Optimised Allocation of System Architectures with Real-time Constraints." Thesis, Mälardalens högskola, Akademin för innovation, design och teknik, 2018. http://urn.kb.se/resolve?urn=urn:nbn:se:mdh:diva-39492.
Повний текст джерелаSvensson, August. "Range-based Wireless Sensor Network Localization for Planetary Rovers." Thesis, Luleå tekniska universitet, Rymdteknik, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:ltu:diva-83213.
Повний текст джерелаMartins, Luiz Gustavo Almeida. "Exploração de sequências de otimização do compilador baseada em técnicas hibridas de mineração de dados complexos." Universidade de São Paulo, 2015. http://www.teses.usp.br/teses/disponiveis/55/55134/tde-28032016-160827/.
Повний текст джерелаDue to the large number of optimizations provided in modern compilers and to compiler optimization specific opportunities, a Design Space Exploration (DSE) is necessary to search for the best sequence of compiler optimizations for a given code fragment (e.g., function). As this exploration is a complex and time consuming task, we present new DSE strategies to reduce the exploration time and still select optimization sequences able to improve the performance of each function. The DSE is based on a clustering approach which groups functions with similarities and then explore the reduced search space provided by the optimizations previously suggested for the functions in each group. The identification of similarities between functions uses a data mining method which is applied to a symbolic representation of the source code. The DSE strategies uses the reduced optimizations set identified by clustering in two ways: as the design space or as the initial configuration of the algorithm. In both ways, the adoption of a pre-selection based on clustering allows the use of simple and fast DSE algorithms. Several experiments for evaluating the effectiveness of the proposed approach address the exploration of compiler optimization sequences. Besides, we investigate the impact of each technique or component employed in the selection process. Experimental results reveal that the use of our new clustering-based DSE approach achieved a significant reduction on the total exploration time of the search space at the same time that obtained performance speedups close to a traditional genetic algorithmbased approach.
Tuzov, Ilya. "Dependability-driven Strategies to Improve the Design and Verification of Safety-Critical HDL-based Embedded Systems." Doctoral thesis, Universitat Politècnica de València, 2021. http://hdl.handle.net/10251/159883.
Повний текст джерела[CA] La utilització de sistemes encastats en cada vegada més àmbits d'aplicació està portant al fet que el seu disseny haja d'enfrontar-se a majors requisits de rendiment, consum d'energia i àrea (PPA). Així mateix, la seua utilització en aplicacions crítiques provoca que hagen de complir amb estrictes requisits de confiabilitat per a garantir el seu correcte funcionament durant períodes prolongats de temps. En particular, l'ús de dispositius lògics programables de tipus FPGA és un gran desafiament des de la perspectiva de la confiabilitat, ja que aquests dispositius són molt sensibles a la radiació. Per tot això, la confiabilitat ha de considerar-se com un dels criteris principals per a la presa de decisions al llarg del tot flux de disseny, que ha de complementar-se amb diversos processos que permeten aconseguir estrictes requisits de confiabilitat. Primer, l'avaluació de la robustesa del disseny permet identificar els seus punts febles, guiant així la definició de mecanismes de tolerància a fallades. Segon, l'eficàcia dels mecanismes definits ha de validar-se experimentalment. Tercer, l'avaluació comparativa de la confiabilitat permet als dissenyadors seleccionar els components predissenyats (IP), les tecnologies d'implementació i les eines de disseny (EDA) més adequades des de la perspectiva de la confiabilitat. Finalment, l'exploració de l'espai de disseny (DSE) permet configurar de manera òptima els components i les eines seleccionats, millorant així la confiabilitat i les mètriques PPA de la implementació resultant. Tots els processos anteriorment esmentats es basen en tècniques d'injecció de fallades per a poder avaluar la robustesa del sistema dissenyat. A pesar que existeix una àmplia varietat de tècniques d'injecció de fallades, diverses problemes encara han d'abordar-se per a cobrir les necessitats plantejades en el flux de disseny. Aquelles solucions basades en simulació (SBFI) han d'adaptar-se als models de nivell d'implementació, tenint en compte l'arquitectura dels diversos components de la tecnologia utilitzada. Les tècniques d'injecció de fallades basades en FPGAs (FFI) han d'abordar problemes relacionats amb la granularitat de l'anàlisi per a poder localitzar els punts febles del disseny. Un altre desafiament és la reducció del cost temporal dels experiments d'injecció de fallades. A causa de l'alta complexitat dels dissenys actuals, el temps experimental dedicat a l'avaluació de la confiabilitat pot ser excessiu fins i tot en aquells escenaris més simples, mentre que pot ser inviable en aquells processos relacionats amb l'avaluació de múltiples configuracions alternatives del disseny. Finalment, aquests processos orientats a la confiabilitat manquen d'un suport instrumental que permeta cobrir el flux de disseny amb tota la seua varietat de llenguatges de descripció de maquinari, tecnologies d'implementació i eines de disseny. Aquesta tesi aborda els reptes anteriorment esmentats amb la finalitat d'integrar, de manera eficaç, aquests processos orientats a la confiabilitat en el flux de disseny. Primerament, es proposen nous mètodes d'injecció de fallades que permeten una avaluació de la confiabilitat, precisa i detallada, en diferents nivells del flux de disseny. Segon, es defineixen noves tècniques per a l'acceleració dels experiments d'injecció que milloren el seu cost temporal. Tercer, es defineix dues estratègies DSE que permeten configurar de manera òptima (des de la perspectiva de la confiabilitat) els components IP i les eines EDA, amb un cost experimental mínim. Quart, es proposa un kit d'eines (DAVOS) que automatitza i incorpora amb eficàcia els processos orientats a la confiabilitat en el flux de disseny semicustom. Finalment, es demostra la utilitat i eficàcia de les propostes mitjançant un cas d'estudi en el qual s'implementen tres processadors encastats en un FPGA de Xilinx serie 7.
[EN] Embedded systems are steadily extending their application areas, dealing with increasing requirements in performance, power consumption, and area (PPA). Whenever embedded systems are used in safety-critical applications, they must also meet rigorous dependability requirements to guarantee their correct operation during an extended period of time. Meeting these requirements is especially challenging for those systems that are based on Field Programmable Gate Arrays (FPGAs), since they are very susceptible to Single Event Upsets. This leads to increased dependability threats, especially in harsh environments. In such a way, dependability should be considered as one of the primary criteria for decision making throughout the whole design flow, which should be complemented by several dependability-driven processes. First, dependability assessment quantifies the robustness of hardware designs against faults and identifies their weak points. Second, dependability-driven verification ensures the correctness and efficiency of fault mitigation mechanisms. Third, dependability benchmarking allows designers to select (from a dependability perspective) the most suitable IP cores, implementation technologies, and electronic design automation (EDA) tools. Finally, dependability-aware design space exploration (DSE) allows to optimally configure the selected IP cores and EDA tools to improve as much as possible the dependability and PPA features of resulting implementations. The aforementioned processes rely on fault injection testing to quantify the robustness of the designed systems. Despite nowadays there exists a wide variety of fault injection solutions, several important problems still should be addressed to better cover the needs of a dependability-driven design flow. In particular, simulation-based fault injection (SBFI) should be adapted to implementation-level HDL models to take into account the architecture of diverse logic primitives, while keeping the injection procedures generic and low-intrusive. Likewise, the granularity of FPGA-based fault injection (FFI) should be refined to the enable accurate identification of weak points in FPGA-based designs. Another important challenge, that dependability-driven processes face in practice, is the reduction of SBFI and FFI experimental effort. The high complexity of modern designs raises the experimental effort beyond the available time budgets, even in simple dependability assessment scenarios, and it becomes prohibitive in presence of alternative design configurations. Finally, dependability-driven processes lack an instrumental support covering the semicustom design flow in all its variety of description languages, implementation technologies, and EDA tools. Existing fault injection tools only partially cover the individual stages of the design flow, being usually specific to a particular design representation level and implementation technology. This work addresses the aforementioned challenges by efficiently integrating dependability-driven processes into the design flow. First, it proposes new SBFI and FFI approaches that enable an accurate and detailed dependability assessment at different levels of the design flow. Second, it improves the performance of dependability-driven processes by defining new techniques for accelerating SBFI and FFI experiments. Third, it defines two DSE strategies that enable the optimal dependability-aware tuning of IP cores and EDA tools, while reducing as much as possible the robustness evaluation effort. Fourth, it proposes a new toolkit (DAVOS) that automates and seamlessly integrates the aforementioned dependability-driven processes into the semicustom design flow. Finally, it illustrates the usefulness and efficiency of these proposals through a case study consisting of three soft-core embedded processors implemented on a Xilinx 7-series SoC FPGA.
Tuzov, I. (2020). Dependability-driven Strategies to Improve the Design and Verification of Safety-Critical HDL-based Embedded Systems [Tesis doctoral]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/159883
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