Дисертації з теми "Software switch"

Orientador: Christian Rodolfo Esteve Rothenberg
Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Elétrica e de Computação
Made available in DSpace on 2018-08-27T04:14:12Z (GMT). No. of bitstreams: 1 Fernandes_EderLeao_M.pdf: 1013570 bytes, checksum: 6c396641a9ce6faceedd380180040736 (MD5) Previous issue date: 2015
Resumo: OpenFlow é a mais proeminente tecnologia para a implementação de Redes Definidas por Software (RDS). Projetada como uma interface de controle entre switches e controladores, o protocolo pode ser visto como um conjunto de instruções para programar a lógica de encaminhamento em comutadores da rede. A primeira versão do OpenFlow atraiu a atenção de pesquisadores da indústria e universidades interessados nos potenciais benefícios prometidos por RDS. Rápidamente surgiram ferramentas para experimentação em OpenFlow 1.0, incluindo comutadores, controladores e software para testes e emulação. Após o início da padronização do protocolo pela OpenNetworkFoundation, o protocolo OpenFlow evoluiu rapidamente dando origem à novas especificações. As novas funcionalidades aumentaram as possibilidades de experimentos, gerando entusiasmo. Porém, o desenvolvimento das ferramentas de experimen- tação não acompanharam o mesmo rítmo do protocolo. Para preencher essa lacuna, nosso projeto desenvolveu um comutador em software com suporte a OpenFlow 1.3. Guiado pelo objetivo de ser simples e básicos requisitos de desempenho, a proposta da ferramenta é ser uma opção, fácil e funcional para desenvolvedores de aplicações RDS buscando utilizar as novas funcionalidades do OpenFlow 1.3. Em suma, o software desenvolvido nesse projeto foi o primeiro comutador OpenFlow 1.3 do mundo. Lançado como projeto de código aberto, possibilitou a pesquisadores de todo o mundo a prototipagem e demonstração de soluções não possíveis anteriormente
Abstract: OpenFlow is the most prominent technology to enable Software Defined Networking (SDN). Designed as a control interface between switches and controllers, the protocol can be considered an instruction set to program the network forwarding logic. The first OpenFlow version attracted attention from both the industry and academy researchers interested in SDN promised benefits. Quickly, a toolset for OpenFlow 1.0 was available, which included switches, controllers, test and emulation software. When the protocol standardization process started by the Open Network Foundation, OpenFlow evolved fast and new specifications emerged in the last years. New features empowered the protocol and created enthusiasm; however projects of experimentation tools did not followed the OpenFlow fast pace. This work addresses one of these gaps, implementing an experimenter friendly OpenFlow 1.3 software switch. Driven by simplicity and basic performance requirements, the tool purpose is to be a functional and easy option for SDN developers that want to take advantage of the benefits brought by more recent OpenFlow versions. Overall, this project resulted in the open source release of the first OpenFlow 1.3 switch, allowing researchers from all around the globe to prototype and demonstrate solutions not possible until this work. Keywords: Computer Networks; Software Defined
Mestrado
Engenharia de Computação
Mestre em Engenharia Elétrica

Self-adaptivity, characterized by the ability to dynamically adjust behavior at runtime, is a growing trend in the evolution of modern embedded systems. While self-adaptive systems tend to be flexible and autonomous, self-adaptivity may inevitably complicate software design, test and analysis. A strategy for taming the growing software complexity of self-adaptive systems is to partition system behaviors into different operational modes specified at design time. Such a multi-mode system can change behavior by switching between modes at runtime under certain circumstances. Multi-mode systems can benefit from a complementary approach to the software development of complex systems: Component-Based Software Engineering (CBSE), which fosters reuse of independently developed software components. However, the state-of-the-art component-based development of multi-mode systems does not take full advantage of CBSE, as reuse of modes at component level is barely addressed. Modes are often treated as system properties, while mode switches are handled by a global mode manager. This centralized mode management entails global information of all components, whereas the global information may be inaccessible in component-based systems. Another potential problem is that a single mode manager does not scale well, particularly at design time,  for a large number of components and modes.   In this thesis we propose a distributed solution to the component-based development of multi-mode systems, aiming for a more efficient and scalable mode management. Our goal is to fully incorporate modes in software component reuse, supporting reuse of multi-mode components, i.e., components able to run in multiple modes. We have developed a generic framework, the Mode-Switch Logic (MSL), which not only supports reuse of multi-mode components but also provides runtime mechanisms for handling mode switch. MSL includes three fundamental elements: (1) a mode-aware component model with the formal specification of reusable multi-mode software components; (2) a mode mapping mechanism for the seamless composition of multi-mode components; and (3) a mode-switch runtime mechanism which is executed by each component in isolation from its functional execution and coordinates the mode switches of different components without the need of global mode information. The mode-switch runtime mechanism has been verified by model checking in conjunction with mathematical proofs. We also provide a mode-switch timing analysis for the runtime mechanism to respect real-time requirements.   MSL is dedicated to the mode aspect of a system irrespective of component execution semantics, thus independent of the choice of component models. We have integrated MSL in the ProCom component model with the extension of support for reuse of multi-mode components and distributed mode-switch handling. Although the distributed mode-switch handling of MSL is more flexible and scalable than the conventional centralized approach, when components are deployed on a single hardware platform and global mode information is available, centralized mode-switch handling is more efficient in terms of runtime overhead and mode-switch time. Hence, MSL is supplemented with a mode transformation technique to enhance runtime mode-switch efficiency by converting the distributed mechanism to a centralized mechanism. MSL together with the mode transformation technique has been implemented in a prototype tool where one can build multi-mode systems by reusing multi-mode components. The applicability of MSL is demonstrated in two proof-of-concept case studies.
ARROWS - Design Techniques for Adaptive Embedded Systems

Component-based software engineering is becoming a prominent solution to the development of complex embedded systems. Since it allows a system to be built by reusable and independently developed components, component-based development substantially facilitates the development of a complex embedded system and allows its complexity to be better managed. Meanwhile, partitioning system behavior into multiple operational modes is also an effective approach to reducing system complexity. Combining the component-based approach with the multi-mode approach, we get a component-based multi-mode system, for which a key issue is its mode switch handling. The mode switch of such a system corresponds to the joint mode switches of many hierarchically organized components. Such a mode switch is not trivial as it amounts to coordinate the mode switches of different components that are independently developed. Since most existing approaches to mode switch handling assume that mode switch is a global event of the entire system, they cannot be easily applied to component-based multi-mode systems where both the mode switch of the system and each individual component must be considered, and where components cannot be assumed to have global knowledge of the system. In this thesis, we present a mechanism---the Mode Switch Logic (MSL)---which provides an effective solution to mode switch in component-based multi-mode systems. MSL enables a multi-mode system to be developed in a component-based manner, including (1) a mode-aware component model proposed to suit the multi-mode context; (2) a mode mapping mechanism for the seamless composition of multi-mode components and their mode switch guidance; (3) a mode switch runtime mechanism which coordinates the mode switches of all related components so that the mode switch can be correctly and efficiently performed at the system level; and (4) a timing analysis for mode switches realized by MSL. All the essential elements of MSL are additionally demonstrated by a case study.
ARROWS

Avec la prévalence de logicielisation, virtualisation est devenue une technologie dominante dans des data-centres et clouds. Deux aspects principaux de la logicielisation de réseaux sont Software Defined Network (SDN) et Network Function Virtualization (NFV), dont un des outils essentiel sont les switches logiciels, à l’opposition des switches matériaux. Les switches logiciels sont également indispensables pour le succès de NFV. Cette thèse vise à relever des défis principaux dans la logicielisation de réseaux. Spécifiquement, elle porte sur le déploiement des switches logiciels dans un réseau virtuel avec SDN
Due to the growing trend of “Softwarization”, virtualization is becoming the dominating technology in data center and cloud environment. Software Defined Network (SDN) and Network Function Virtualization (NFV) are different expressions of “Network Softwarization”. Software switch is exactly the suitable and powerful tool to support network softwarization, which is also indispensable to the success of network virtualization. Regarding the challenges and opportunities in network softwarization, this thesis aims to investigate the deployment of software switch in a SDN-enabled network virtualization environment

This thesis investigated the development of an EEG-based brain controlled switch and the design of a software for nerve conduction study. For EEG-based brain controlled switch, we proposed a novel paradigm for an online brain-controlled switch based on Event-Related Synchronizations (ERDs) following external sync signals. Furthermore, the ERD feature was enhanced by 3 event-related moving averages and the performance was tested online. Subjects were instructed to perform an intended motor task following an external sync signal in order to turn on a virtual switch. Meanwhile, the beta-band (16-20Hz) relative ERD power (ERD in reverse value order) of a single EEG Laplacian channel from primary motor area was calculated and filtered by 3 event-related moving average in real-time. The computer continuously monitored the filtered relative ERD power level until it exceeded a pre-set threshold selected based on the observations of ERD power range to turn on the virtual switch. Four right handed healthy volunteers participated in this study. The false positive rates encountered among the four subjects during the operation of the virtual switch were 0.8±0.4%, whereby the response time delay was 36.9±13.0s and the subjects required approximately 12.3±4.4 s of active urging time to perform repeated attempts in order to turn on the switch in the online experiments. The aim of nerve conduction simulator software design is to create software that can be used by nerve conduction simulator to serve as a medical simulator or education tool to train novice physicians for nerve conduction study test. The real response waveform of 10 different upper limb nerves in conduction studies were obtained from the equipment used in real patient studies. A waveform generation model was built to generalize the response waveform near the standard stimulus site within study interest region based on the extracted waveforms and normal reference parameters of each study and stimulus site coordinates. Finally, based on the model, a software interface was created to simulate 10 different nerve conduction studies of the upper limb with 9 pathological conditions.

Il paradigma “Software-Defined Networking” (SDN) ha suscitato recentemente interesse grazie allo sviluppo e all'implementazione di uno standard tecnologico come OpenFlow. Con il modello SDN viene proposta una rete programmabile tramite la separazione dell’unità di controllo e l'unità di instradamento, rendendo quindi i nodi di rete (come ad es. router o switch) esclusivamente hardware che inoltra pacchetti di dati secondo le regole dettate dal controller. OpenFlow rappresenta lo standard dominante nella tecnologia SDN in grado di far comunicare l'unità controller e l'hardware di uno o più nodi di rete. L'utilizzo di OpenFlow consente maggiore dinamicità e agevolazione nella personalizzazione della rete attraverso un'interfaccia utente, includendo svariate funzioni quali la modifica e l’automatizzazione delle regole di instradamento, la creazione di una rete virtuale dotata di nodi logici o la possibilità di monitorare il traffico accrescendo la sicurezza della propria rete.

Questa tesi si concentra nell’analizzare la Software-Defined Networking e in particolare il protocollo OVSDB (Open vSwitch Database) che permette di avere un’interfaccia di gestione moderna e programmatica per la gestione e l’automazione delle reti. Grazie ad esso è possibile gestire le implementazioni Open vSwitch attraverso degli appositi comandi da remoto i quali, sfruttando i metodi JSON-RPC, ci consentono di modificare il database di un server.

The Quality of Service (QoS) is in converged systems an important parameter. The dissertation thesis deals with research of QoS implementation into a newly developed network element. There was designed and implemented new protocol, based on the IP. The dissertation thesis deals with proposal of a new network element – the switch controlled by a neural network. During the research have been measured switches cross a performance classes. On the base of the measurement was designed the new four-port switch with switch fabric build on crossbar switch with an external control. The switch was designed with maximum QoS support. The switch fabric is controlled by the feedforward backpropagation neural network. The designed switch was modeled in the MATLAB and Simulink. The simulations prove that developed solution is functional.

Essa dissertação de mestrado apresenta um estudo na Teoria de Opções Reais, um assunto ainda não muito conhecido da análise de projetos industriais, mas que vem sendo considerado como de extrema importância para a valoração e seleção de novos projetos. Esta teoria trata da incerteza, da flexibilidade e da capacidade do gerente em tomar decisões em projetos. No mundo atual, as interações competitivas e avanços tecnológicos ocorrem de forma acelerada. Companhias precisam ser flexíveis e reagir rapidamente a mudanças para evitar por em risco suas posições no mercado. A utilização de técnicas de análise tradicionais, que desconsideram a ação gerencial, tem levado grandes companhias a perder sua posição competitiva. O desenvolvimento da Teoria de Opções Reais em análise de projetos é, portanto, de grande importância na implantação de inovações. O objetivo desta dissertação é, com o estudo aprofundado do tema proposto, desenvolver um modelo abstrato (framework) a partir do qual é possível construir sistemas gerenciais que utilizem opções reais como ferramenta de análise. A partir desse modelo será desenvolvido um protótipo capaz de analisar opções reais de parada temporária (pausa), de abandono e de troca por uma nova tecnologia. Esse protótipo poderá determinar o valor de um projeto flexível (i.e.que permite mudanças ao longo de seu desenvolvimento) e o valor quantitativo da opção, ou seja, da ação gerencial.
This Masters Thesis presents a research on the Real Options Theory, a subject not yet very well known to the industrial project analysis area but increasingly being considered of most importance to the pricing and selection of new projects. This theory deals with uncertainty, flexibility and the manager`s capability to take decisions about projects. Nowadays, the competitive interactions and the technological advances occur in a everincreasing pace. Corporations need to be flexible and rapidly react to changes in order to avoid endangering their established market positions. The use of traditional analysis techniques, which do not take into account the managements actions, has been making large corporations loose their competitive market positions. The further development of the Real Options Theory in the context of project analysis is, thus, of great importance to applying innovations. The objective of this thesis is to, with the deeper study of the subject at hand, conceive an abstract model (framework) that can be instantiated to management systems that utilize real options as an analysis tool. A prototype capable of analyzing pause, stop and switch use options will be developed as a proof of concept. The software will be able to determine the value of a flexible project (i.e. one that allows for changes along its life time) and the quantitative value of the option (management action).

While a lot of time and resources have been placed into transceiver design, due to the pace of a conventional engineering design process, the design of a power amplifier is often completed using scattered resources; and not always in a methodological manner, and frequently even by an iterative trial and error process. In this thesis, a research question is posed which enables for the investigation of the possibility of streamlining the design flow for power amplifiers. After thorough theoretical investigation of existing power amplifier design methods and modelling, inductors inevitably used in power amplifier design were identified as a major drawback to efficient design, even when examples of inductors are packaged in design HIT-Kits. The main contribution of this research is engineering of an inductor design process, which in-effect contributes towards enhancing conventional power amplifiers. This inductance search algorithm finds the highest quality factor configuration of a single-layer square spiral inductor within certain tolerance using formulae for inductance and inductor parasitics of traditional single-π inductor model. Further contribution of this research is a set of algorithms for the complete design of switch-mode (Class-E and Class-F) power amplifiers and their output matching networks. These algorithms make use of classic deterministic design equations so that values of parasitic components can be calculated given input parameters, including required output power, centre frequency, supply voltage, and choice of class of operation. The hypothesis was satisfied for SiGe BiCMOS S35 process from Austriamicrosystems (AMS). Several metal-3 and thick-metal inductors were designed using the abovementioned algorithm and compared with experimental results provided by AMS. Correspondence was established between designed, experimental and EM simulation results, enabling qualification of inductors other than those with experimental results available from AMS by means of EM simulations with average relative errors of 3.7% for inductors and 21% for the Q factor at its peak frequency. For a wide range of inductors, Q-factors of 10 and more were readily experienced. Furthermore, simulations were performed for number of Class-E and Class-F amplifier configurations with HBTs with ft greater than 60 GHz and total emitter area of 96 μm² as driving transistors to complete the hypothesis testing. For the complete PA system design (including inductors), simulations showed that switch-mode power amplifiers for 50 Ω load at 2.4 GHz centre frequency can be designed using the streamlined method of this research for the output power of about 6 dB less than aimed. This power loss was expected, since it can be attributed to non-ideal properties of the driving transistor and Q-factor limitations of the integrated inductors, assumptions which the computations of the routine were based on. Although these results were obtained for a single micro-process, it was further speculated that outcome of this research has a general contribution, since streamlined method can be used with a much wider range of CMOS and BiCMOS processes, when low-gigahertz operating power amplifiers are needed. This theory was confirmed by means of simulation and fabrication in 180 nm BiCMOS process from IBM, results of which were also presented. The work presented here, was combined with algorithms for SPICE netlist extraction and the spiral inductor layout extraction (CIF and GDSII formats). This secondary research outcome further contributed to the completeness of the design flow. All the above features showed that the routine developed here is substantially better than cut-and-try methods for design of power amplifiers found in the existing body of knowledge.
Thesis (PhD(Eng))--University of Pretoria, 2011.
Electrical, Electronic and Computer Engineering
unrestricted

A channel change in digital television is usually conducted at a reference frame, which are sent at certain intervals. A higher compression ratio could however be obtained by sending reference frames at arbitrary long intervals. This would on the other hand increase the average channel change time for the end user. This thesis investigates various approaches for reducing the average channel change time while using arbitrary long intervals between reference frames, and presents an implementation and evaluation of one of these methods, called Baydec.

The approach of Baydec for solving the channel switch problem is to statistically estimate what the original image looked like, starting with an incoming P-frame and estimate an image between the original and current image. Baydec gathers statistical data from typical video sequences and calculates expected likelihood for estimation. Further on it uses the Simulated Annealing search method to maximise the likelihood function.

This method is more general than the requirements of this thesis. It is not only applicable to channel switches between video streams, but can also be used for random access in general. Baydec could also be used if an I-frame is dropped in a video stream.

However, Baydec has so far shown only theoretical result, but very small visual improvements. Baydec produces images with better PSNR than without the method in some cases, but the visual impression is not better than for the motion compensated residual images. Some examples of future work to improve Baydec is also presented.

This thesis addresses the issues of network topology mapping, where the network consists of multiple Cisco devices. It includes theoretical knowledge in this field and closely describes possible solutions to this problem. It explains the process of design and implementation of this kind of network mapping software by chosen means. Correct function of the created application is tested on a virtual network.

Allpass filters are commonly employed in many applications to perform group delay equalisation in the passband. They are non-minimum phase by definition and are characterised by poles and zeros in mirror-image symmetry. SI allpass filters of both cascade biquad and bilinear-LDI ladder types have been in existence. These were implemented using Euler based integrators. Cascade biquads are known to have highly sensitive amplitude responses and Euler integrators suffer from excess phase. The equalisers that are proposed here are based on bilinear integrators instead of Euler ones. Derivation of these equalisers can proceed from either the s-domain, or directly from the z-domain, where a prototype is synthesised using the respective continued-fractions expansions, and simulated using standard matrix methods. The amplitude response of the bilinear allpass filter is shown to be completely insensitive to deviations in the reactive ladder section. Simulations of sensitivities and non-ideal responses reveal the advantages and disadvantages of the various structures. Existing DI multirate filters have to date been implemented as direct-form FIR and IIR polyphase structures, or as simple cascade biquad or ladder structures with non-optimum settling times. FIR structures require a large number of impulse coefficients to realise highly selective responses. Even in the case of linear phase response with symmetric impulse coefficients, when the number of coefficients can be halved, significant overheads can be incurred by additional multiplexing circuitry. Direct-form IIR structures are simple but are known to be sensitive to coefficient deviations and structures with non-optimum settling times operate entirely at the higher clock frequency. The novel SI decimators and interpolators proposed are based on low sensitivity ladder structures coupled with FIR polyphase networks. They operate entirely at the lower clock frequency which maximises the time available for the memory cells to settle. Two different coupling architectures with different advantages and disadvantages are studied.

In this study, development of software, which can analyze and optimize an SRM by accurately calculating its performance, is aimed. Existing methods in the literature are investigated. Some studies for the calculation of performance use 2D field solutions and are known to be accurate
however, using field solutions is not feasible for the optimization purpose. So, a method based on a set of normalized permeance and force data are chosen for prediction of magnetizing characteristics. Selected methods are programmed into the software with a user friendly interface. The results from the software are compared with test results from an existing motor. It is found that the accuracy of the predictions is not acceptable if the effect of end winding leakage flux is not accounted for. An approach is proposed for accounting the end winding leakage. The software is modified accordingly. In this case, the results obtained are found to have good accuracy, compared with measurements. The SR motor design optimization problem is treated as a constrained wieght optimization problem. This problem is converted to an unconstrained optimization problem, by using the Augmented Lagrangian method. To decrease the computation time of some of the performance calculation algorithms, some modifications are made. These are described in the related sections. The derivatives for the optimization process are numerically calculated. The accuracy of the performance calculation is once again verified against test results at this stage. The optimization software is then used to optimize the design of an SR motor for a washing machine application. The results obtained are discussed.

The present methods of enterprise network security mostly operate under strict operational constraints; network operators are faced with solutions that are complex, proprietary and closed for innovation. Security policies in today's networks are mostly expressed and enforced using dynamic network traffic parameters, making their manageability difficult and expensive. Additionally, the security functionalities on today's network devices are mostly retrofitted onto existing ones (such as forwarding), thereby resulting in complex interactions - leading to a solution that is brittle, expensive to manage, and most of all, not open to enhancement. Software-Defined Networking (SDN) and Network Functions Virtualisation (NFV) are exciting technologies that create a paradigm shift in computer networking. These provide an exciting opportunity for the industry and researchers to solve some of the most persistent networking problems through creativity and improved ease of development, but also the rapid deployment of network services through automation and orchestration. This thesis presents a principle approach to the redesign of enterprise network access control architecture using 802.IX framework. We present FlowIdentity, an architecture that simplifies the engineering of network access control, lowering the cost of managing security policies, and increases deployment agility of network security services. The solution is a software-defined network access control architecture which redesigns the 802.lX framework and employs OpenFlow protocol, combining a novel authorization method by a stateful role-based firewall. Our solution presents a novel unification of policy definition and enforcement for network access control and endpoint vulnerability assessment. We present a proof-of-concept prototype and evaluate it for functionality, scalability and performance.

Water distribution networks are a fundamental part of any modern city and their daily operations constitute a significant expenditure in terms of energy and maintenance costs. Careful scheduling of pump operations may lead to significant energy savings and prevent wear and tear. By means of computer simulation, an optimal schedule of pumps can be found by an optimisation algorithm. The subject of this thesis is the study of pump scheduling as an optimisation problem. New representations of pump schedules are investigated for restricting the number of potential schedules. Recombination and mutation operators are proposed, in order to use the new representations in evolutionary algorithms. These new representations are empirically compared to traditional representations using different network instances, one of them being a large and complex network from UK. By means of the new representations, the evolutionary algorithm developed during this thesis finds new best-known solutions for both networks. Pump scheduling as the multi-objective problem of minimising energy and maintenance costs in terms of Pareto optimality is also investigated in this thesis. Two alternative surrogate measures of maintenance cost are considered: the minimisation of the number of pump switches and the maximisation of the shortest idle time. A single run of the multi-objective evolutionary algorithm obtains pump schedules with lower electrical cost and lower number of pump switches than those found in the literature. Alternatively, schedules with very long idle times may be found with slightly higher electrical cost. Finally, ant colony optimisation is also adapted to the pump scheduling problem. Both Ant System and Max-Min Ant System are tested. Max-Min Ant System, in particular, outperforms all other algorithms in the large real-world network instance and obtains competitive results in the smallest test network. Computation time is further reduced by parallel simulation of pump schedules.

Submitted by LÍGIA RODRIGUES PRETE (ligiaprete@gmail.com) on 2017-02-09T18:51:10Z No. of bitstreams: 1 ligia_rodrigues_prete.pdf: 7338300 bytes, checksum: 749589aef86e7cc89e556975ee3c0763 (MD5)
Approved for entry into archive by LUIZA DE MENEZES ROMANETTO (luizamenezes@reitoria.unesp.br) on 2017-02-14T17:42:37Z (GMT) No. of bitstreams: 1 prete_lr_dr_ilha.pdf: 7338300 bytes, checksum: 749589aef86e7cc89e556975ee3c0763 (MD5)
Made available in DSpace on 2017-02-14T17:42:37Z (GMT). No. of bitstreams: 1 prete_lr_dr_ilha.pdf: 7338300 bytes, checksum: 749589aef86e7cc89e556975ee3c0763 (MD5) Previous issue date: 2016-12-13
O consumo de energia no setor de Tecnologia da Informação e Comunicação (TIC) tem crescido exponencialmente nos últimos anos, em virtude da quantidade crescente de equipamentos para armazenamento e processamento de dados. O paradigma de Redes Definidas por Software (do inglês, Software-Defined Networking - SDN) e a arquitetura OpenFlow estão permitindo uma nova gama de aplicações e serviços para redes. A presente tese apresenta um estudo que aplica tecnologias SDN em um ambiente virtualizado com a federação GENI (Global Environment for Network Innovation). Neste trabalho foi desenvolvido um módulo no controlador Floodlight intitulado como Módulo Economia de Energia que emprega um algoritmo denominado MiNet (Mínima Rede) para a construção da Árvore de Extensão Mínima (do inglês, Minimum Spanning Tree - MST) sobre os componentes de comutação em redes. Este estudo apresenta três simulações em duas topologias de rede Fat Tree, sendo, uma com dez (FatTree10) e outra com vinte switches (FatTree20). Na primeira simulação foi realizada sem o módulo com a configuração padrão do controlador Floodlight para servir de comparação com os resultados de desempenho obtidos nas outras duas simulações. Já a segunda, com o Módulo Economia de Energia incluído no controlador, foi avaliada quanto aos custos iniciais nas ligações entre os switches. Na terceira, os custos nas ligações dos switches foram alterados para evidenciar que o Módulo Economia de Energia é capaz de recalcular uma nova Árvore de Extensão Mínima sobre os custos fornecidos e assim adaptar-se à rede para uma nova situação de atualização. Por meio de simulações realizadas, considerando somente as ligações entre os switches, sendo, quarenta portas Ethernet para a topologia menor e oitenta portas Ethernet para a topologia ampla, de acordo com os resultados alcançados, o módulo incorporado no Floodlight reduziu o consumo de energia final em 35% para a topologia FatTree10 e 32,5% na topologia FatTree20.
Energy consumption in the Information and Communication Technology (ICT) sector has grown exponentially recently, due to the increasing amount of equipment for data storage and processing. The paradigm of Software-Defined Networking (SDN) and OpenFlow architecture are enabling a new range of applications and services for networks. This thesis presents a study that applies SDN technologies in a virtualized environment with the GENI federation (Global Environment for Network Innovation). This paper developed a module in Floodlight controller titled Energy Saving Module employing an algorithm called MiNet (Minimum Network) for the construction of the Minimum Spanning Tree (MST) on the switching components in networks. This study presents three simulations in two network topologies Fat Tree, as it follows, a ten one (FatTree10) and another with twenty switches (FatTree20). In the first simulation, it was performed without the module with the default configuration of Floodlight controller to serve as a comparison with the performance results in the other two simulations. The second, with Module Energy Saver included in the controller, it evaluated the initial costs on the links between switches. In the third, the costs in the connections of the switches were changed to high light that the Energy Savings Module is able to recalculate a new Minimum Spanning Tree on the provided costs and thus adapt the network to a new update situation. Through the performed simulations, considering only the links between switches, as it is, forty Ethernet ports for smaller topology and eighty Ethernet ports for wide topology, according to the achieved results, the embedded module Floodlight reduced the final energy consumption to 35% FatTree10 topology and 32.5% FatTree20 topology.

Orientador: Ailton Akira Shinoda
Resumo: O consumo de energia no setor de Tecnologia da Informação e Comunicação (TIC) tem crescido exponencialmente nos últimos anos, em virtude da quantidade crescente de equipamentos para armazenamento e processamento de dados. O paradigma de Redes Definidas por Software (do inglês, Software-Defined Networking - SDN) e a arquitetura OpenFlow estão permitindo uma nova gama de aplicações e serviços para redes. A presente tese apresenta um estudo que aplica tecnologias SDN em um ambiente virtualizado com a federação GENI (Global Environment for Network Innovation). Neste trabalho foi desenvolvido um módulo no controlador Floodlight intitulado como Módulo Economia de Energia que emprega um algoritmo denominado MiNet (Mínima Rede) para a construção da Árvore de Extensão Mínima (do inglês, Minimum Spanning Tree - MST) sobre os componentes de comutação em redes. Este estudo apresenta três simulações em duas topologias de rede Fat Tree, sendo, uma com dez (FatTree10) e outra com vinte switches (FatTree20). Na primeira simulação foi realizada sem o módulo com a configuração padrão do controlador Floodlight para servir de comparação com os resultados de desempenho obtidos nas outras duas simulações. Já a segunda, com o Módulo Economia de Energia incluído no controlador, foi avaliada quanto aos custos iniciais nas ligações entre os switches. Na terceira, os custos nas ligações dos switches foram alterados para evidenciar que o Módulo Economia de Energia é capaz de recalcular uma nova Árvore d... (Resumo completo, clicar acesso eletrônico abaixo)
Doutor

This thesis deals with a theoretical analysis of the basic parameters of receivers, input circuit architecture and signal digitization. According to the specified assignment it is outlined block scheme of front end for software receiver with specified components and the total bilance is calculated. Individual parts of the system are designed and realized. This is a set of four input filters for bandwidths: short waves up to 30 MHz, 87,5-108 MHz, 144-148 MHz and 174-230 MHz. The main point of design is a circuit containing a low-noise amplifiers, switches, and two amplifiers with adjustable amplification. Mainly are used integrated circuits from Analog Devices corporation. To control the various switches and adjustable amplifiers was designed a separate panel, which is connected to the main circuit via a cable. In the last phase was the whole system and its components subjected to measurements. Thanks to a number of mounted SMA connectors it is possible to measure different parts of the system and we are able to modify it partially.

The thesis investigates the possibility to enrich standard mobile phone calls with cooperative web applications. Originating from the research field know as Computer Supported Cooperative Work (CSCW) this thesis report introduces and describes the implementation of several applications which can be used by the calling parties together during a phone call. Additionally, the report describes a proof-of-concept prototype for the Android platform, and discusses the performance of cooperative web application running on mobile devices in terms of network and CPU use. The conclusions of the thesis describe a prototype application addressing and implementing the requirements as described by the theory of computer supported collaborated work. The performance of the running application showed to be satisfactory, both regarding to network demand and processor use.

In this study, three different programs are developed for the analysis of the three-phase induction motor, single-phase capacitor type induction motor and switched reluctance motor. The programs are developed by using Pascal and C++ programming languages. In the performance calculations of motors, analytical methods are used and these methods are tested for accuracy. These programs have also capabilities to design an optimum motor, which meets a set of performance, material and manufacturing constraints while minimizing the weight or any other defined objective function. In addition, in this study, an optimization tool is used to obtain an appropriate optimization method for the design of different types of motors. The software is tested over different commercial motors. The results illustrates that the performance calculations and optimization approach of the programs lead to good results.

En raison de ses avantages inhérents, tels que son faible coût, sa fiabilité élevée, sa capacité de fonctionnement à grande vitesse et en environnements difficiles, la machine à réluctance variable (MRV) est une solution attrayante pour l'industrie automobile. Cependant, la traction automobile est une application pour laquelle le comportement acoustique du groupe motopropulseur doit être particulièrement considéré, dans l'optique de ne pas dégrader le confort des passagers. Afin de rendre la MRV compétitive pour cette application automobile, le travail présenté se concentre sur plusieurs méthodes de contrôle cherchant à améliorer le comportement acoustique des MRV en réduisant les vibrations d'origine électromagnétique. Un modèle multi-physique électromagnétique / mécanique semi-analytique est proposé à partir de résultats de simulation numérique obtenus par la méthode des éléments finis. Ce modèle multiphysique est composé de modèles électromagnétiques et structurels, qui sont reliés par la composante radiale de la force électromagnétique. Deux méthodes de contrôle sont ensuite proposées. La première réduit la vibration en faisant varier l'angle de coupure du courant, la fréquence du la variation étant basée sur les propriétés mécaniques de la structure MRV. De plus, une fonction aléatoire uniformément distribuée est introduite pour éviter une composante fréquentielle locale de forte vibration. Une seconde méthode est basée sur le contrôle direct de la force (DFC), qui vise à obtenir une force radiale globale plus douce pour réduire les vibrations. Un adaptateur de courant de référence (RCA) est proposé pour limiter l'ondulation de couple introduite par le DFC, provoquée par l'absence de limitation de courant. Cette seconde méthode de réduction des vibrations appelée DFC & RCA est évaluée par des tests expérimentaux utilisant un prototype de MRV 8/6 afin de montrer sa pertinence. Une solution de partitionnement hardware/software est proposée pour implémenter cette méthode sur une carte FPGA utilisée en combinaison avec un microprocesseur
Due to its inherent advantages Switched Reluctance Machine (SRM) are appealing to the automotive industry. However, automotive traction is a very noise sensitive application where the acoustic behavior of the power train may be the distinction between market success and market failure. To make SRM more competitive in the automotive application, this work will focus on the control strategy to improve the acoustic behavior of SRM by vibration reduction. A semi-analytical electromagnetic/structural multi-physics model is proposed based on the simulation results of numerical computation. This multi-physics model is composed by electromagnetic and structural models, which are connected by the radial force. Two control strategies are proposed. The first strategy to improve the acoustic behavior of SRM by vibration reduction. A semi-analytical electromagnetic/ structural multi-physics model is proposed based on the simulation results of numerical computation. This multi-physics model is composed by electromagnetic and structural models, which are connected by the radial force. Two control strategies are proposed. The first one reduces the vibration by varying the turn-off angle, the frequency of the variable signal is based on the mechanical property of switched reluctance machine. Besides, an uniformly distributed random function is introduced to avoid local high vibration component. Another one is based on the Direct Force Control (DFC), which aims to obtain a smoother total radial force to reduce the vibration. An reference current adapter (RCA) is proposed to limit the torque ripple introduced by the DFC, which is caused by the absence of the current limitation. The second vibration reduction strategy named DFC&RCA is evaluated by experimental tests using an 8/6 SRM prototype. A hardware/software partitioning solution is proposed to implement this method, where FPGA board is used combined with a Microprocessor

Optical communications systems operate at the limits of their margins to respond to increasing capacity demands. Some of the signal processing functions required must soon operate at speeds beyond electronic implementation. Optical signal processors are fundamentally analog which requires precise control of the operating state. Programmable optical components are consequently essential. The thesis explores and elucidates the properties of meshes of generalized Mach-Zehnder interferometers (GMZIs) amenable to silicon (Si) photonics integration that are based on multimode interference couplers with programmability achieved via voltage controlled phase-shift elements within the interferometer arms to perform a variety of finite impulse response (FIR) and infinite impulse response (IIR) signal processing functions. The thesis presents a novel class of integrated photonic phased array systems with a single-stage, multistage, and feedback architectures. The designed photonic integrated systems utilize nano-electromechanical-system (NEMS) operated phase shifters of cascaded free suspended slot waveguides that are compact and require a small amount of power to operate. The structure of the integrated photonic phased array switch (IPPAS) elements is organized such that it brings the NEMS-operated phase shifters to the exterior sides of the construction; facilitating electrical connection. The transition slot couplers used to interconnect the phase shifters to the rest of the silicon structure are designed to enable biasing one of the silicon beams of each phase shifter from an electrode located at the side of the phase shifter. The other silicon beam of each phase shifter is biased through the rest of the silicon structure of the fabric, which is taken as a ground. Phased array processors of 2×2 and 4×4 multiple-input-multiple-output (MIMO) ports are conveniently designed within reasonable footprints native to the current fabrication technologies. The response of the single-stage 4×4 broadband IPPAS element is determined, and its phase synthesis states required for single-throw, double-throw and broadcast routing operations are predicted. The transmission responses of the single-stage wavelength division multiplexing (WDM) processors of 2×2 and 4×4 MIMO ports are simulated. The wavelength steering capability of the transmission interferograms by applying progressive phase shifts through the array of NEMS-operated phase shift elements of the single-stage 4×4 WDM (de)multiplexer is demonstrated. The advantages of cascading broadband and WDM phased array sections are articulated through several study cases. Five different cascaded phased array architectures are trialed for the construction of non-blocking 4×4 IPPAS broadband switches that are essential elements in the construction of universal photonic processors. A cascaded 2×2 WDM (de)multiplexer that can set the bandwidth of the (de)multiplexed cyclic channels into a binary number of programmable values is demonstrated. The envelope and wavelength modulations of the transmission responses utilizing a cascaded forward structure of three 2×2 sections that can be utilized for the (de)multiplexing of different bandwidth channels are demonstrated providing individual wavelength steering capability of the narrowband and wideband channels and the individual wavelength steering capability of the slow envelope and wavelength modulating functions. Innovative universal 2×2 and 4×4 cascaded phased array processors of advanced high-order architectures that can function as both non-blocking broadband routers and tunable WDM (de)multiplexers with spectrum steering and bandwidth control of the (de)multiplexed demands are introduced. The multimode interference (MMI) coupler is utilized for the construction of several IIR feedback photonic processors. Tunable photonic feedback processors have the advantage of using less number of MMI couplers compared to their counterparts of FIR forward-path processors saving on the footprint and loss merits. A passive feedback 2×2 (de)multiplexer made of a 4×4 MMI coupler and two loopback paths is proposed. The inclusion of an imbalance in the lengths of the loopback paths of the same symmetrical feedback (de)multiplexer is demonstrated to achieve wavelength modulation of the (de)multiplexed transmission responses that are useful for the (de)multiplexing of different bandwidth channels. Several newly introduced IIR feedback architectures are demonstrated to function similarly as their counterparts of FIR forward-path processors as binary bandwidth variable (de)multiplexers, envelope and wavelength modulation (de)multiplexers, and universal feedback processors. The investigation provided in this thesis is also supported with dynamic zero-pole evolution analysis in the complex plane of analysis of the studied FIR and IIR photonic processors to enhance understanding the principle of operation. This research expands the prospective for constructing innovative silicon-on-insulator (SOI) based optical processors for applications in modern optical communication systems and programmable elastic optical networks (EONs).

碩士
國立臺灣科技大學
電子工程系
104
In this paper, primarily for the design is implement of hardware acceleration switch. Experimental environment is based on the Xilinx ZC706 development platform and 4-port Ethernet expansion card. ZC706 platform feature is integration of embedded processors and field programmable gate array hardware array (FPGA). It is combines the advantages of software and hardware. Through software and hardware co-design approach to achieve low-power and high-performance. In this paper, the design approach, the main use of FPGA hardware can be for a specific network environment, network performance to achieve the specified requirements, and software, the use of an embedded processor switches to communicate with the central controller SDN, can effectively reduce power high consumption problem.

碩士
國立交通大學
資訊科學與工程研究所
104
The software defined network (SDN) has been widely studied and rapidly developed in recent years. SDN can achieve flexible network management by using the controller to access the flow table inside a switch. The flow table, implemented by Ternary Content Addressable Memory (TCAM), is expensive, power hungry and occupies large silicon space. These characteristics limit the size of a flow table. The limited size of the flow table may result in the flow table overflow problem. The state of the art, such as FTRS, still has high probability of occurrence of flow table overflow. To conquer this problem, we propose a mechanism named In-switch Dynamic Flow Aggregation (IDFA). The IDFA resides in the OpenFlow switch and can be divided into three components: dynamic threshold adjustment, redundant flow entry insertion and validation, and flow aggregation algorithm. The IDFA can be dynamically triggered in order to achieve fewer trigger times and shorter flow aggregation convergence time. In the IDFA, redundant flow entries are inserted to speed up flow aggregation convergence time. In the flow aggregation algorithm, we propose two novel techniques, degradation and repermutation, to aggregate flows effectively and still maintain semantic equivalence. Evaluation results show that, the average compression ratio of the IDFA in the fat-tree topology of a LAN environment is 26.3% better than that of the FTRS. The average compression ratio of the IDFA in the fat-tree topology of a random IP environment is 43% better than that of the FTRS. The average flow aggregation convergence time of the IDFA in the fat-tree topology is 84% shorter than that of the FTRS.

Tese de mestrado, Engenharia Informática (Arquitetura, Sistemas e Redes de Computadores) Universidade de Lisboa, Faculdade de Ciências, 2019
O tráfego na internet está a crescer a um ritmo elevado. A ocorrência de Gargalos é, então, cada vez mais, uma ocorrência comum, resultando em atrasos no transporte de informação e em ineficiências. Isto é um problema em parte decorrente do paradigma tradicional “store and foreward”. Quando um pacote chega a um nó da rede, é armazenado numa fila de espera enquanto aguarda por uma decisão de encaminhamento. Quando existe tráfego elevado, as filas de pacotes crescem e os atrasos aumentam (assim como as perdas de pacotes). O conceito de Codificação na Rede procura oferecer um paradigma. A ideia fundamental é a seguinte: à capacidade de armazenamento e encaminhamento. Quando existe tráfego elevado, as filas de pacotes crescem e os atrasos aumentam (assim como a perda dos pacotes).O Conceito de Codificação na Rede procura oferecer uma alternativa de paradigma. A ideia fundamental é a seguinte: à capacidade de armazenamento e encaminhamento é adicionada aos nós a capacidade de combinar pacotes. Com esta Técnica é possível aumentar as taxas de transferência de informação, assim como a resiliência da rede. Para se entender melhor o conceito vajamos um exemplo. Considere um nó A e um B que comunicam através de um ponto de acesso S, num ambiente sem fios. Vejamos as transmissões necessárias para A enviar a e B, e para B enviar mensagem b para A, usando o modelo tradicional:1A envia a para S 2B envia b para S 3S faz broadcast de a para os dois nós4S faz broadcast de b para os dois nós Como se pode observar, foram necessárias quatro transmissões ao todo. Ao aplicarmos codificação na rede podemos poupar no número de transmissões da seguinte forma:1A envia a para S2B envia b para S3S combina as duas mensagens aplicando um XOR sobre elas e envia o resultado, a b, para A e BNo entanto, o exemplo demonstrado acima é um caso base de Linear Network Coding (LNC). Esta técnica de codificação consiste em dar capacidade, a cada nó da rede, de gerar novos pacotes através de combinações lineares de pacotes recebidos anteriormente, multiplicando-os por coeficientes escolhidos de um dado campo finito, sendo o mais comum de tamanho 28. Já no exemplo anterior, em que foi utilizado uma técnica de codificação através do XOR para codificar dois pacotes, o tamanho do campo finito era de 2. Sendo este, então, um caso particular.Porém, o LNC requere que os coeficientes utilizados nas combinações lineares sejam definidos e computados à prori por todos os nós da rede através de um algoritmo e de informação partilhada. Estamos, então, perante uma Limitação desta técnica que introduz um custo. Random Linear Network Coding (RLNC), uma variante da técnica de LNC, permite ultrapassar essa limitação. Isto é possível devido à sua natureza aleatória, significando que os coeficientes empregues nas combinações lineares são gerados deforma aleatória dado um certo campo finito. Esta propriedade garante com uma dada probabilidade, desde que o campo finito tenha um tamanho suficiente largo, de que as combinações lineares geradas sejam independentes entre si, com o intuito de aumentar esta probabilidade, RLNC introduz ainda a capacidade de recodificar pacotes, isto é, codificar pacotes que já foram codificados por outro nó na rede. Assim, quando o nó destinatário recebe uma quantidade suficiente de pacotes codificados que sejam linearmente independentes é possível descodificar os pacotes resolvendo as combinações lineares. Para tal, o destinatário tem de ter conhecimento dos coeficientes empregues nas combinações lineares. Então, por norma, em RLNC os coeficientes empregues nas combinações lineares. Então por norma, em RLNC os coeficientes são anexados ao cabeçalho do pacote, após a codificação deste, para que os coeficientes sejam levados até ao destinatário. Tanto a operação de codificação como de descodificação introduzem uma certa complexidade computacional proporcional ao tamanho dos dados a serem transmitidos. A técnica designada por Generation-based RLNC, permite solucionar este problema. Esta consiste em dividir em grandes quantidades de dados em blocos mais pequenos, chamados gerações. Então, tanto a operação de codificação como a de descodificação são aplicadas por geração e não na totalidade de dados. Existe uma grande quantidade de trabalho teórico relacionado com Network Coding e implementações ao nível da Camada aplicacional. No entanto, não existe nenhum trabalho concreto cujo objetivo tenha sido desenvolver e implementar uma solução de Network Coding diretamente no plano de dados da rede. Isto resulta do facto de os switches serem hardware especializado com função única, não permitindo a codificação de pacotes.Recentemente, no entanto, foram desenvolvidos switches programáveis, que removem esta restrição. Ao contrário dos switches tradicionais que são dispositivos fechados que seguem um conjunto de protocolos definidos pelo fabricante, estes switches permitem ao operador definir exatamente o processamento dos pacotes. Entretanto foi desenvolvida também uma linguagem de alto nível para programar estes novos switches programáveis, designada como P4. Em Suma, uma das limitações de todas as soluções de codificação em rede existentes prende-se com o facto de serem implementações em software. Esta Limitação é resultado de inflexibilidade dos planos de dados em hardware (switches e routers) tradicionais, que não permitem a combinação de pacotes. Nesta dissertação começamos a atacar este problema através da exploração dos novos switches em hardware programáveis, desenhando e implementando um switch que executa Random Linear Network Coding usando a versão mais recente da linguagem de programação de switches P4 (especificamente, P4_16). A avaliação da nossa solução oferece boas perspetivas para a possibilidade de deployment em hardware destas técnicas de codificação em rede, mas apresente também alguns dos desafios que permanecem em aberto para explorar em trabalho futuro.

碩士
輔仁大學
資訊管理學系
100
The main purpose of this study is the supplier's point of view, while standing on the client user's perspective, to explore the key factors of customers in the software conversion process. Dimensions of relationship quality, service quality, corporate image, hoping to find customers in the software conversion process to better fit into the customer needs to meet customer and user satisfaction, and then through software conversion success, to enhance customer loyalty. Enterprise software conversion often involves organizational change, this study, relationship quality, user satisfaction, testing enterprise software vendor, product, corporate image whether there is a positive relationship, as well as enterprise software conversion process, software switch costs, perceived risk has a positive relationship to be explored.In this study, after data analysis, the following conclusions: the results of the study, relationship quality and products and corporate image are a positive relationship with the user satisfaction. The enterprise software vendor, from the above three key factors to improve user satisfaction, in order to maintain the customer relationship to ensure that the customer is not lost (switch software). In addition, the cost of software conversion study cost, no positive effect on user loyalty, and no positive impact on the cost of software conversion costs to build the level of user loyalty. In other words, from the results of this study, users are not satisfied with the case, will not count the level of switching costs, to select a different enterprise software vendor. This study has far-reaching managerial implications for software vendors.

碩士
朝陽科技大學
資訊與通訊系
104
Software-Defined Networking (SDN) becomes an attractive issue because it makes protocols programmable and management centralized by the controller of Control layer, which is isolated from Data layer. Then, in Data layer, the network facility only processes the delivery of flow entries by using switches. Therefore, SDN not only simplifies the process and solves numerous issues from managing facilities, but also takes advantage of the flexibility of action field to assign output flow of entries. As Internet of Thing (IoT) spring up, many flow entries transmit data by different priorities in the network. However, in the traditional network, the important packet is labeled in the header of packet when it is delivered because of the highest priority among of others. To deal with the configuration of those packets, a large-sized and complex scheduler addressed by algorithm is proposed. It may have difficulty to apply on networking hardware because of the complications from the process. Therefore, in this study, a low costed SDN platform used Ryu software compiled SDN Application is proposed to achieve the switch port priority control. We show that the switch port with high priority can achieve higher bandwidth and throughput than others. Furthermore, our proposed approach does not consider that a scheduler of that size may be complex to implement in hardware, and makes management and transmission more efficient to derive more applications under SDN.

碩士
國立交通大學
網路工程研究所
105
In the software defined network (SDN), the flow table of an OpenFlow switch is usually implemented by the ternary content addressable memory (TCAM), which can perform rule matching in a linear speed. However, the TCAM has limited capacity since it is extremely costly and power-hungry. Once the TCAM is out of memory, new rules will not be able to be inserted into the flow table and thus their corresponding flows will not be forwarded. Such a problem is called the flow table overflow problem. To address the problem, a state-of-the-art, the flow-driven rule caching optimization (FDRC), performs a rule replacement scheme according to the estimated next-packet arrival time of each flow; however, it may remove a rule whose packets will soon arrive at a switch, especially when the network is unstable. This thesis proposes a new TCAM management scheme named in-switch rule caching and replacement algorithm (IRCR) to better deal with the flow table overflow problem. The IRCR adopts the concept of caching and replaces a rule according to the expected number of incoming matched flows (EIMF), which can be derived from the inter-arrival time distribution models of the corresponding flows. The IRCR is designed to be an in-switch application to avoid link delays between the controller and switches. We have evaluated the proposed IRCR and the hit ratio of IRCR is 26.3%, 14% and 15.3% higher than three classical replacement algorithms, FDRC, LRU and FIFO, respectively. The IRCR only takes 34.7 milliseconds out of 1 second to compute the EIMFs of 1600 rules.

碩士
國立臺灣科技大學
資訊管理系
103
In these recent years, Software Defined Network (SDN) is predicted to be the future network. The basic idea of SDN is data plane and control plane which are separated unlike traditional network that has both planes in one device. Therefore, the controller has key controlling functions of its SDN environment. Many researchers discuss where to place the controller in order to get the optimal delay. However, these researches only focus on switches that are connected to one controller. There are some advantage for switches to connect to more than one controller such as efficient load balance, fail-over and reliability. Thus, we will discuss the controller placement where switches can connect to multiple controllers. This is important to answer the controller locations in a topology and percentage of switch connecting to each controller distribution load from a transmission delay view. Therefore, we will calculate the percentage and location by Switch to Multiple Controller Placement (SMCP). The result shows that SMCP can reduce 20-30% of transmission delay compared to random placement.

碩士
國立交通大學
資訊科學與工程研究所
103
In this thesis, we design, implement, and evaluate the functions and performance of a parallel-running comparison system that is built on OpenVswitch software switch. Parallel running is a very important method to change from an existing system to a new system. The conversion usually occurs when the technology of the old system is outdated and a new system is needed to be installed to replace the old one. During parallel running, both the old and new systems are running side by side and their behaviors are compared against each other until the users are certain that the new and old systems behave exactly the same. At that time, the old system will be removed and the new system will totally replace the old system. In this thesis, we use the OpenVswitch software system to design and implement a comparison system for parallel running. Our evaluation results show that this tool is very useful and of high performance.

碩士
國立交通大學
網路工程研究所
104
In this thesis, we design, implement, and evaluate the performance of software OpenFlow flow entry counters on a commodity switch. In the SDN technology, the protocol that is most widely used for the SDN controller to control network switches is the OpenFlow protocol. The OpenFlow protocol requires that each flow entry in the flow table(s) of an OpenFlow switch have two counters to count the number of packets that match the flow entry and the length of these packets in bytes. With these information, the SDN controller can easily calculate the most recent bandwidth usage of any flow to perform advanced tasks such as traffic engineering. These flow entry counters are implemented in hardware and their number needs to be very large to support a large flow-based SDN network. Although these hardware counters are very useful and operate very fast, they greatly increase the cost of an OpenFlow switch. In addition, due to the limited size of the switching ASIC used in the OpenFlow switch, the number of hardware counters cannot scale to a large number. To overcome these drawbacks, in this work we design and implement these hardware counters as software counters on a commodity switch and evaluate their performance. This thesis reports our experiences in this work and the important performance findings that we obtained from this work.

碩士
國立臺灣科技大學
電子工程系
105
Finally, the experimental results show that the proposed stackable OpenFlow switch can effectively interconnect switches, as it can achieve effective packet switching for cross the switch. Furthermore, it also can guarantee quality of network resource.

碩士
龍華科技大學
資訊管理系碩士班
103
Recently, smart phones bring up the use of applications dramatically that smart phone owners download and use the APP with communication service such as Facebook. Due to the sudden rise of Line APP, the registered users of the leading virtual community Facebook are flown. The issues of switching behavior from one mobile instance messenger software to another are noticed by practitioners and scholars. Survey methodology was adopted in the study and the data were collected from users who own both accounts of Facebook and Line. A sample data set with 345 respondents is collected from a website and the multiple regression method is applied to analyze the empirical data. This study adopts the perspective of switching cost to explore the related factors impacting on switch intention. Inertia, uses and gratification, conformity, perceived ease of use, perceived usefulness, and sticker media richness were demonstrated in the research model. The research results show that inertial, conformity perceived usefulness, uses and gratification are critical factors influencing the intention of switch-ing mobile instance messenger software. The theoretical and management implications are provide at the end of articles.

碩士
中華大學
資訊工程學系
107
Today's society is an era of information expansion. Everyone can't do without the Internet access function of mobile phones and computers. Internet access has become the normal behavior of modern people, so the demand for network use has increased greatly. The OSI network model has been with us for many years, and each layer of Layer will communicate with the isolated Layer. The ultimate goal is to send the completed packet to the destination. Why talk about the OSI network model? The reason is that there are a lot of things to be set in the network, such as Routing, VLAN, QoS, STP, and LACP. In a large network, the network administrator needs to mobilize these settings from time to time. Of course, literally It's very easy, but it's very complicated in the real environment. The network administrator needs a certain amount of manpower and time to mobilize the configuration. Therefore, the (SDN) software defines the network to be a systematic central control method. It is easier and easier for administrators to manage network systems. SDN network, this new network architecture separates and centralizes the control plane, enabling network devices to only pass packets and simplify device management and configuration. The OpenFlow switch is implemented as one of the products of the SDN network, providing a unified communication interface for the control plane to communicate with the data plane. OpenFlow switch factory's Match condition, each customer will have different needs, but there are many combinations of Match conditions, which will inevitably affect product development and verification time. This paper designs fairness under a test time limit and considering the needs of many customers. Sexual test plans to help decision-makers make the most appropriate decisions early. Keywords: SDN, OpenFlow, Test Time Limit Requirements, Consideration of Multi-customer Fair Design Issues

碩士
國立臺北科技大學
資訊工程系研究所
105
Due to unprecedented and diversified network services and applications created, the network traffic grow explosively. The concept of the Software-Defined Network(SDN) reverses the view of traditional network control and transmission mode. It separates a network into control and data plane so that the network administrator can grasp the more complete information of the internet. Although there were many researches on SDN congestion control, they were based on modifying existing agreements or mechanisms and transplanting to SDN. The design of congestion control that adapts to SDN architecture is still unseen. This research proposed a novel SDN transmission system, which can control all the data in this network system and carry out the traffic control by access switch acting as the traffic lights. Those special access switches were called “edge switches”. Then the thesis designed a dedicated congestion control mechanism in edge switches in order to completely manage the flows in the SDN instead of relying on special protocols or machines. The proposed SDN architecture can regulate both TCP (Transmission Control Protocol) and UDP (User Datagram Protocol) flows and resolve the congestion efficiently. The performance was examined through intensive experiments under various traffic conditions and the results showed that it was approaching that of TCPs ECN (Explicit Congestion Notification) mechanism.

Microelectromechanical systems (MEMS) depend on mechanical deformation to sense their environment, enhance electrical circuitry, or store data. Nonlinear forces arising from multiphysics phenomena at the micro- and nanoscale -- van der Waals forces, electrostatic fields, dielectric charging, capillary forces, surface roughness, asperity interactions -- lead to challenging problems for analysis, simulation, and measurement of the deforming device elements. Herein, a foundation for the study of mechanical deformation is provided through computational and experimental studies of MEMS microcantilever capacitive switches. Numerical techniques are built to capture deformation equilibria expediently. A compact analytical model is developed from principle multiphysics governing operation. Experimental measurements support the phenomena predicted by the analytical model, and finite element method (FEM) simulations confirm device-specific performance. Altogether, the static multistability and quasistatic performance of the electrostatically-actuated switches are confirmed across analysis, simulation, and experimentation.

The nonlinear multiphysics forces present in the devices are critical to the switching behavior exploited for novel applications, but are also a culprit in a common failure mode when the attractive forces overcome the restorative and repulsive forces to result in two elements sticking together. Quasistatic operation is functional for switching between multistable states during normal conditions, but is insufficient under such stiction-failure. Exploration of dynamic methods for stiction release is often the only option for many system configurations. But how and when is release achieved? To investigate the fundamental mechanism of dynamic release, an atomic force microscopy (AFM) system -- a microcantilever with a motion-controlled base and a single-asperity probe tip, measured and actuated via lasers -- is configured to replicate elements of a stiction-failed MEMS device. Through this surrogate, observable dynamic signatures of microcantilever deflection indicate the onset of detachment between the probe and a sample.

The Catalyst 6500 is a modern commercial switch, capable of processing millions of packets per second through the utilization of specialized hardware. One of the main hardware components aiding the switch in performing its task is the Ternary Content Addressable Memory (TCAM). TCAMs update themselves with data relevant to routing and switching based on the traffic flowing through the switch. This enables the switch to forward future packets destined to a location that has already been previously discovered - at a very high speed. The problem is TCAMs have a limited size, and once they reach their capacity, the switch has to rely on software to perform the switching and routing - a much slower process than performing Hardware Switching that utilizes the TCAM. A framework has been developed to analyze the switch’s performance once the TCAM has reached its capacity, as well as measure the penalty associated with a cache miss. This thesis concludes with some recommendations and future work.

碩士
國立臺北教育大學
資訊科學系碩士班
107
Each traditional network switch can resolve the packet by itself, but this way cannot dynamically consider the overall network status into the selection path, so it is still possible to stream the data into the blocked link. The SDN support flexible scheduling and programmable control of network resources. It separates the Control Plane from the Data Plane. The controller is responsible for parsing and processing the packets. When the Data Plane receives the custom rules of the Control Plane, Data Plane forwarding packets according to the output port specified by its rules. It is know from the research of many scholars that multi-path transmission can improve the network transmission efficiency. Although OpenFlow can also implement packet-oriented multipath transmission, but OpenFlow is used by the controller to set the processing rules of the switch to the packet, when the controller fails and cannot be connected with the switch, the multipath transmission will be invalid. This research based on the P4 architecture and used the approach of placing the control layer in the switch that could be avoids the aforementioned problem. When the packet enters the P4 switch, the P4 Register, P4 Meter, or P4 Counter accesses it... The various states of the packets check the table in a stylized control manner and execute the corresponding action, and the random function in the actions determines which output port the packet should be send. In the same time, use the P4 simple_switch_CLI to support the cmd module written in python language, to define the probability of sending packets to different output ports. So that the P4 switch in the network can offload data packets and transmit them through different paths with different chances. At the same time, use the MRI tool belonging to the SDN Data Plane to collect the state information of the network topology. When the switch finds that one of the output paths is congestion, which can be programmable control the packets transmission to the specified output port. Simulation results showed that the proposed multipath transmission mechanism in addition to avoiding the problem of data transmission interruption due to single transmission path failure, it can improve transmission efficiency, reliability, and network throughput.

Tese de mestrado, Engenharia Informática (Arquitectura, Sistemas e Redes de Computadores), Universidade de Lisboa, Faculdade de Ciências, 2017
Atualmente, as redes de computadores seguem um paradigma tradicional de store-andforward, ou seja, os dispositivos de rede fazem armazenamento, encaminhamento e/ou replicação de pacotes recebidos, sem os modificar. No virar do milénio, surgiu um artigo seminal [24], no qual foi demonstrado teoricamente que a combinação da informação proveniente de diversos pacotes, permite aumentar a capacidade de uma rede relativamente à capacidade máxima, alcançada por simples encaminhamento. Este resultado representou o nascimento de uma área promissora de investigação, conhecida como Codificação na Rede (Network Coding). A ideia é permitir que os nós intermédios da rede, possam aplicar uma função de codificação sobre o conteúdo dos pacotes antes do seu encaminhamento, proporcionando assim um novo paradigma de store-code-forward. A família de técnicas tradicionais pode ser divida em duas categorias, com propósitos distintos. Codificação na Origem (Source Coding) com o objetivo de comprimir a informação enviada, e Codificação no Canal (Channel Coding) para compensar perdas e alteração de informação em canais ruidosos. Com codificação na rede, surge oportunidade para a definição de técnicas mais elaboradas e que visam outros propósitos. Deste modo, as técnicas de codificação tradicionais podem ser extendidas para além da codificação de pacotes em nós de origem, e da descodificação em nós de destino. De um ponto de vista geral, a codificação na rede tem potencial para melhorar a taxa de transferência de informação na rede; aumentar a resiliência contra perda de pacotes, interrupção de canais e nós da rede; e aumentar a segurança contra ataques maliciosos que visam a captura, interpretação e modificação de pacotes. Como técnica, a codificação na rede pode ser aplicada de dois modos distintos. Por um lado, sobre pacotes provenientes de um único fluxo de comunicação (intraflow network coding) e por outro, sobre múltiplos fluxos sem qualquer relação entre si (interflow network coding). A título de exemplo, se considerarmos dois fluxos que chegam a um switch por dois canais distintos, mas que contestam o mesmo canal de saída, temos um gargalo na rede. Usando codificação na rede, o switch pode aplicar, bit a bit, o Ou-Exclusivo (XOR) sobre dois pacotes (um de cada fluxo) e encaminhar o resultado. A taxa de transferência é melhorada, pois o switch necessita apenas de encaminhar um pacote codificado em vez de dois originais. É de salientar que, de forma a descodificar o pacote, o nó de destino tem de ter um dos pacotes originais usados na codificação. Portanto, as vantagens da codificação na rede estão dependentes da topologia da rede, da própria função de codificação utilizada, e do modo como é aplicada. Numa rede, um nó intermédio terá à partida acesso a vários pacotes. De forma a tirar máximo partido da técnica de codificação na rede, as funções de codificação utilizadas acabam por consistir num código linear (Linear Network Coding). A ideia é considerar todos os pacotes de uma mensagem a enviar (por exemplo, um ficheiro de texto, um vídeo, ou até um simples pedido HTTP) como um vetor de elementos de um dado campo finito. O tamanho de cada elemento, é dado pelo número de bits necessário para representar o maior valor desse campo. Se por exemplo o campo finito for 256, cada elemento terá 8 bits. A um vetor de elementos, damos o nome de símbolo. Associado a cada símbolo transmitido na rede, existe um vetor de coeficientes, necessário para codificação e descodificação. O tamanho do vetor, é ditado pelo número de símbolos originais. Se a mensagem é divida em 5 símbolos, então o vetor tem tamanho 5. Para codificar e criar um novo símbolo, o nó da rede começa por selecionar um novo vetor de coeficientes local. A função de codificação consiste numa combinação linear sobre um dado número de símbolos, utilizando o novo vetor local. O vetor do novo símbolo codificado é obtido da mesma forma. Sobre os vetores dos símbolos utilizados, é feita uma combinação linear utilizando o vetor local. Para descodificar os símbolos originais, são necessários um número igual de símbolos codificados, linearmente independentes. De forma a que os símbolos codificados e recodificados na rede, sejam linearmente independentes, podem ser utilizados algoritmos de tempo polinomial [59], para estabelecer os vetores locais utilizados por cada nó intermédio da rede. De forma a simplificar o problema, os vetores locais podem ser aleatórios (Random Linear Network Coding). Se o campo finito for suficientemente grande, a probabilidade de obter símbolos codificados linearmente independentes chega perto dos 100%. De forma a ter vetores mais reduzidos, tornando as operações mais simples, e permitindo uma descodificação gradual, os símbolos originais da mensagem podem ser organizados em gerações. Por cada geração, são gerados e injetados pela rede, símbolos codificados. Quando uma geração é descodificada, procede-se para a geração seguinte. Repare-se que a função de codificação referida anteriormente, com base em XOR, é o caso base e mais simples de um código linear. Neste caso, o campo finito é de tamanho 2. Apesar de ser um conceito relativamente simples, implementar e usar técnicas de codificação no plano de dados dos próprios dispositivos de rede é uma tarefa bastante complicada. Até mesmo quase impossível na maioria dos casos, visto que a payload dos pacotes é sujeita a alterações. O seu funcionamento baseia-se em protocolos fixos, que correm no próprio hardware de forma a maximizar o desempenho, o que torna difícil a tarefa de configurar e gerir uma rede para além das simples operações de encaminhamento de pacotes. Por este motivo, as implementações práticas de codificação na rede que têm vindo a surgir nos últimos anos, operam em redes overlay. Uma rede overlay reside logicamente na camada de aplicação, implicando que os dispositivos de rede propriamente ditos não são alterados. O interesse crescente em operações mais complexas e exigentes na rede, mas condicionado pelo funcionamento rígido e fechado dos routers e switches tradicionais, motivou uma mudança de paradigma: de redes configuráveis para redes programáveis. A primeira instância de uma rede programável é conhecida como Rede Definida por Software (SDN). Numa rede SDN, o plano de controlo é separado do plano de dados, e reside num dispositivo à parte - um controlador logicamente centralizado. Utilizando a informação de pacotes provenientes do plano de dados dos switches, o controlador pode definir políticas de configuração mais flexíveis e instalar regras nas tabelas match-action dos mesmos. A comunicação entre os switches e o controlador está estandardizada, sendo utilizado um protocolo conhecido como OpenFlow. A limitação de switches e controladores Open- Flow está no processamento de pacotes, que continua a ser fixo. De facto, o OpenFlow atua sobre um conjunto fixo de protocolos. Além disso, a sequência de tabelas e ações de um switch Openflow também é fixa. Portanto, o OpenFlow não permite realmente definir nova funcionalidade no plano de dados de um switch. Apenas fornece um meio para o controlador tomar decisões e instalar regras nas tabelas match-action, dos mesmos. No âmbito de codificação na rede, este fator impossibilita a alteração da payload dos pacotes, e consequentemente a sua combinação. No entanto, têm vindo a surgir recentemente switches programáveis, alguns até já em produção (por exemplo, Tofino da Barefoot Networks). Estes dispositivos permitem a programação e reprogramação do plano de dados, o que possibilita uma definição precisa e customizada do modo de processamento de pacotes. Com esta liberdade, a codificação na rede torna-se possível, no plano de dados. Porém, a sua programação é baseada em interfaces de baixo nível, tornando-se um processo demorado e doloroso. Esta dificuldade, acrescida também às limitações descritas do OpenFlow, motivou a criação da linguagem de alto nível, P4. A linguagem P4 permite definir cabeçalhos, parsers e a sequência de tabelas de matchaction, para qualquer dispositivo de rede compatível. As ações podem ser definidas utilizando um conjunto de primitivas básicas oferecidas pela linguagem. A linguagem P4 oferece três vantagens. Primeiro, não está dependente de protocolos e formatos de pacotes específicos, uma vez que a sua definição pode ser feita pelo programador. Segundo, permite a reconfiguração do switch a qualquer momento. Terceiro, não depende do hardware subjacente, podendo ser escrita, da mesma forma, para qualquer dispositivo que tenha o compilador adequado. O objetivo desta dissertação consiste no desenho, implementação e avaliação do primeiro switch capaz de realizar codificação no plano de dados, recorrendo à linguagem P4. Mais concretamente, a nossa solução consiste em dois switches: um que executa XOR (P4- XOR Switch), e outro que executa uma variante de Random Linear Network Coding (P4-RLNC Switch). Durante a implementação enfrentámos vários desafios, devido às peculiaridades da linguagem. Entre os principais fatores que dificultaram a implementação, está o facto de a linguagem ser declarativa, não permitindo a criação de estruturas de dados auxiliares em tempo de execução; e a impossibilidade de criar ciclos, essencial para repetir o mesmo processo de codificação sobre os vários elementos dos símbolos, no caso do P4-RLNC Switch. Sendo um trabalho inovador, a avaliação focou-se essencialmente na funcionalidade dos dois switches concretizados. Adicionalmente, a performance do P4-XOR Switch também foi avaliada.
Network Coding (NC) is a technique that can be used to improve a network’s throughput. In addition, it has significant potential to improve the security, manageability, resilience (to packet losses, link failures and node departures) and the support of quality of service, in both wired and wireless network environments. The idea is to allow intermediate nodes of the network (i.e. switches and/or routers) to mix the contents of incoming data packets before forwarding them. Something that, traditionally carried out at source nodes, is therefore extended to the network, creating an array of new options. The difficulty of deploying NC on traditional switches lies in the impossibility to change or extend their operation with the requirements of this new paradigm. The devices are closed, the software and underlying hardware are vendor specific, and follow a fixed set of protocols and processing pipeline. This rigidity precludes NC in today’s switches and routers. Fortunately, programmable switches are beginning to emerge, with some already achieving production-levels and reaching the market (e.g., Barefoot Tofino). A new high-level language to program these switches has recently been proposed: P4. The P4 language allows the precise definition of how packets are processed in these programmable switches. Namely, it enables the definition of headers, parsers, match-action tables, and the processing pipeline itself. Therefore, by taking advantage of these constructs, P4 enables the deployment of NC, on the switch’s data plane, for the first time. In this dissertation, we design and implement two NC switches using the P4 language. Both switches employ Linear Network Coding (LNC). The main difference is that the first (P4-XOR Switch), simply performs the XOR of packets (i.e., a linear code with field size 2). The second (P4-RLNC Switch) is more generic, allowing larger field sizes. For this purpose it performs Random Linear Network Coding (RLNC), which is a random variant of LNC. The evaluation was performed on Mininet (a network emulator) and focused on the functionality of both switches. Additionally, the performance of the P4-XOR Switch was tested as well. The main conclusion is that our implementations correctly perform the required operations allowing, for the first time, NC to be performed in real data planes.

碩士
朝陽科技大學
資訊與通訊系
105
In the world of Internet, in order to meet the needs of low transmission latency and easy route management, generally, we adopt the transmission methods of shortest path or single path. However, this the methods make it troublesome since it becomes harder to utilize bandwidth effectively. To solve this problem, some researchers have focused on the route optimization algorithms. The proposed algorithms when transmitting the data select one of routing paths. Nevertheless, the problem of utilization of bandwidth is still existed. Moreover, the routing security risk is high since the transmission of single path is easy to intercept and wiretap. Therefore, in this study, the method called Weight-Based Flow Dividing (WFD) on the OpenFlow switch under the framework of Software-Defined Networking (SDN) is proposed to utilize bandwidth effectively and reduce the routing security risk. The experiment results show the packets are transmitted on Multi-Path instead of single path by WFD. On the other hand, the bandwidth utilization of SDN is easier to adjust than that of traditional network in the implementations of software and hardware because of the programming of SDN.

This document discusses the concept of drivers implemented within the context of the REMPLI (Real-Time Energy Management over Power line and Internet, see section 1.8.) network. The process image approach and the tunnelling approach are presented and reasoning is given why the tunnelling approach is preferred. Each of the drivers implemented is associated with a specific metering protocol. This document further discusses the general architecture of such a driver structure. The generic software architecture serves as a framework for integrating serial communication based metering protocols over packet-orientated remote networks and meters, by tunnelling the protocol data units to the remote meters. Principally each Protocol Driver consists of three parts, one part situated at the Application Server, one at the Access Point and one at the Node. This document then gives a description of the general driver structure within the REMPLI network and briefly explains the functions of all the modules contained within the driver structure. An example is used to show how these modules, which make up the software architecture of the Protocol Driver, are used to send an application generated request from the Application Server to the Metering Equipment and sending the response back from the remote Metering Equipment to the Application Server. This dissertation further discusses the need for address translation within the REMPLI network and the need to restrict access to meters by using these addresses and an access control list. This document also discusses the need for a “Keep-alive” signalling scheme, if supported by the underlying protocol and gives a general concept as to how it should be implemented. The role of an Optimization Module is also discussed for low bandwidth networks by means of an M-Bus example. Finally the M-Bus protocol driver implementation is discussed. The results achieved are presented, showing that the driver architecture can successfully be used to tunnel the M-Bus protocol to remote meters, provided the underlying network conforms to the quality of service requirements determined by the implemented metering protocol. The work proposed in this document started off as part of the REMPLI project by the REMPLI team but was completed independently.
Dissertation (MEng (Computer Engineering))--University of Pretoria, 2008.
Electrical, Electronic and Computer Engineering
unrestricted