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Автор: Grafiati
Опубліковано: 14 березня 2023

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Статті в журналах з теми "Software-based fault injection"

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Laurent, J., C. Deleuze, F. Pebay-Peyroula, and V. Beroulle. "Bridging the Gap between RTL and Software Fault Injection." ACM Journal on Emerging Technologies in Computing Systems 17, no. 3 (May 11, 2021): 1–24. http://dx.doi.org/10.1145/3446214.

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Анотація:
Protecting programs against hardware fault injection requires accurate software fault models. However, typical models, such as the instruction skip, do not take into account the microarchitecture specificities of a processor. We propose in this article an approach to study the relation between faults at the Register Transfer Level (RTL) and faults at the software level. The goal is twofold: accurately model RTL faults at the software level and materialize software fault models to actual RTL injections. These goals lead to a better understanding of a system's security against hardware fault injection, which is important to design effective and cost-efficient countermeasures. Our approach is based on the comparison between results from RTL simulations and software injections (using a program mutation tool). Various analyses are included in this article to give insight on the relevance of software fault models, such as the computation of a coverage and fidelity metric, and to link software fault models to hardware RTL descriptions. These analyses are applied on various single-bit and multiple-bit injection campaigns to study the faulty behaviors of a RISC-V processor.
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Park, Jihyun, and Byoungju Choi. "ASFIT: AUTOSAR-Based Software Fault Injection Test for Vehicles." Electronics 9, no. 5 (May 20, 2020): 850. http://dx.doi.org/10.3390/electronics9050850.

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Анотація:
With recent increases in the amount of software installed in vehicles, the probability of automotive software faults that lead to accidents has also increased. Because automotive software faults can lead to serious accidents or even mortalities, vehicle software design and testing must consider safety a top priority. ISO 26262 recommends fault injection testing as a measure to verify the functional safety of vehicles. However, the standard does not clearly specify when and where faults should be injected, and the tools to support fault injection testing for automotive software are also insufficient. In the present study, we define faults that may occur in Automotive Open System Architecture (AUTOSAR)-based automotive software and propose a fault injection method to be applied during the software development process. The proposed method can inject different types of faults that may occur in AUTOSAR-based automotive software, such as access, asymmetric, and timing errors, while minimizing performance degradation due to fault injection, and without using any separate hardware devices. The superior performance of the proposed method is demonstrated through empirical studies applied to fault injection testing of a range of vehicle electronic control unit software.
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Arasteh, Bahman. "A Program-Aware Fault-Injection Method for Dependability Evaluation Against Soft-Error Using Genetic Algorithm." Journal of Circuits, Systems and Computers 27, no. 09 (April 26, 2018): 1850144. http://dx.doi.org/10.1142/s021812661850144x.

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Анотація:
Decreasing the scale of transistors and exponential increase in the transistor counts has made the soft-errors as one of the major causes of software failures. Fault injection is a powerful method for dependability assessment of a computer system against soft-errors. A considerable number of randomly injected faults in the current methods and tools are effect-less or equivalent. To overcome this problem and reduce the cost of fault injection, this study presents a software based fault-injection method that accurately evaluates the dependability of a computer system with a limited number fault-injection. Using a genetic algorithm (GA) the most vulnerable executable paths of an input program is identified; then only the basic blocs (BBs) into the identified vulnerable paths are considered as the target of fault injection. The results of fault injections on the set of 8 traditional benchmark-programs show that the proposed method reduces about 20% of effect-less faults by avoiding the injection of faults in the error-derating blocks of a program. Furthermore, the number of injected faults is reduced to 60% of its original size in the random injection. Also, the proposed method provides more stable and accurate results than the random injection.
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Shamim Hos, Mohammod. "Web Service Based Software Implemented Fault Injection." Information Technology Journal 5, no. 1 (December 15, 2005): 138–43. http://dx.doi.org/10.3923/itj.2006.138.143.

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Li, Yi, Ping Xu, and Han Wan. "A Fault Injection System Based on QEMU Simulator and Designed for BIT Software Testing." Applied Mechanics and Materials 347-350 (August 2013): 580–87. http://dx.doi.org/10.4028/www.scientific.net/amm.347-350.580.

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Анотація:
An important step in the development of dependable systems is the validation of their fault tolerance properties. Fault injection has been widely used for this purpose. This paper presents a simulator implemented fault injection and monitoring environment based on the QEMU platform, called BitVaSim, which is targeted for the embedded development boards equipped with PowerPC or ARM processor together with Built-In Test software operating environment.BitVaSim takes advantage of simulation and do no harm or irruption to either the real hardware or the software, in addition, all the simulated parts are reachable so that more fault modes are available to achieve.BitVaSim uses abstract key-value pairs to describe the functional fault modes, and then simulates the hardware board as while as realistic faults incurred by hardware into the simulator, in order to monitor the activation of the faults and their impact on the target system especially the BIT system behavior in detail. Fault injection interfaces are configured to implement failure mode matching and fault conditions triggering to inject faults on demand in simulator runtime.Faults injected by BitVaSim can affect any process running on the target system (including the kernel), and it is possible to inject faults in applications for which the source code is not available.Experimental results are presented to demonstrate the accuracy and potential of BitVaSim in the evaluation of the dependability properties of the complex computer systems and the BIT system.
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Shi, Biao Biao, and Xiao Peng Gao. "An Implementation of Simulation-Based Environment for Bus Fault Injection Techniques." Advanced Materials Research 756-759 (September 2013): 4672–76. http://dx.doi.org/10.4028/www.scientific.net/amr.756-759.4672.

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Анотація:
Reliability is the most important feature in this more and more complex computer system era. Fault injection is dependability validation technique to evaluating the system. Hardware and Software implementations of fault injection have a long history and are much more mature than simulated fault injection. In this paper, we compare the differences between these three types of fault injections at first. Then, we identify and understand the types of fault. We design a low-cost, simulation-based fault injection system and design experiments to verify the correctness.
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Aguilera, Carlos J. G., Cristiano P. Chenet, and Tiago R. Balen. "Fault Injection on a Mixed-Signal Programmable SoC with Design Diversity Mitigation." Journal of Integrated Circuits and Systems 11, no. 3 (December 28, 2016): 185–91. http://dx.doi.org/10.29292/jics.v11i3.443.

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Анотація:
This paper presents an approach for runtime software-based fault injection, applied to a commercial mixed-signal programmable system-on-chip (PSoC). The fault-injection scheme is based on a pseudo-random sequence generator and software interruption. A fault tolerant data acquisition system, based on a design diversity redundant scheme, is considered as case study. The fault injection is performed by intensively inserting bit flips in the peripherals control registers of the mixed-signal PSoC blocks, as well as in the SRAM memory of the device. Results allow to evaluate the applied fault tolerance technique, indicating that the system is able to tolerate most of the generated errors. Additionally, a high fault masking effect is observed, and different criticality levels are observed for faults injected into the SRAM memory and in the peripherals control registers.
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Gangolli, Aakash, Qusay H. Mahmoud, and Akramul Azim. "A Systematic Review of Fault Injection Attacks on IoT Systems." Electronics 11, no. 13 (June 28, 2022): 2023. http://dx.doi.org/10.3390/electronics11132023.

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Анотація:
The field of the Internet of Things (IoT) is growing at a breakneck pace and its applications are becoming increasingly sophisticated with time. Fault injection attacks on IoT systems are aimed at altering software behavior by introducing faults into the hardware devices of the system. Attackers introduce glitches into hardware components, such as the clock generator, microcontroller, and voltage source, which can affect software functioning, causing it to misbehave. The methods proposed in the literature to handle fault injection attacks on IoT systems vary from hardware-based attack detection using system-level properties to analyzing the IoT software for vulnerabilities against fault injection attacks. This paper provides a systematic review of the various techniques proposed in the literature to counter fault injection attacks at both the system level and the software level to identify their limitations and propose solutions to address them. Hybrid attack detection methods at the software level are proposed to enhance the security of IoT systems against fault injection attacks. Solutions to the identified limitations are suggested using machine learning, dynamic code instrumentation tools, hardware emulation platforms, and concepts from the software testing domain. Future research possibilities, such as the use of software fault injection tools and supervised machine learning for attack detection at the software level, are investigated.
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Geoghegan, Sean J., and D. R. Avresky. "Designing and Validation of Error Detection Software." International Journal of Reliability, Quality and Safety Engineering 05, no. 04 (December 1998): 337–57. http://dx.doi.org/10.1142/s0218539398000297.

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Анотація:
We propose a systematic approach for design and validation of error detection software. Formally, the semantic of a specification is represented by a transition system. This representation is then used to generate a flowgraph or ddgraph which is used to construct an execution path tree. The information obtained from this algorithm representation is used to aid in the design of software-based fault detection techniques for hardware faults. Flowgraph and ddgraph representations provide information to predict future program flow. During execution, the current program path is recorded, along with the expected path. Checks are placed to verify that the program path follows the predicted path. Algorithm-based fault tolerance (ABFT) techniques are used to detect data structure corrupting faults and to improve the fault coverage. Fault coverage provided by this approach for different types of hardware faults has been estimated through experiments with the software-based fault injection tool (SOFIT) and the data is presented to demonstrate the effectiveness of the method.
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Azimi, Sarah, Corrado De Sio, Daniele Rizzieri, and Luca Sterpone. "Analysis of Single Event Effects on Embedded Processor." Electronics 10, no. 24 (December 18, 2021): 3160. http://dx.doi.org/10.3390/electronics10243160.

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Анотація:
The continuous scaling of electronic components has led to the development of high-performance microprocessors which are even suitable for safety-critical applications where radiation-induced errors, such as single event effects (SEEs), are one of the most important reliability issues. This work focuses on the development of a fault injection environment capable of analyzing the impact of errors on the functionality of an ARM Cortex-A9 microprocessor embedded within a Zynq-7000 AP-SoC, considering different fault models affecting both the system memory and register resources of the embedded processor. We developed a novel Python-based fault injection platform for the emulation of radiation-induced faults within the AP-SoC hardware resources during the execution of software applications. The fault injection approach is not intrusive, and it does not require modifying the software application under evaluation. The experimental analyses have been performed on a subset of the MiBench benchmark software suite. Fault injection results demonstrate the capability of the developed method and the possibility of evaluating various sets of fault models.
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Більше джерел

Дисертації з теми "Software-based fault injection"

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Azambuja, José Rodrigo Furlanetto de. "Análise de técnicas de tolerância a falhas baseadas em software para a proteção de microprocessadores." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2010. http://hdl.handle.net/10183/49076.

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Анотація:
Da mesma maneira que novas tecnologias trouxeram avanços para a indústria de semicondutores, diminuíram a confiabilidade dos transistores e consequentemente dos sistemas digitais. Efeitos causados por partículas energizadas antes só vistos em ambientes espaciais hoje se manifestam a nível do mar, introduzindo novos desafios para a fabricação e projeto de sistemas que requerem confiabilidade. Sistemas de alta confiabilidade que utilizam circuitos integrados exigem a utilização de técnicas de tolerância a falhas capazes de detectar ou mesmo corrigir os erros causados por partículas energizadas. Esta proteção pode ser implementada em diferentes níveis: hardware ou software. Enquanto o primeiro exige a modificação interna de circuitos integrados desprotegidos e oferece alto desempenho, o segundo altera somente o código de programa, porém com perdas de desempenho que variam conforme o grau de proteção do sistema. O objetivo deste trabalho é analisar a eficiência na detecção de falhas em microprocessadores através de técnicas de tolerância a falhas baseadas somente em software. Para isto, são propostas diferentes técnicas de tolerância a falhas baseadas somente em software inspiradas em técnicas apresentadas no estado da arte. Estas são implementadas separadamente e combinadas, de maneira a encontrar suas vulnerabilidades e descobrir como estas podem ser combinadas, a fim de apresentar uma solução ideal para diferentes sistemas em termos de desempenho e confiabilidade. A análise se dá através de uma campanha de injeção de falhas direcionada para cada parte de um microprocessador e observando-se os efeitos causados por cada falha no resultado do sistema.
As new technologies brought advances to the semiconductor industry, they also lowered transistors' reliability and therefore decreased digital systems' reliability. Effects caused by energized particles which were only seen in spatial environments nowadays manifest at sea level, introducing new challenges in the design and fabrication of systems that require high reliability. High reliable systems based on integrated circuits require fault tolerant techniques in order to detect or even correct errors caused by energized particles. This protection can be implemented in different levels: hardware or software. While the first requires internal modifications in the integrated circuit and offers high performance, the second modifies only the program code, but causes system's performance degradation, which can vary according the system's protection level. This work's objective is to analyze software-based fault tolerant techniques efficiency to detect faults in microprocessors. In order to achieve it, different fault tolerance techniques based in software are proposed inspired in techniques presented in state-of-the-art techniques. They are implemented separately and then combined, to analyze their vulnerabilities and realize how to combine them, in order to present an ideal solution for each system, taking into account performance and reliability. The analysis is based in a fault injection campaign directed to each part of the microprocessor, considering the effects caused by each fault in the system's response.
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Schirmeier, Horst Benjamin [Verfasser], Olaf [Akademischer Betreuer] Spinczyk, and Andreas [Gutachter] Polze. "Efficient fault-injection-based assessment of software-implemented hardware fault tolerance / Horst Benjamin Schirmeier. Betreuer: Olaf Spinczyk. Gutachter: Andreas Polze." Dortmund : Universitätsbibliothek Dortmund, 2016. http://d-nb.info/1112561862/34.

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VELASCO, ALEJANDRO DAVID. "Software-based methods for Operating system dependability." Doctoral thesis, Politecnico di Torino, 2017. http://hdl.handle.net/11583/2678125.

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Анотація:
Guaranteeing correct system behaviour in modern computer systems has become essential, in particular for safety-critical computer-based systems. However all modern systems are susceptible to transient faults that can disrupt the intended operation and function of such systems. In order to evaluate the sensitivity of such systems, different methods have been developed, and among them Fault Injection is considered a valid approach widely adopted. This document presents a fault injection tool, called Kernel-based Fault-Injection Tool Open-source (KITO), to analyze the effects of faults in memory elements containing kernel data structures belonging to a Unix-based Operating System and, in particular, elements involved in resources synchronization. This tool was evaluated in different stages of its development with different experimental analyses by performing Faults Injections in the Operating System, while the system was subject to stress from benchmark programs that use different elements of the Linux kernel. The results showed that KITO was capable of generating faults in different elements of the operating systems with limited intrusiveness, and that the data structures belonging to synchronization aspects of the kernel are susceptible to an appreciable set of possible errors ranging from performance degradation to complete system failure, thus preventing benchmark applications to perform their task. Finally, aiming at overcoming the vulnerabilities discovered with KITO, a couple of solutions have been proposed consisting in the implementation of hardening techniques in the source code of the Linux kernel, such as Triple Modular Redundancy and Error Detection And Correction codes. An experimental fault injection analysis has been conducted to evaluate the effectiveness of the proposed solutions. Results have shown that it is possible to successfully detect and correct the noxious effects generated by single faults in the system with a limited performance overhead in kernel data structures of the Linux kernel.
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Rollins, Nathaniel Hatley. "Hardware and Software Fault-Tolerance of Softcore Processors Implemented in SRAM-Based FPGAs." BYU ScholarsArchive, 2012. https://scholarsarchive.byu.edu/etd/2998.

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Анотація:
Softcore processors are an attractive alternative to using expensive radiation-hardened processors for space-based applications. Since they can be implemented in the latest SRAM-based FPGA technologies, they are fast, flexible and significantly less expensive. However, unlike ASIC-based processors, the logic and routing of a softcore processor are vulnerable to the effects of single-event upsets (SEUs). To protect softcore processors from SEUs, this dissertation explores the processor design-space for the LEON3 softcore processor implemented in a commercial SRAM-based FPGA. The traditional mitigation techniques of triple modular redundancy (TMR) and duplication with compare (DWC) and checkpointing provide reliability to a softcore processor at great spatial cost. To reduce the spatial cost, terrestrial ASIC-based processor protection techniques are applied to the LEON3 processor. These techniques come at the cost of time instead of area. The software fault-tolerance techniques used to protect the logic and routing of the LEON3 softcore processor include a modified version of software implemented fault tolerance (SWIFT), consistency checks, software indications, and checkpointing. To measure the reliability of a mitigated LEON3 softcore processor, an updated hardware fault-injection model is created, and novel reliability metrics are employed. The improvement in reliabilty over an unmitigated LEON3 is measured using four metrics: architectural vulnerability factor (AVF), mean time to failure (MTTF), mean useful instructions to failure (MuITF), and reliability-area-performance (RAP). Traditional reliability techniques provide the best reliability: DWC with checkpointing improves the MTTF and MuITF by almost 35x and TMR with triplicated input and outputs improves the MTTF and MuITF by almost 6000x. Software fault-tolerance provides significant reliability for a much lower area cost. Each of these techniques provides greater processor protection than a popular state-of-the-art rad-hard processor.
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Fadel, Aline Cristine 1984. "Técnicas de testes aplicadas a software embarcado em redes ópticas." [s.n.], 2011. http://repositorio.unicamp.br/jspui/handle/REPOSIP/267792.

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Анотація:
Orientadores: Regina Lúcia de Oliveira Moraes, Eliane Martins
Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Tecnologia
Made available in DSpace on 2018-08-19T14:09:37Z (GMT). No. of bitstreams: 1 Fadel_AlineCristine_M.pdf: 3259764 bytes, checksum: a287ca33254d027f23e2f2f818464ee1 (MD5) Previous issue date: 2011
Resumo: Esse trabalho apresenta os detalhes e os resultados de testes automatizados e manuais que utilizaram a técnica de injeção de falhas e que foram aplicados em redes ópticas. No primeiro experimento o teste foi automatizado e utilizou a emulação de falhas físicas baseadas na máquina de estados do software embarcado dessa rede. Para esse teste foi utilizado uma chave óptica que é controlada por um robô de testes. O segundo experimento foi um teste manual, que injetou falhas nas mensagens de comunicação do protocolo dessa rede, a fim de validar os mecanismos de tolerância a falhas do software central dessa rede. Esse experimento utilizou a metodologia Conformance and Fault injection para preparar, executar e relatar os resultados dos casos de testes. Nos dois experimentos também foi utilizado um padrão de documentação de testes que visa facilitar a reprodução dos testes, a fim de que eles possam ser aplicados em outros ambientes. Com a aplicação desses testes, a rede óptica pode alcançar uma maior confiabilidade, disponibilidade e robustez, que são características essenciais para sistemas que requerem alta dependabilidade
Abstract: This work presents the details and the results of automatic and manual tests that used the fault injection technique and were applied on GPON network. In the first experiment the test was automated, and it performed the emulation of physical faults based on the state machine of the embedded software in this network. In this test is used an optical switch that is controlled by a test robot. The second experiment was a manual test, which injected faults on protocol communication message exchanged through the optical network, in order to validate the main software fault tolerance mechanisms. This experiment used a Conformance and Fault injection methodology to prepare, execute and report the results of the test cases. In both experiments, it was used a standard test documentation to facilitate the reproduction of the tests, so that they can be applied in other environments. With applying both tests, the optical networks reach greater reliability, availability and robustness. These attributes are essential for systems that require high dependability
Mestrado
Tecnologia e Inovação
Mestre em Tecnologia
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6

Geissler, Filipe de Aguiar. "Metodologia de injeção de falhas baseada em emulação de processadores." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2014. http://hdl.handle.net/10183/107543.

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Анотація:
Esta dissertação tem por finalidade apresentar uma metodologia de injeção de falhas baseada em emulação de processadores. Os efeitos causados pela radiação em processadores, operando no espaço ou em altitudes elevadas, têm sido estudados na literatura para o desenvolvimento de mecanismos de tolerância a falhas. Com a crescente popularidade do uso de processadores comerciais, (COTS – do inglês, Commercial Off-The-Shelf), em aplicações críticas, uma série de preocupações tem surgido devido a falta de confiabilidade apresentada por estes sistemas. Sendo desprovidos de mecanismos de tolerância para melhor robustez em ambientes espaciais, estes dispositivos comerciais são mais suscetíveis aos efeitos da radiação. Neste contexto, técnicas de tolerância a falhas baseadas em software vêm sendo estudadas a fim de aumentar a confiabilidade desta abordagem. Para a devida validação de tais mecanismos de tolerância, o uso de técnicas de injeção de falhas é aplicável. Estas técnicas de injeção de falhas possuem uma série de limitações que podem inviabilizar a sua aplicabilidade, dependendo da abordagem utilizada. Fatores como custo, indisponibilidade da descrição de hardware – utilizada em técnicas de injeção de falhas por simulação ou emulação em FPGA (Field Programmable Gate Array), e o longo tempo necessário para execução dos experimentos, são alguns exemplos de limitações das técnicas disponíveis. Com base nisso, a metodologia de injeção de falhas alternativa apresentada neste trabalho, visa reduzir as limitações presentes nas mais diversas técnicas. Baseada na utilização de tradução dinâmica de instruções, para acelerar o processo de execução de aplicações em emuladores, a metodologia apresenta um modelo de falhas para efeitos transientes e permanentes, aplicáveis neste cenário. Como método de classificação dos efeitos observados neste processo, um modelo presente na literatura foi utilizado. Para validação desta metodologia, um injetor de falhas baseado no emulador QEMU foi desenvolvido. Posteriormente, um estudo de caso com o injetor de falhas foi realizado para três estruturas de software distintas executando individualmente no processador MIPS 24kc, representando três níveis de complexidade distintos: sistema operacional Linux, sistema de tempo real, (RTEMS – do inglês, Real-Time Operating System), e uma aplicação dedicada. Cada sistema foi submetido a uma campanha de injeção de falhas transientes para emulação de efeitos singulares (SEU – do inglês, Single Event Upset). Como alvo de falhas, foram selecionados os registradores do processador e a memória de dados. Por fim, as análises obtidas através dos experimentos mostraram os diferentes efeitos observados para os três níveis de complexidade dos softwares executados. Além disso, se pôde avaliar o desempenho do injetor de falhas, disponibilizando ao final do trabalho uma ferramenta para o auxílio no desenvolvimento de técnicas de tolerância a falhas por software.
This dissertation aims to present a fault injection methodology based on microprocessor emulation. The effects caused by radiation in microprocessors, operating in space or at high altitudes, have been studied in the literature for the development of fault tolerance mechanisms. With the growing popularity of COTS (Commercial Off-The-Shelf) processors usage, in critical applications, a number of concerns have arisen due to the lack of reliability, presented in these systems. Due to the lack of fault tolerance mechanisms, these COTS devices are more susceptible to radiation effects. In this context, software-based fault tolerance techniques have been studied in the literature in order to increase the reliability of this approach. To validate such fault tolerance mechanisms, the use of fault injection techniques is applicable. These fault injection techniques have several limitations which can preclude their applicability, depending on of its design approach. Factor such as cost, unavailability of hardware description – used by fault injection techniques based on simulation or emulation with FPGA (Field Programmable Gate Array), and the long time demanded to execute experiments, are some examples of limitations in the available techniques. Based on this, the alternative fault injection methodology presented in this work aims to reduce these limitations. Based on the dynamic translation of instructions usage to accelerate the execution of application on emulators, the methodology presents a fault model for transient and permanent faults applicable in this scenario. As a classification method of the observed effects in this process, a model in the literature has been used. To validate this methodology, a fault injector based on the QEMU emulator was implemented. Later, a case study with the fault injector was performed for three software structures running at a time on a MIPS 24kc processor, representing three different levels of complexity: Linux operating system, RTEMS (Real-Time Operating System), and a dedicated application. Each system was submitted to a fault injection campaign emulating Single Event Upsets (SEUs). As fault targets it was selected the processor registers and the data memory. Finally, the analysis obtained with the experiments showed the different effects observed for the three levels of complexity. Besides that, the fault injector performance could be evaluated providing in the end a tool to help in the development of software-based fault injection techniques.
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Khosrowjerdi, Hojat. "Learning-based Testing for Automotive Embedded Systems : A requirements modeling and Fault injection study." Licentiate thesis, KTH, Teoretisk datalogi, TCS, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-247506.

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Анотація:
This thesis concerns applications of learning-based testing (LBT) in the automotive domain. In this domain, LBT is an attractive testing solution, since it offers a highly automated technology to conduct safety critical requirements testing based on machine learning. Furthermore, as a black-box testing technique, LBT can manage the complexity of modern automotive software applications such as advanced driver assistance systems. Within the automotive domain, three relevant software testing questions for LBT are studied namely: effectiveness of requirements modeling, learning efficiency and error discovery capabilities. Besides traditional requirements testing, this thesis also considers fault injection testing starting from the perspective of automotive safety standards, such as ISO26262. For fault injection testing, a new methodology is developed based on the integration of LBT technologies with virtualized hardware emulation to implement both test case generation and fault injection. This represents a novel application of machine learning to fault injection testing. Our approach is flexible, non-intrusive and highly automated. It can therefore provide a complement to traditional fault injection methodologies such as hardware-based fault injection.

QC 20190325

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Частини книг з теми "Software-based fault injection"

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Ambrosio, Ana Maria, Fátima Mattiello-Francisco, Valdivino A. Santiago, Wendell P. Silva, and Eliane Martins. "Designing Fault Injection Experiments Using State-Based Model to Test a Space Software." In Lecture Notes in Computer Science, 170–78. Berlin, Heidelberg: Springer Berlin Heidelberg, 2007. http://dx.doi.org/10.1007/978-3-540-75294-3_13.

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Cotroneo, Domenico, and Henrique Madeira. "Introduction to Software Fault Injection." In Innovative Technologies for Dependable OTS-Based Critical Systems, 1–15. Milano: Springer Milan, 2013. http://dx.doi.org/10.1007/978-88-470-2772-5_1.

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Meinke, Karl, and Peter Nycander. "Learning-Based Testing of Distributed Microservice Architectures: Correctness and Fault Injection." In Software Engineering and Formal Methods, 3–10. Berlin, Heidelberg: Springer Berlin Heidelberg, 2015. http://dx.doi.org/10.1007/978-3-662-49224-6_1.

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Kühn, Johannes Maximilian, Oliver Bringmann, and Wolfgang Rosenstiel. "Increasing Reliability Using Adaptive Cross-Layer Techniques in DRPs: Just-Safe-Enough Responses to Reliability Threats." In Dependable Embedded Systems, 121–38. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-52017-5_5.

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AbstractThe developments in the semiconductor industry as predicted by institutions such as the ITRS present a difficult question to hardware and software developers alike: How to implement increasingly complex, power hungry, and critical applications reliably in today’s and tomorrow’s semiconductor technology? The present trend of semiconductor technology is characterized by a sharp increase in complexity, cost, and delicacy. Also, it does not scale along the demands which are still based on and often exceed Moore’s Law. In this chapter, we propose to exploit the architectural redundancies provided by potent, yet energy efficient massively parallel architectures, modeled using Dynamically Reconfigurable Processors (DRP). Using DRPs, we built an extensive cross-layer approach, offering different levels of reliability measures to operating system (OS) and software developers through low-cost hardware redundancy schemes and appropriate physical operating condition tuning. On the hardware side, online testing schemes and error detection are deployed to trigger dynamic remapping to avoid the usage of faulty components. This approach is further complemented through hardware health monitoring that can detect reliability issues such as negative bias temperature instability (NBTI) or hot carrier injection (HCI) before they surface as an error as well as further tuning of operating conditions to delay such phenomena from surfacing.
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Salterain, A., A. Galarza, S. Urcelayeta, J. Mendizabal-Samper, and J. Blanco. "UML-based Fault Injection for Software Model Testing (FISMT)." In Reliability, Risk, and Safety. CRC Press, 2009. http://dx.doi.org/10.1201/9780203859759.ch278.

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Carrozza, Gabriella, and Roberto Natella. "A Recovery-Oriented Approach for Software Fault Diagnosis in Complex Critical Systems." In Machine Learning, 388–413. IGI Global, 2012. http://dx.doi.org/10.4018/978-1-60960-818-7.ch303.

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This paper proposes an approach to software faults diagnosis in complex fault tolerant systems, encompassing the phases of error detection, fault location, and system recovery. Errors are detected in the first phase, exploiting the operating system support. Faults are identified during the location phase, through a machine learning based approach. Then, the best recovery action is triggered once the fault is located. Feedback actions are also used during the location phase to improve detection quality over time. A real world application from the Air Traffic Control field has been used as case study for evaluating the proposed approach. Experimental results, achieved by means of fault injection, show that the diagnosis engine is able to diagnose faults with high accuracy and at a low overhead.
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Vimaladevi M. and Zayaraz G. "A Game Theoretic Approach for Quality Assurance in Software Systems Using Antifragility-Based Learning Hooks." In Research Anthology on Agile Software, Software Development, and Testing, 1701–19. IGI Global, 2022. http://dx.doi.org/10.4018/978-1-6684-3702-5.ch081.

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The use of software in mission critical applications poses greater quality needs. Quality assurance activities are aimed at ensuring such quality requirements of the software system. Antifragility is a property of software that increases its quality as a result of errors, faults, and attacks. Such antifragile software systems proactively accepts the errors and learns from these errors and relies on test-driven development methodology. In this article, an innovative approach is proposed which uses a fault injection methodology to perform the task of quality assurance. Such a fault injection mechanism makes the software antifragile and it gets better with the increase in the intensity of such errors up to a point. A software quality game is designed as a two-player game model with stressor and backer entities. The stressor is an error model which injects errors into the software system. The software system acts as a backer, and tries to recover from the errors. The backer uses a cheating mechanism by implementing software Learning Hooks (SLH) which learn from the injected errors. This makes the software antifragile and leads to improvement of the code. Moreover, the SLH uses a Q-Learning reinforcement algorithm with a hybrid reward function to learn from the incoming defects. The game is played for a maximum of K errors. This approach is introduced to incorporate the anti-fragility aspects into the software system within the existing framework of object-oriented development. The game is run at the end of every increment during the construction of object-oriented systems. A detailed report of the injected errors and the actions taken is output at the end of each increment so that necessary actions are incorporated into the actual software during the next iteration. This ensures at the end of all the iterations, the software is immune to majority of the so-called Black Swans. The experiment is conducted with an open source Java sample and the results are studied selected two categories of evaluation parameters. The defect related performance parameters considered are the defect density, defect distribution over different iterations, and number of hooks inserted. These parameters show much reduction in adopting the proposed approach. The quality parameters such as abstraction, inheritance, and coupling are studied for various iterations and this approach ensures considerable increases in these parameters.
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Hanawa, Toshihiro, and Mitsuhisa Sato. "D-Cloud." In Cloud Technology, 2307–22. IGI Global, 2015. http://dx.doi.org/10.4018/978-1-4666-6539-2.ch110.

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Various information systems are widely used in the information society era, and the demand for highly dependable system is increasing year after year. However, software testing for such a system becomes more difficult due to the enlargement and the complexity of the system. In particular, it is often difficult to test parallel and distributed systems in the real world after deployment, although reliable systems, such as high-availability servers, are parallel and distributed systems. To solve these problems, the authors propose a software testing environment for dependable parallel and distributed system using the cloud computing technology, named D-Cloud. D-Cloud consists of the cloud management software as the role of the resource management, and a lot of virtual machine monitors with fault injection facility in order to simulate hardware faults. In addition, D-Cloud introduces the scenario manager, and it makes a number of different tests perform automatically. Currently, D-Cloud is realized by the use of Eucalyptus as the cloud management software. Furthermore, the authors introduce FaultVM based on QEMU as the virtualization software, and D-Cloud frontend that interprets test scenario, constructs test environment, and dispatches commands. D-Cloud enables automating the system configuration and the test procedure as well as performing a number of test cases simultaneously and emulating hardware faults flexibly. This chapter presents the concept and design of D-Cloud, and describes how to specify the system configuration and the test scenario. Furthermore, the preliminary test example as the software testing using D-Cloud is presented. As the result, the authors show that D-Cloud allows easy setup of the environment, and to test the software testing for the distributed system.
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Тези доповідей конференцій з теми "Software-based fault injection"

1

Jin, Ang, Jianhui Jiang, Jiawei Hu, and Jungang Lou. "A PIN-Based Dynamic Software Fault Injection System." In 2008 9th International Conference for Young Computer Scientists (ICYCS). IEEE, 2008. http://dx.doi.org/10.1109/icycs.2008.329.

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Dandan Liu, Zhanyong Ren, Mengmeng Liu, and Zhaoyang Zeng. "Methodology of fault injection based on EDA software." In 2010 Prognostics and System Health Management Conference (PHM). IEEE, 2010. http://dx.doi.org/10.1109/phm.2010.5413479.

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Ahmad, Hussien Al-haj, Yasser Sedaghat, and Mahin Moradiyan. "LDSFI: a Lightweight Dynamic Software-based Fault Injection." In 2019 9th International Conference on Computer and Knowledge Engineering (ICCKE). IEEE, 2019. http://dx.doi.org/10.1109/iccke48569.2019.8964875.

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Gravellier, Joseph, Jean-Max Dutertre, Yannick Teglia, and Philippe Loubet Moundi. "FaultLine: Software-Based Fault Injection on Memory Transfers." In 2021 IEEE International Symposium on Hardware Oriented Security and Trust (HOST). IEEE, 2021. http://dx.doi.org/10.1109/host49136.2021.9702295.

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Murdock, Kit, David Oswald, Flavio D. Garcia, Jo Van Bulck, Daniel Gruss, and Frank Piessens. "Plundervolt: Software-based Fault Injection Attacks against Intel SGX." In 2020 IEEE Symposium on Security and Privacy (SP). IEEE, 2020. http://dx.doi.org/10.1109/sp40000.2020.00057.

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Wang, G. H., W. J. Qin, and W. S. Zhang. "A testability-demonstration software platform based on fault injection." In The 2015 International Conference on Electronics, Electrical Engineering and Information Science (EEEIS2015). WORLD SCIENTIFIC, 2016. http://dx.doi.org/10.1142/9789814740135_0070.

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Yu, Li, Liu Jia, Li GuoDong, and Li Xin. "Airborne Software Testing Technology Analysis Based on Fault Injection." In 2020 IEEE International Conference on Information Technology,Big Data and Artificial Intelligence (ICIBA). IEEE, 2020. http://dx.doi.org/10.1109/iciba50161.2020.9277468.

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Gordeyev, Alexander, Vyacheslav Khar henko, Anton Andrashov, Boris Konorev, Vladimir Sklyar, and Artem Boyarchuk. "Case-based software reliability assessmentby fault injection unified procedures." In the 2008 international workshop. New York, New York, USA: ACM Press, 2008. http://dx.doi.org/10.1145/1370868.1370870.

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Zeng, Fanping, Juan Li, Ling Li, and Xufa Wang. "Fault Injection Technology for Software Vulnerability Testing Based on Xen." In 2009 WRI World Congress on Software Engineering. IEEE, 2009. http://dx.doi.org/10.1109/wcse.2009.172.

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Jia Zhang. "Fault Injection-based Test Case Generation for SOA-oriented Software." In 2006 IEEE International Conference on Service Operations and Logistics, and Informatics. IEEE, 2006. http://dx.doi.org/10.1109/soli.2006.236579.

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