Дисертації з теми "Silicon Thin Film Technology"

In the last decades, there has been a huge proliferation of portable devices. Among them, consumer electronics such as mobile phones, music players, e-books, etc. are greatly extended. In order to provide these devices with the required autonomy, a power supply system has to be integrated within the device packaging. This impels the search of integrated power sources that could satisfy the requirements of high power density, long operation lifetime and low cost. Up to now, batteries have been commonly used as power supply for these devices. However, as functionalities increase, the need high off-grid power supply and storage exponentially increases. Just entering on the 4th generation (4G) era on consumer electronics devices, some studies suggest that the already optimized batteries are probably reaching their energy density limit and no longer can be considered for reliably powering high-performance devices. Therefore, in the last years, many research groups around the world have focused their attention on the development of efficient alternatives to batteries, as power supply for the new high-performance portable devices working on the low power regime (1−20W). Due to their long lifetime, high power density and integrability, probably the most promising alternative is the development of micro fuel cells. Among them, micro solid oxide fuel cells (micro SOFC) present the highest values of specific energy densities (by unit mass and/or volume), mainly due to their higher operating temperature and subsequent capability of operate directly on hydrocarbon fuels. The most extended design for micro SOFC devices is based on the fabrication of accessible freeKstanding membranes of the functional layers, i.e. a thin electrolyte covered by an anode and a cathode one at each side (electrodes), supported on silicon-based microfabricated platforms. The use of silicon as supporting material has been found to be very convenient as it is the principal material used in microfabrication technology and therefore there exist a wide and well-known series of techniques already developed for its micromachining. This allows the fabrication of functional membranes, while ensuring robustness on the system. This thesis encompasses the design, fabrication and characterization of thin film-based micro solid oxide fuel cells integrated in silicon. The development of micro SOFC was carried out in three different ways; (i.) presenting new designing strategies for the optimization of the free-standing membranes, (ii.) fabricating thermo-mechanically stable thin film electrolytes and (iii.) suggesting and implementing new more reliable thin film electrode materials. On one side, two different membrane designs are micro fabricated using silicon micro machining technology. First, the fabrication of a basic square design was firstly addressed, where the main concerns were placed on the adaptation of the fabrication flow to the Clean Room capabilities at IMB-CNM (CSIC). Then, an innovative large-area membrane was designed and fabricated. This second design was based on the use of doped silicon slab grids as robust support for the larger freeKstanding areas, allowing the fabrication of x30 larger membranes than previous basic designs. Yttria-stabilized zirconia (YSZ), the state-of-the-art electrolyte material in bulk SOFC, was used for the fabrication of thin film free-standing electrolytic membranes. Dense, fully crystalline and homogeneous films were obtained, as required for the fabrication of effective electrolytes, thus avoiding shortcuts between electrodes and/or gas leakages. An exhaustive study on the thermoKmechanical stability of the electrolytic membranes was performed, paying special attention to the evolution of the stress with fabrication conditions. Finally, target values of resistance associated to the electrolyte (Area Specific Resistance, ASR= 0.15 Ωcm(2)) were obtained at temperatures as low as 400℃ for 250 nm-thick YSZ membranes, thus presenting them as suitable electrolyte for micro SOFC operating in the intermediate range of temperatures (IT range, 400 − 800℃). Several materials were tested as thin film electrodes for their use in micro SOFC. First, although widely used by other authors in previous reports of micro SOFC systems, thin film metallic electrodes (porous Pt) were found to be thermally instable under micro SOFC operating temperatures. This impelled the search for alternative materials as either cathode or anode. For the cathode side, porous La(0.6)Sr(0.4)CoO(3-δ) (LSC) thin films were fabricated and implemented in real micro SOFC configurations, i.e. free-standing membranes. Sufficient conductivity for their use as cathode films was measured, and no degradation was observed in the whole operating range. The thermo-mechanical stability of LSC/YSZ/LSC membranes was ensured up to 700℃. Target values of ASR required for SOFC cathode/electrolyte bi-layers (0.30Ω cm(2)) were achieved in the IT range (700℃). For the anode side, porous Pt-Ce(0.8)Gd(0.2)O(1.9-δ) (Pt-CGO) thin film cermets were fabricated. Porous CGO films below 1m thick had to be fabricated due to delamination problems. Percolation of Pt into the porous ceramic network was ensured by thermal treatment and observed by SEM. Anode electrochemical performance was tested on Pt-CGO/YSZ/CGO-Pt symmetrical membranes. Target values for the anode/electrolyte biKlayer were reached again at temperatures of ca. 700℃. In addition, the fabrication of thermally stable metal-based current collectors was also addressed. A non-conventional lithographic step, i.e. nanosphere lithography was used in order to define a patterned grid on both sides of the functional membranes. Dense Pt grids were fabricated thermo-mechanically stable, and their durability was ensured during real micro SOFC operating conditions. Finally, a fully ceramic-based micro SOFC was presented here for the first time. The three functional components of the fuel cell, i.e. cathode, electrolyte and anode, were fabricated by using the previously developed thin films. Thus, LSC/YSZ/CGO-Pt free-standing membranes were fabricated, and finally Pt current collectors were implemented on both sides. Thermo-mechanical stability of the micro SOFC membrane was proved till 750℃, extending the up-to-now reported operating temperatures of micro SOFC and therefore allowing the use of ceramic electrodes. A maximum power density of 100 mW/cm(2) was measured at 750℃ under pure H2 as fuel and synthetic air as oxidant. These results represented the first report on a second generation of more reliable micro SOFC systems, based on ceramics instead of thermally instable metal-based electrodes.
En las últimas décadas, ha habido una gran proliferación de aparatos portátiles. Entre ellos, cabe destacar los aparatos destinados a electrónica de consumo, como por ejemplo teléfonos móviles, reproductores de música, libros electrónicos, etc., los cuales están actualmente muy extendidos. De cara a proporcionar a estos aparatos con suficiente autonomía, se ha de integrar una fuente de alimentación en el mismo dispositivo. Esto urge a buscar posibles fuentes de alimentación con capacidad de integración, y que a su vez satisfagan los requerimientos básicos de alta densidad de potencia, gran tiempo de vida y bajo coste. Hasta ahora, la principal fuente de alimentación utilizada en este tipo de dispositivos ha sido las baterías. Sin embargo, conforme aumentan las funcionalidades, la necesidad de mayor capacidad de suministro (o almacenamiento) energético aumenta. Es más, justo ahora entrando en la cuarta generación (4G) de la electrónica de consumo, diversos estudios sugieren que las baterías, ya optimizadas, probablemente están alcanzando su límite en densidad energética, con lo que no podrían ya considerarse más para alimentar de manera viable los dispositivos más avanzados. En este sentido, en los últimos años muchos grupos de investigación han puesto su atención en el desarrollo de alternativas viables que puedan mejorar las prestaciones de las baterías como fuente de alimentación de dispositivos de altas prestaciones que trabajen en el régimen de baja potencia (1 − 20W). Debido a su alto tiempo de vida, alta densidad energética y capacidad de integración, probablemente la alternativa más prometedora es el desarrollo de micro pilas de combustible. En particular, entre los diferentes tipos, las micro pilas de combustible de óxido sólido (micro SOFC, de sus siglas en inglés), presentan los mayores valores de densidad energética específica (por unidad de masa y/o volumen), mayormente debido a su alta temperatura de operación y la consecuente capacidad de operar directamente con combustibles hidrocarburos. El diseño de micro SOFC más extendido está basado en la fabricación de membranas auto soportadas, las cuales integran ya todas las partes funcionales de la pila, es decir, un electrolito fino cubierto por un ánodo y un cátodo (uno a cada lado). Estas membranas, de grosor muy fino (menos de 1m), normalmente se encuentran soportadas en plataformas de silicio micro mecanizadas, de manera que se facilita un fácil acceso al combustible directamente a ambos lados de la membrana, a la vez que se proporciona robustez al sistema. El uso de silicio como material de soporte es muy conveniente, ya que es el material más utilizado en micro fabricación, por lo que existe una amplia y altamente desarrollada serie de técnicas para su micro mecanizado. Esta tesis engloba el diseño, la fabricación y la caracterización de micro pilas de combustible de óxido sólido basadas en capas delgadas, e integradas en tecnología de silicio. El desarrollo de las micro SOFC se ha llevado a cabo de tres formas diferentes: (i.) presentando nuevos diseños para la optimización de las membranas auto soportadas, (ii.) fabricando electrolitos en capa delgada estables termo-mecánicamente y (iii.) sugiriendo e implementando en el dispositivo final nuevos materiales de electrodo en capa delgada más efectivos y viables que los actuales. En primer lugar, se fabricaron dos diseños de membrana diferentes, usando tecnología de micro fabricación de silicio. En el primero de los diseños, se fabricaron membranas cuadradas básicas. En este caso, el trabajo más importante fue el de la adaptación del proceso de fabricación al flujo de fabricación de la Sala Blanca del IMB-CNM (CSIC). Más adelante, se desarrolló un nuevo diseño de membrana de gran superficie, basado en el uso de mallas de nervios de silicio dopado como soporte robusto. Así, se consiguieron fabricar membranas auto soportadas con un área total de hasta 30 veces mayor que las conseguidas en el diseño básico anterior. Para el electrolito, se usó zirconia estabilizada con ytria (YSZ, de sus siglas en inglés), el material estado del arte en SOFC de gran volumen. Se fabricaron membranas auto soportadas de YSZ con gran reproducibilidad, obteniendo capas delgadas densas, cristalinas y de grosor homogéneo. Estas características son básicas para un buen funcionamiento del electrolito, ya que así se evitan posibles cortocircuitos entre los dos electrodos y/o fugas de gas. Además, se realizó un estudio exhaustivo de la estabilidad termo-mecánica de las membranas de YSZ, ya que las temperaturas de operación de la pila son de varios centenares de ℃. En particular, se prestó atención especial a la evolución de los estreses en función de las condiciones de fabricación de la capa de YSZ, para as. evitar posibles fallos en los continuos ciclados térmicos. Finalmente, se realizó un estudio de las propiedades electroquímicas de las membranas de YSZ fabricadas. Normalmente, se establece un valor de resistencia específica por área de 0.15 Ω cm2 para cada una de las capas funcionales de las pilas. En este caso, este valor objetivo se obtuvo a temperaturas de 400℃ en membranas de YSZ de 250 nm de grosor. De esta forma, se comprobó que estas capas pueden funcionar perfectamente como electrolito en todo el rango de operación de las micro SOFC, que normalmente se establece en 400 − 800℃. A continuación, se probaron diversos materiales como electrodos en capa delgada, para su implementación en micro SOFC. En primer lugar, aunque éstos han sido usados frecuentemente por otros autores en estudios previos de micro SOFC, se comprobó que los electrodos metálicos en capa delgada (capas de Pt poroso) son inestables a las temperaturas de operación de las micro SOFC. Por lo tanto, esto hizo que se probaran materiales alternativos, bien para el ánodo o para el cátodo. En particular, para el cátodo se fabricaron capas delgadas porosas de La(0.6)Sr(0.4)CoO(3-δ) (LSC) y se integraron en membranas auto soportadas de YSZ (electrolito). La conductividad eléctrica que se midió en estas capas es adecuada, y no se observó degradación en todo el rango de temperaturas de operación. Así mismo, se comprobó la estabilidad termo mecánica del sistema fabricando membranas simétricas de LSC/YSZ/LSC y realizándoles ciclados térmicos hasta los 700℃. Por último, se midieron las propiedades electroquímicas de las bi-capas cátodo/electrolito, obteniendo los valores objetivo de resistencia específica por área (0.30 Ωcm2) a temperaturas de 700℃. Para el ánodo, se fabricaron capas delgadas porosas de un cermet de Pt y Ce0(.8)Gd(0.2)O(1.9-δ) (PtKCGO). Las capas de CGO se tuvieron que fabricar de grosores por debajo de 1 m, debido a problemas de delaminación del sustrato. Se aseguró una buena inter-conexión entre el Pt y el CGO mediante tratamientos térmicos. Las propiedades electroquímicas se midieron nuevamente fabricando membranas simétricas, esta vez Pt-CGO/YSZ/CGO-Pt. Así mismo, el objetivo de 0.30 Ωcm2 se obtuvo de nuevo a temperaturas alrededor de 700℃. Además, en esta tesis se llevó a cabo la fabricación de colectores de corriente térmicamente estables y a su vez compatibles con la configuración básica de una micro SOFC (membranas auto soportadas). Para ello, se usó un proceso de litografía no convencional, llamado "nanosphere lithography". De esta forma se fabricaron mallas de Pt denso perfectamente ordenadas en ambos lados de las membranas. La estabilidad térmica y la durabilidad en el tiempo de estas mallas fue igualmente probada mediante medidas en condiciones de trabajo reales de micro SOFC. Por último, en este trabajo se presentó una micro SOFC completamente basada en cerámicas por primera vez. Las tres capas funcionales de la pila, es decir, tanto el cátodo, como el electrolito y el ánodo, se fabricaron basándose en los estudios previos de cada material. Así, se fabricaron membranas auto soportadas siguiendo la configuración LSC/YSZ/CGO-Pt. Además, se implementaron mallas de Pt en ambos lados para asegurar una buena colección de corriente. La estabilidad termo mecánica de la membrana se midió hasta 750℃, extendiendo así el rango de temperaturas de operación reportado anteriormente en dispositivos finales de micro SOFC y en consecuencia permitiendo el uso de electrodos cerámicos. Se midieron valores de densidad de potencia de 100 mW/cm2 a 750℃, usando H2 como combustible y aire sintético como oxidante. Estos resultados representan los primeros valores de potencia presentados en micro SOFC basadas en cerámicas, abriendo as. la posibilidad de desarrollar una segunda generación de micro SOFC más viables térmicamente.

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1994.
Includes bibliographical references (p. 343-360).
by Vincent Maurice McNeil.
Ph.D.

This work deals with the development of vertical thin film transistors (VTFTs) via the fabrication processes and the analysis of the electrical characteristics. The low-temperature (T ≤ 600°C) polycrystalline silicon technology is adopted in the fabrication processes. The first step of the work consists in the fabrication and characterization of VTFTs obtained by rotating the lateral thin film transistors (LTFTs) 90°. The feasibility of VTFTs fabrication is validated with an ION/IOFF ratio of about 10³, and it is analyzed that the large overlapping area between source and drain leads to a large off-current IOFF. The second step of the work lies in the partial suppression of the large overlapping area, and therefore, an ION/IOFF ratio of almost 10⁵ is obtained. The third step of the work deals with the proposal of a new VTFT structure that absolutely eliminates the overlapping area. Different improvements have been made on this new VTFT structure, especially by optimization of the following parameters: the active layer thickness, type and thickness of the barrier layer, and the geometric dimension. The optimized transistor highlights an ION/IOFF ratio of higher than 10⁵ with a reduced off-current IOFF, high stability and good reproducibility. P and N-type VTFTs have also been fabricated and showed symmetrical electrical characteristics; they are thus suitable for CMOS-like VTFT applications
Ce travail porte sur le développement de transistors en couches minces verticaux (VTFTs), du procédé de fabrication à l'analyse des caractéristiques électriques. Les transistors sont réalisés à partir de silicium polycristallin déposé et cristallisé en utilisant une technologie basse température (T ≤ 600°C). La première étape de ce travail consiste à la fabrication et la caractérisation de VTFTs obtenus par rotation de 90° des transistors à couches minces latéraux (LTFTs). La faisabilité technologique de VTFTs est alors validée, et un rapport ION/IOFF d'environ 10³ est obtenu. L'analyse des résultats de caractérisation électrique a mis en évidence que ce fort courant à l'état bloquant IOFF est principalement dû à la grande zone de recouvrement entre source et drain. La deuxième étape du travail réside dans la suppression partielle de cette zone de recouvrement qui aboutit à un rapport ION/IOFF proche de 10⁵. Dans la troisième partie de ce travail, une nouvelle architecture de transistors verticaux est proposée, qui élimine totalement la zone de recouvrement. Les effets de différents paramètres sont étudiés, notamment l'influence de l'épaisseur de la couche active, de la couche d'isolation, et de la dimension géométrique. Les transistors optimisés mettent en évidence un rapport ION/IOFF supérieur à 10⁵ avec une réduction du courant à l'état bloquant, une grande stabilité et une bonne reproductibilité du procédé technologique. Des transistors verticaux de type P et N ont également été réalisés. Ils ont montré des caractéristiques électriques symétriques, qui les rendent utilisables dans des applications similaires à la technologie CMOS

In this thesis, growth of ZrB2 thin films by direct current magnetron sputtering is investigatedusing a high vacuum industrial scale deposition system and an ultra-high vacuum laboratory scalesystem. The films were grown from ZrB2 compound targets at temperatures ranging from ambient (without external heating) to 900 °C and with substrate biases from -20 to -120 V. Short deposition times of typically 100 or 300 s and high growth rates of 80-180 nm/min were emphasized to yield films with thicknesses of 300-400 nm. The films were characterized by thinfilm X-ray diffraction with the techniques θ/2θ and ω scans, pole figure measurements andreciprocal space mapping, scanning and transmission electron microscopy, elastic recoil detection analysis and four point probe measurements. The substrates applied were Si(100), Si(111),4H-SiC(0001) and GaN(0001) epilayers grown on 4H-SiC. The Si(111), 4H-SiC(0001) substrates and GaN(0001) epilayers were chosen given their small lattice mismatches to ZrB2 making them suitable for epitaxial growth.The films deposited in the industrial system were found to be close to stoichiometric with a low degree of contaminants, with O being the most abundant at a level of < 1 at.%. Furthermore, the structure of the films is temperature dependent as films deposited in this system without external heating are fiber textured with a 0001-orientation while the films deposited at 550 °C exhibitrandom orientation. In contrast, epitaxial growth was demonstrated in the laboratory scale system on etched 4H-SiC(0001) and Si(111) deposited at 900 °C following outgassing of the substrates at 300 °C and in-situ heat treatment at the applied growth temperature to remove the native oxides. However, films grown on GaN(0001) were found to be 0001 textured at the applied deposition conditions, which make further studies necessary to enable epitaxial growth on this substrate material. Four point probe measurements on the films deposited in the industrial system show typical resistivity values ranging from ˜95 to 200 μΩcm with a trend to lower values for the films deposited at higher temperatures and at higher substrate bias voltages.

La thèse porte sur l’étude de la cinétique de Smart Cut™ dans du silicium après implantation hydrogène, pour des températures de recuit comprises entre 500°C et 1300°C. Ainsi, la cinétique de séparation de couches (splitting) est caractérisée en considérant des recuits dans un four à moufle ainsi que des recuits laser. Sur la base de cette caractérisation, un modèle physique, basé sur le comportement de l’hydrogène implanté durant le recuit, est proposé. Le modèle s’appuie sur des caractérisations SIMS de l’évolution de la concentration d’hydrogène durant le recuit, ainsi que sur des simulations numériques. Le modèle propose une explication aux propriétés des films obtenus en fonction des conditions de recuit et mesurées par microscopie optique, AFM ainsi que par des mesures des énergies d’interfaces. Sur la base du modèle de splitting obtenu, deux procédés de fabrication de films de silicium sont proposés pour l’élaboration de matériaux de silicium sur saphir et verre par recuit laser ainsi que pour l’élaboration de feuilles de silicium monocristallin par épitaxie en phase liquide sur substrat silicium implanté. L’étude de premier procédé prouve pour la première fois la possibilité d’appliquer le procédé Smart Cut™ sur des substrats de silicium implanté. Les films ainsi obtenus présentent des grandes surfaces de transfert (wafer de 200 mm), ce qui présente un grand intérêt industriel. L’étude propose différentes caractérisations des films obtenus (AFM, profilométrie optique, mesure 4 pointe). Le deuxième procédé est démontré en utilisant des bancs d’épitaxie en phase liquide de silicium (température supérieure à 1410°C) afin d’effectuer des dépôts sur des substrats de silicium implantés. Les films obtenus montrent un grand degré de croissance épitaxiale (jusqu’à 90% du film déposé mesuré par EBSD) et présentent une épaisseur aussi faible que 100 µm. D’autre part, le détachement par Smart Cut™ des films ainsi déposés est démontré
At first, the thesis studies the kinetics of Smart Cut™ in silicon implanted with hydrogen ions for annealing temperature in the range 500°C-1300°C. The kinetics is characterized by using a specially-dedicated furnace and by considering laser annealing. Based on the related characterization and observations, a physical model is established based on the behavior of implanted hydrogen during annealing. The model is strengthened by SIMS characterization focused on the evolution of hydrogen during annealing and on numerical calculations. Additionally, the model proposes an explanation for the properties of the obtained films as a function of the annealing conditions, based on optical microscope and AFM observations and bonding energy characterization. Based on this splitting model, two innovative processes for fabrication of silicon films are proposed. The first process allows to produce films of silicon on sapphire and films of silicon on glass by considering a laser annealing. The second produces foils of monocrystalline silicon by liquid phase epitaxial growth on implanted silicon substrate. The study of the first process proves for the first time the possibility to apply the Smart Cut™ for substrates of implanted silicon. The resulting films present large surface of transferred films (up to 200 mm wafers), which is very interesting in an industrial perspective. The study proposes different characterization of the films obtained by this process (AFM, optical profilometry and 4 probe measurement). The second process is demonstrated by using a chamber of liquid phase epitaxial growth of silicon (deposition temperature superior to 1410°C) in order to deposit liquid silicon on implanted silicon substrates. The obtained films show a high degree of epitaxial growth (up to 90% of the film as characterized by EBSD) and show a thickness as low as 100µm. Additionally the detachment by Smart Cut of the deposited films is demonstrated

>Magister Scientiae - MSc
Amorphous silicon carbide (a-SiC) is a versatile material due to its interesting mechanical, chemical and optical properties that make it a candidate for application in solar cell technology. As a-SiC stoichiometry can be tuned over a large range, consequently is its bandgap. In this thesis, amorphous silicon carbide thin films for solar cells application have been deposited by means of the electron-beam physical vapour deposition (e-beam PVD) technique and have been isochronally annealed at varying temperatures. The structural and optical properties of the films have been investigated by Fourier transform Infrared and Raman spectroscopies, X-ray diffraction, Scanning Electron Microscopy, Energy Dispersive X-ray Spectroscopy and UV-VIS-NIR spectroscopy. The effect of annealing is a gradual crystallization of the amorphous network of as-deposited silicon carbide films and consequently the microstructural and optical properties are altered. We showed that the microstructural changes of the as-deposited films depend on the annealing temperature. High temperature enhances the growth of Si and SiC nanocrystals in amorphous SiC matrix. Improved stoichiometry of SiC comes with high band gap of the material up to 2.53 eV which makes the films transparent to the visible radiation and thus they can be applied as window layer in solar cells.

Die Verbindung von hoch entwickelten Nanomaterialien mit fluoreszenzbasierten Technologien hat sich zu einem aufstrebenden Forschungsbereich entwickelt. Nichtsdestotrotz ist bis heute der Schritt von einem organischen Indikatormolekül zum anwendbaren Sensorsystem ein komplexer Prozess. Diese Arbeit zielte darauf ab, sensorische Materialien verschiedener chemischer Natur für diverse Analyten zu entwickeln, zu charakterisieren und zu etablieren. Hierbei wurden zunächst pH sensitive Fluoreszenzfarbstoffe entwickelt und in dünnen Membranen immobilisiert. Der Teststreifen ermöglicht die Beurteilung von pH-Änderungen mit dem Auge. Darüber hinaus wurde gezeigt, wie diese Farbstoffe auch in eine wasserlösliche Form überführt werden können. Damit konnten lokale pH-Änderungen an der Wachstumsfront von Silikat-Biomorphs detektiert werden. Auch partikuläre Systeme stellten sich als geeignete Materialien heraus. Es konnte gezeigt werden, wie die Silikat-Matrix von Partikeln zu verbesserten Eigenschaften für Farbstoffe führt. Mittels farbstoffbeladener Partikel konnte in einem Lateral-Flow-Assay ein schneller Nachweis von TATP etabliert werden. Ein anderer Ansatz verfolgte das Ziel des sensitiven Nachweises von Quecksilberionen in Wasser. In einem anderen System konnten Silikat-Nanopartikeln so funktionalisiert werden, dass ein sensitiver und selektiver Nachweis von Schwermetallionen und Anionen über ein Quencher-Displacement-Assay gelang. Zusätzlich wurde die einzigartige Oberfläche von Zellulosepartikeln mithilfe eines neu entwickelten Fluoreszenzfarbstoffs untersucht. Die untersuchten Materialien und Strategien zeigen, wie leicht innovative Moleküle für potentielle sensorische Systeme im wässrigen Medium auf Basis von fluoreszierenden Partikeln und dünnen Schichten geschaffen werden können. Das Verhalten der hergestellten Materialien wurde über spektroskopische Methoden evaluiert und dabei, wenn möglich, die Parameter Sensitivität, Selektivität und Ansprechzeit beurteilt.
The combination of fluorescence and nanomaterials has developed into an emerging research area. Nonetheless until now the step from an organic sensory molecule to a final sensor format is a complex endeavor. This thesis aimed at the preparation of particulate and thin-film based platforms for various analytes through combining the features of an appropriate host material with outstanding properties of dyes concomitant with sensitive fluorescence detection techniques. In particular, pH sensitive fluorescent probes were sterically immobilized into a thin membrane. The dip-stick allows the assessment upon change in pH with the eye. Especially a probe working at high basic pH range was converted into a water-soluble analogue and was directly applied at the growth front of silica biomorphs to detect local pH changes. But also particulate structures are suitable host materials. It is shown how the silica matrix of nanoparticles lead to improved optical properties for embedded dyes. The interactions of silica and fluorescent dyes within the pores of mesoporous particles were exploited to develop an actual sensor format based detection of TATP. In another approach it was possible to detect mercury ions in water. Heavy metal ions were also successfully detected in a quencher displacement assay involving receptor-dye functionalized silica nanoparticles. The impact of the unique surface properties of cellulose microparticles was shown by a fluorescent dye which allows an assessment of the surface functional groups and microenvironment through the reactivity and its changes in the optical properties. The performance of the prepared materials were evaluated mostly by spectroscopic methods and if possible assessed in terms of sensitivity, selectivity and response time. The newly developed and investigated materials based on fluorescent particulate and thin-films show the facile application of innovative sensor probes for potentially sensing devices.

Au cours de cette thèse, j’ai étudié la possibilité et les avantages d’utiliser des contacts nanométriques au-dessous de 1 µm. Des simulations analytiques et numériques ont montré que ces contacts nanométriques sont avantageux pour les cellules en silicium cristallin comme ils peuvent entrainer une résistance ohmique négligeable. Mon travail expérimental était focalisé sur le développement de ces contacts en utilisant des nanoparticules de polystyrène comme un masque. En utilisant la technique de floating transfert pour déposer les nanosphères, une monocouche dense de nanoparticules s’est formée. Cela nécessite une gravure par plasma de O2 afin de réduire la zone de couverture des NPs. Cette gravure était faite et étudiée en utilisant la technique de plasmas matriciels distribués à résonance cyclotronique électronique (MD-ECR). Une variété de techniques de créations de trous nanométriques était développée et testée dans des structures de couches minces et silicium cristallin. Des trous nanométriques étaient formés dans la couche de passivation, de SiO2 thermique, du silicium cristallin pour former des contacts nanométriques dopés. Un dopage local de bore était fait, à travers ces trous nanométriques par diffusion thermique et implantation ionique. En faisant la diffusion, le dopage local était observé par CP-AFM en mesurant des courbes de courant-tension à l’intérieur et à l’extérieur des zones dopées et en détectant des cellules solaires nanométriques. Par contre le processus de dopage local par implantation ionique a besoin d’être améliorer afin d’obtenir un résultat similaire à celui de diffusion
The use of point contacts has made the Passivated Emitter and Rear Cell design one of the most efficient monocrystalline-silicon photovoltaic cell designs in production. The main feature of such solar cell is that the rear surface is partially contacted by periodic openings in a dielectric film that provides surface passivation. However, a trade-off between ohmic losses and surface recombination is found. Due to the technology used to locally open the contacts in the passivation layer, the distance between neighboring contacts is on the order of hundreds of microns, introducing a significant series resistance.In this work, I explore the possibility and potential advantages of using nanoscale contact openings with a pitch between 300 nm to 10 µm. Analytic and numerical simulations done during the course of this thesis have shown that such nanoscale contacts would result in negligible ohmic losses while still keeping the surface recombination velocity Seff,rear at an acceptable level, as long as the recombination velocity at the contact (Scont) is in the range from 103-105 cm/s. To achieve such contacts in a potentially cost-reducing way, my experimental work has focused on the use of polystyrene nanospheres as a sacrificial mask.The thesis is therefore divided into three sections. The first section develops and explores processes to enable the formation of such contacts using various nanosphere dispersion, thin-film deposition, and layer etching processes. The second section describes a test device using a thin-film amorphous silicon NIP diode to explore the electrical properties of the point contacts. Finally, the third section considers the application of such point contacts on crystalline silicon by exploring localized doping through the nanoholes formed.In the first section, I have explored using polystyrene nanoparticles (NPs) as a patterning mask. The first two tested NPs deposition techniques (spray-coating, spin-coating) give poorly controlled distributions of nanospheres on the surface, but with very low values of coverage. The third tested NPs deposition technique (floating transfer technique) provided a closely-packed monolayer of NPs on the surface; this process was more repeatable but necessitated an additional O2 plasma step to reduce the coverage area of the sphere. This was performed using matrix distributed electron cyclotron resonance (MD-ECR) in order to etch the NPs by performing a detailed study.The NPs have been used in two ways; by using them as a direct deposition mask or by depositing a secondary etching mask layer on top of them.In the second section of this thesis, I have tested the nanoholes as electrical point-contacts in thin-film a-Si:H devices. For low-diffusion length technologies such as thin-film silicon, the distance between contacts must be in the order of few hundred nanometers. Using spin coated 100 nm NPs of polystyrene as a sacrificial deposition mask, I could form randomly spaced contacts with an average spacing of a few hundred nanometers. A set of NIP a-Si:H solar cells, using RF-PECVD, have been deposited on the back reflector substrates formed with metallic layers covered with dielectrics having nanoholes. Their electrical characteristics were compared to the same cells done with and without a complete dielectric layer. These structures allowed me to verify that good electrical contact through the nanoholes was possible, but no enhanced performance was observed.In the third section of this thesis, I investigate the use of such nanoholes in crystalline silicon technology by the formation of passivated contacts through the nanoholes. Boron doping by both thermal diffusion and ion implantation techniques were investigated. A thermally grown oxide layer with holes was used as the doping barrier. These samples were characterized, after removing the oxide layer, by secondary electron microscopy (SEM) and conductive probe atomic force microscopy (CP-AFM)

Un nouvel essai mécanique a été développé pour répondre à la demande d'analyse des propriétés mécaniques des revêtements et films d'épaisseur nanométrique par essai de gonflement. La méthode utilisée est l'application d'une différence de pression sur une membrane non supportée, usinée en utilisant les techniques standards de gravure microélectronique. Le banc d'essai permettra d'effectuer des essais à haute température (au dessus de 900°C). La principale difficulté rencontrée a été la mise au point d'une méthode de mesure de la déflection de la membrane qui perturbe celle ci aussi peu que possible. Deux techniques ont été utilisées : capteur ponctuel et capteur interférométrique 2D avec référence sphérique. La première technique, plus simple, s'est révélée difficilement praticable, en particulier dans le cas de flambage de la membrane. La mise en place de la deuxième a nécessité une description fine du comportement du système optique (distorsion des images, calcul des interférogrammes) aboutissant à une méthode de mesure simple, susceptible d'être intégrée en ligne au système de contrôle de l'interféromètre, et complétée par un traitement complet des données après essai.Afin de valider l'essai, deux types de revêtements ont été caractérisés. Tout d'abord des films fragiles de nitrure de silicium et de silicium pour mettre en évidence la fiabilité et la reproductibilité des essais. Puis des films minces d'or pour observer l'influence de la microstructure sur le début de la déformation plastique
A new mechanical testing device of free standing membranes by Bulge Test has been built at Institute Jean Lamour in order to investigate the mechanical properties of thin films of nanometric thickness. The Bulge Test measures the deflection of a free standing membrane to which a differential atmospheric pressure has been applied. (The specimens are prepared from film on substrate deposits by cutting a window within the substrate by standard microelectronic techniques.) We aim of achieve tests from room temperature to ~ 900°C. The main technical difficulty met during this work was to develop a non perturbating method of measurement of the film bulge. Two different techniques were tested: point measurement and 2D interferometry using a spherical reference. The first technique, however simple, was difficult to practice, especially in the case of buckling membranes. The second method required a detailed analysis of the whole optical system (image distorsion, calculation of interferograms) leading to a simple measurement method, suitable for integration in the acquisition and command chain of the device, followed by an off line full treatment.The operating method was used on two different sets of specimens: fragile silicon nitride and silicon membranes in order to test the reproducibility of the device. Polycrystalline gold thin films were then used to study the early stage of plastic strain

The first block of this thesis deals with the study of the degradation process of tungsten catalytic filaments in the field of silicon deposition with the Hot Wire Chemical Vapour Deposition (HWCVD) technique. The development of technological solutions addressed to the filaments protection will also be dealt as well as the design, fabrication and performance of a novel system for the automatic replacement of used filaments in a HWCVD reactor. The second block deals with the scaling up of HWCVD towards large area deposition and the existence of a scaling law that may allow the deposition of microcrystalline silicon (µc-Si:H) at high rate preserving the material quality.
El primer bloc d'aquesta tesi es centra en l'estudi del procés de degradació dels filaments de tungstè catalítics en el camp de la deposició de silici amb la tècnica de dipòsit químic en fase vapor assistida per filament calent (HWCVD). També es tractarà el desenvolupament de solucions tecnològiques dirigides a la protecció filaments i al reemplaçament d’aquests de forma automàtica, sense interrompre el procés. El segon bloc tracta sobre l’escalat de la tècnica HWCVD cap a gran àrea i sobre l'existència d'una llei d'escala que permeti la deposició de silici microcristal•lí a altes velocitats, tot preservant la qualitat del material.

This thesis presents my work on the fabrication of nanocrystalline silicon (nc-Si) thin film transistors and characterization of their stability under different conditions. Nc-Si transistors are promising alternative to the current amorphous silicon (a-Si:H) devices, especially in areas where a-Si:H TFTs are reaching the performance ceiling, e.g. new large area applications such as active matrix organic light emitting diode displays (AMOLED). This is mostly due to the superior nc-Si properties – high carrier mobility and good electrical stability stemming from the crystalline Si grains embedded in a disordered a-Si:H matrix. Another large advantage of nc-Si TFTs over competing materials is the full compatibility with the a-Si:H fabrication base. Nanocrystalline silicon is a relatively new material and some aspects require further investigation before industrial applications. The pool of knowledge on nc-Si devices is especially shallow for the electrical stability of bottom gate TFTs under prolonged illumination which is important for several thin film applications, such as AMOLED and phototransistors. This issue was selected as the main topic of the thesis. Top gate TFTs were also designed, fabricated, characterized and compared to the bottom gate transistors. The electrically detected magnetic resonance method was employed to investigate the nc-Si/dielectric structures and it was shown that it can be used to evaluate the TG TFT channel/dielectric interface.

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 2005.
Includes bibliographical references (p. 147-158).
Monolithic integration has been implemented successfully in complementary metal oxide semiconductor (CMOS) technology and led to improved device performance, increased reliability, and overall cost reduction. The next element to be incorporated on the silicon chip is the power unit; possibly as part of the back end process of the very large scale integrated (VLSI) circuits' production. This thesis describes the work done in developing and studying thin film integrated lithium ion batteries compatible with microelectronics with respect to the material system employed, the cells' fabrication methods, and performance. The project consisted of three stages; first, a material system new to the battery application field was explored and power cells were fabricated and characterized. In the second stage, the fabrication process of the first material system cells was optimized thereby improving their performance. The third stage dealt with a more conventional battery material system, utilizing thin film technology to fabricate and explore power cells.
(cont.) All the cells fabricated in this work were created using microelectronic technology and were characterized by thin film analysis techniques and by measurement equipment commonly used for microelectronic device testing. The cells were fabricated in four sizes of active areas: 5x5 mm², 2x2 mm², lxl mm², and 0.5x0.5 mm². The first material system consisted of a novel lithium-free electrolyte in the form of an ultra-thin SiO₂ layer, thermally grown from sacrificial polysilicon layer on a doped polysilicon anode. The concept of SiO₂ as an electrolyte is innovative since common solid state lithium and lithium ion batteries consist of 1-2 ptm thick lithium-containing electrolytes. The controlled transport of lithium through SiO₂, 9-40 nm thick, was studied for electrolyte application. The fabricated LiCoO₂/SiO₂/polysilicon cells were successfully charged and discharged. This stage of the project demonstrated the concept of an ultra-thin lithium free electrolyte layer and introduces SiO₂ as an interesting candidate material. The second stage of the project focused on improving the LiCoO₂/SiO₂/polysilicon cell's performance and optimizing its fabrication process.
(cont.) Chemical mechanical polishing (CMP), a typical planarization method in microelectronics, new to the battery application field, was introduced in order to enhance the cell's properties and performance. LiCoO₂/SiO₂/polysilicon cells consisting of Si0₂ layers 7-40 nm thick were studied. Cells with the planarized polysilicon anode were characterized and the planarization effect was evaluated. This stage demonstrates the importance of interfacial quality in thin film batteries and the advantages incorporation of CMP as a planarization step in the fabrication process. Finally, the third stage of the project focused on applying the thin film technology knowledge and expertise to a more commonly used material system V₂0₅/LiPON/LiCoO₂. With the aim of reducing interfacial roughness, a surface morphology study of V₂0₅ was performed, tailoring different deposition conditions and surface morphology. Implementing the optimized conditions obtained from this analysis, a V₂0₅/LiPON/LiCoO₂ rocking-chair battery was studied next. The cells consisted of approximately 100 or 350 nm thick lithium phosphorus oxynitride (LiPON) electrolyte.
(cont.) This stage demonstrated the advantage of thin film technology in reducing film thickness and the performance enhancement achieved. The work described in this thesis approached the thin film battery subject from the microelectronic perspective, in order to "bring the battery into the clean room".
by Nava Ariel.
Ph.D.

Dans la premiere partie de la these, nous presentons un nouveau mode de fonctionnement des transistors mos sur silicium sur isolant, qui consiste dans l'inversion forte et totale du film de silicium. Nous presentons ensuite les avantages induits par ce nouveau mode de fonctionnement. Nous montrons aussi qu'il est possible d'etablir, dans les deux cas extremes de transistors a film de silicium respectivement tres mince et tres epais, des modeles analytiques simples qui decrivent adequatement le fonctionnement electrique des tmos a volume inverse (tmos-vi) en regime ohmique. La deuxieme partie est consacree a la presentation des diverses techniques numeriques et equations physiques que nous avons retenues pour la realisation du simulateur electrique bidimensionnel des structures tmos-ssi: isis ii. L'objet de la troisieme partie est d'illustrer les possibilites d'etudes par la simulation electrique des dispositifs ssi, offertes par isis ii

O desempenho de componentes de engenharia está intimamente ligado a fenômenos de superfície, pois esta funciona como a interface entre o componente e o ambiente que o cerca. A escolha de um material com propriedades superficiais adequadas é fundamental para a sua funcionalidade. Neste trabalho as propriedades físico-químicas, estruturais e mecânicas do filmes de nitreto de silício depositados por magnetron sputtering reativo com uma fonte de radiofreqüência, antes e após tratamento térmico em 18O2, foram analisadas por diferentes métodos, tais como nanodureza, difração de raios X, perfilometria por reação nuclear ressonante, nanoindentação, espectrometria de retroespalhamento Rutherford, espectroscopia de fotoelétrons induzidos por raios X e reflectometria de raios X. Os filmes de Si3N4 depositados são essencialmente amorfos, estequiométricos e livres de contaminantes para vários parâmetros de deposição, com valores de dureza que variam de 16,5 GPa 22 GPa, dependendo principalmente da temperatura de deposição dos filmes. Depois de realizado o tratamento térmico em 18O2 a 1000 °C, a dureza de filmes converge para 21 GPa, independentemente da temperatura de deposição o que é explicado com base na cristalização dos filmes nesta temperatura de tratamento térmico. Além disso, o oxigênio é incorporado apenas 7,5 nm do filme de Si3N4, formando oxinitreto de silício na superfície do filme, indicando uma boa resistência à oxidação em altas temperaturas. Finalmente, a deformação elástica até a fratura H3/E2, que é um bom indicador da resistência ao desgaste do filme, dobra após o tratamento térmico a 1000 °C. Estas observações mostram o grande potencial do nitreto de silício como um revestimento duro para aplicações em altas temperaturas.
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The performance of engineering components is closely tied to surface phenomena, because it acts as an interface between the component and the environment that surrounds it. The choice of a suitable material with surface properties is critical to its functionality. In this study the physicochemical, structural and mechanical properties of silicon nitride films deposited by radio frequency reactive magnetron sputtering before and after thermal annealing in 18O2 were analyzed using different methods, such as nanohardness, X-ray diffraction, profilometry resonant nuclear reaction, nanoindentation, Rutherford backscattering spectrometry, photoelectron spectroscopy and X-ray induced X-ray reflectometry The Si3N4 films deposited are essentially amorphous, stoichiometric and free of contaminants for various deposition parameters, with hardness values ranging from 16.5 GPa 22 GPa, depending mainly on the deposition temperature of films. After 18O2 annealing at 1000°C, films hardness converged to 21 GPa, independently of the deposition temperature, which is explained on the basis of crystallization of the films at this annealing temperature. Furthermore, oxygen is incorporated only in the 7.5 nm film of Si3N4, forming silicon oxynitride on the surface of the film, indicating good oxidation resistance at high temperature. Finally, the elastic strain to failure H3/E2, which mimics the wear resistance of the film, doubles after the 1000°C annealing. These observations show the great potential of silicon nitride as a hard coating for high temperature applications.

Thin-film silicon photovoltaics are seen as a good possibility for reducing the cost of solar electricity. The focus of this thesis is the ALICIA cell, a thin-film polycrystalline silicon solar cell made on a glass superstrate. The name ALICIA comes from the fabrication steps - ALuminium Induced Crystallisation, Ion Assisted deposition. The concept is to form a high-quality crystalline silicon layer on glass by Aluminium Induced Crystallisation (AIC). This is then the template from which to epitaxially grow the solar cell structure by Ion Assisted Deposition (IAD). IAD allows high-rate silicon epitaxy at low temperatures compatible with glass. In thin-film solar cells, light trapping is critical to increase the absorption of the solar spectrum. ALICIA cells have been fabricated on textured glass sheets, increasing light absorption due to their anti-reflection nature and light trapping properties. A 1.8 μm thick textured ALICIA cell absorbs 55% of the AM1.5G spectrum without a back-surface reflector, or 76% with an optimal reflector. Experimentally, Pigmented Diffuse Reflectors (PDRs) have been shown to be the best reflector. These highly reflective and optically diffuse materials increase the light-trapping potential and hence the short-circuit currents of ALICIA cells. In textured cells, the current increased by almost 30% compared to using a simple aluminium reflector. Current densities up to 13.7 mA/cm2 were achieved by application of a PDR to the best ALICIA cells. The electronic quality of the absorber layer of ALICIA cells is strongly determined by the epitaxy process. Very high-rate epitaxial growth decreases the crystalline quality of the epitaxial layer, but nevertheless increases the short-circuit current density of the solar cells. This indicates that the diffusion length in the absorber layer of the ALICIA cell is primarily limited by contamination, not crystal quality. Further gains in current density can therefore be achieved by increasing the deposition rate of the absorber layer, or by improving the vacuum quality. Large-area ALICIA cells were then fabricated, and series resistance reduced by using an interdigitated metallisation scheme. The best measured efficiency was 2.65%, with considerable efficiency gains still possible from optimisation of the epitaxial growth and metallisation processes.

In this research, the optoelectronic and structural properties of thin film silicon carbide (SiC) prepared by plasma enhanced chemical vapour deposition and excimer (ArF) laser crystallisation are presented. These materials have been utilised as p-i-n electroluminescent devices, including development of various novel device structures. A wide-ranging series of experiments aimed at optimising the deposition conditions of amorphous and microcrystalline SiC films are described. Dark conductivity, photoconductivity, photoluminescence, optical absorption by Swanepoel's method and constant photocurrent method (CPM), scanning and transmission electron microscopy, infrared spectroscopy, and elastic recoil detection analysis were employed to characterise the films. Absorption spectra and the density of states profile of amorphous silicon carbide as found by CPM are reported. As the carbon content increases, the valence band tail becomes broader. At the same time, the deep defect density of states increases and also becomes broader. The CPM data also verified that the band gap widening is due to the conduction band shifting with increasing carbon content. It is shown that H₂ dilution leads to an improvement of electronic properties via a decrease in the density of localised states. A novel method has been developed to prepare highly conductive and wide band gap doped microcrystalline silicon carbide (μc-SiC) by excimer (ArF) laser crystallisation. After crystallisation, this material has Tauc gap of around 2.0 eV and exhibits a dark conductivity as high as 20 (Ωcm)^-1, more than ten orders of magnitude higher than before the laser irradiation. This is shown to be mainly correlated to structural change. The dopant concentration plays a dominant role in the electrical transport properties of μc-SiC, regardless of type of dopant and carbon concentration up to 30 at.%. Laser crystallised μc-SiC can be utilised not only as the carrier injection layer in a-SiC:H based electroluminescent devices, but also as a luminescent layer. EL devices fabricated with μc-SiC as a hole injector possess the highest electroluminescent intensity, the most stable emission and the longest operating life-time among all the investigated device structures. The electroluminescence from these devices is possibly related to the formation of some form of porous SiC by laser crystallisation.

Au vu des limitations rencontrées par la miniaturisation des circuits microélectroniques, l’augmentation de performances des systèmes repose largement aujourd’hui sur la fabrication d’empilements de couches minces complexes et innovants pour offrir davantage de compacité et de flexibilité. L’intérêt grandissant pour la réalisation de structures innovantes temporaires, i.e. permettant de réaliser des circuits sur les deux faces d’un même film, nous a mené à évaluer les potentialités d’une technologie combinant le transfert de films minces monocristallins, i.e. la technologie Smart Cut™, et un procédé de de porosification partielle du silicium afin de mettre au point une technologie de double report de film monocristallin. En ce sens, des substrats de silicium monocristallin ont été partiellement porosifiés par anodisation électrochimique. La mise en œuvre de traitements de substrats partiellement poreux a nécessité l’emploi de techniques de caractérisation variées pour dresser une fiche d’identité des couches minces poreuses après anodisation et évaluer l’évolution des propriétés de ces couches en fonction des différents traitements appliqués. Les propriétés chimiques, structurales et mécaniques des couches de Si poreux ont ainsi été étudiées via l’utilisation de différentes techniques de caractérisation (XPS-SIMS, AFM-MEB-XRD, nanoindentation, technique d’insertion de lame, etc.). Ces études ont permis d’appréhender et de décrire les mécanismes physiques mis au jeu au cours des différents traitements et de déterminer les caractéristiques {porosité, épaisseur} optimales des couches poreuses compatibles avec les séquences de la technologie proposée. La technologie Smart Cut™ a ainsi été appliquée à des substrats partiellement porosifiés menant à la fabrication réussie d’une structure temporaire de type Silicium-sur-Isolant avec une couche de silicium poreux enterrée. Ces structures temporaires ont été « démontées » dans un second temps par collage polymère ou collage direct et insertion de lame menant au second report de film mince monocristallin par rupture au sein de la couche porosifiée et donc fragile. Les structures fabriquées ont été caractérisées pour vérifier leur intégrité et leurs stabilités chimique et mécanique. Les propriétés cristallines du film mince de Si monocristallin, reporté en deux temps, ont été vérifiées confirmant ainsi la compatibilité des structures fabriquées avec des applications microélectroniques telles que les applications de type « Back-Side Imager » nécessitant une implémentation de composants sur les deux faces du film. Ainsi une technologie prometteuse et performante a pu être élaborée permettant le double report de films minces monocristallins et à fort potentiel pour des applications variées comme les imageurs visibles ou le photovoltaïque
As scaling of microelectronic devices is confronted from now to fundamental limits, improving microelectronic systems performances is largely based nowadays on complex and innovative stack realization to offer more compaction and flexibility to structures. Growing interest in the fabrication of innovative temporary structures, allowing for example double sided layer processing, lead us to investigate the capability to combine one technology of thin single crystalline layer transfer, i.e. the Smart Cut™ technology, and partial porosification of silicon substrate in order to develop an original double layer transfer technology of thin single crystalline silicon film. To this purpose, single crystalline silicon substrates were first partially porosified by electrochemical anodization. Application of suitable treatments of porous silicon layer has required the use of several characterization methods to identify intrinsic porous silicon properties after anodization and to verify their evolution as function of different applied treatments. Chemical, structural and mechanical properties of porous silicon layers were studied by using different characterization techniques (XPS-SIMS, AFM-MEB-XRD, nanoindentation, razor blade insertion, etc.). Such studies allowed comprehending and describing physical mechanisms occurring during each applied technological steps and well determining appropriated {porosity, thickness} parameters of porous silicon layer with the developed technological process flow. The Smart Cut™ technology was successfully applied to partially porosified silicon substrates leading to the fabrication of temporary SOI-like structures with a weak embedded porous Si layer. Such structures were then “dismantled” thanks to a second polymer or direct bonding and razor blade insertion to produce a mechanical rupture through the fragile embedded porous silicon layer and to get the second thin silicon film transfer. Each fabricated structure was characterized step by step to check its integrity and its chemical and mechanical stabilities. Crystalline properties of the double transferred silicon layer were verified demonstrating the compatibility of such structures with microelectronic applications such as “Back-Side Imagers” needing double-sided layer processing. Eventually, a promising and efficient technology has been developed to allow the double transfer of thin single crystalline silicon layer which presents a high potential for various applications such as visible imagers or photovoltaic systems

n-channel and p-channel amorphous-silicon thin-film transistors (a-Si:H TFTs) with copper electrodes prepared by a novel plasma etching process have been fabricated and studied. Their characteristics are similar to those of TFTs with molybdenum electrodes. The reliability was examined by extended high-temperature annealing and gate-bias stress. High-performance CMOS-type a-Si:H TFTs can be fabricated with this plasma etching method. Electrical characteristics of a-Si:H TFTs after Co-60 irradiation and at different experimental stages have been measured. The gamma-ray irradiation damaged bulk films and interfaces and caused the shift of the transfer characteristics to the positive voltage direction. The field effect mobility, on/off current ratio, and interface state density of the TFTs were deteriorated by the irradiation process. Thermal annealing almost restored the original state's characteristics. Floating gate n-channel a-Si:H TFT nonvolatile memory device with a thin a- Si:H layer embedded in the SiNx gate dielectric layer has been prepared and studied. The hysteresis of the TFT's transfer characteristics has been used to demonstrate its memory function. A steady threshold voltage change between the "0" and "1" states and a large charge retention time of > 3600 s with the "write" and "erase" gap of 0.5 V have been detected. Charge storage is related to properties of the embedded a-Si:H layer and its interfaces in the gate dielectric structure. Discharge efficiencies with various methods, i.e., thermal annealing, negative gate bias, and light exposure, separately, were investigated. The charge storage and discharge efficiency decrease with the increase of the drain voltage under a dynamic operation condition. Optimum operating temperatures are low temperature for storage and higher temperature for discharge. a-Si:H metal insulator semiconductor (MIS) capacitor with a thin a-Si:H film embedded in the silicon nitride gate dielectric stack has been characterized for memory functions. The hysteresis of the capacitor's current-voltage and capacitance-voltage curves showed strong charge trapping and detrapping phenomena. The 9 nm embedded a-Si:H layer had a charge storage capacity six times that of the capacitor without the embedded layer. The nonvolatile memory device has potential for low temperature circuit applications.

The growth of amorphous hydrogenated silicon (a-Si:H) thin films deposided by hot wire chemical vapor deposition (HWCVD) has been studied. The films have been characterised for optical and structural properties by means of UV/VIS,FITR,ERDA, XRD.XTEM and Raman spectroscopy. Low subtrate heater temperatures in the range form 130 to 200 degrees celcius were used in this thesis because it is believed to allow for the deposition of device quality a-Si:H which can be used for electronic photovoltaic devices. Furthermore, low temperatures allows the deposition of a-Si:H on any subtrate and thus offers the possibility of making large area devices on flexible organic substances. We showed that the optical and structural properties of grown a-Si:H films depended critically upon whether the films were produced with silane gas or silane diluted with hydrogen gas. We also showed that it is possible to to deposit crystalline materials at low temperature under high hydrogen dilution ratio of silane gas.

Dielectric thin films have a long history in silicon photovoltaics. Due to the specific physical properties, they can function as passivation layer in solar cells. Also, they can be used as antireflection coating layers on top of the devices. They can improve the back surface reflectance if proper dielectric layers combination is used. What??s more, they can protect areas by masking during chemical etching, diffusion, metallization among the whole fabrication process. Crystalline silicon solar cell can be passivated by two ways: one is to deposit dielectric thin films to saturate the dangling bonds; the other is to introduce surface electrical field and repel back the minority carriers. This thesis explores thermally grown SiO2 and sputtered Si3N4(:H) to passivate n-type and thermal evaporation AlF3 to passivate p-type Float Zone silicon wafers, respectively. Sputtering is a cheap passivation method to replace PECVD in industry usage, but all sputtered samples are more likely to have encountered surface damage from neutral Ar and secondary electrons, both coming from the sputtered target. AlF3/SiO2 multi-layer stack is a negative charge combination; p inversion layer will form on the wafer surface. Light trapping is an important part in solar cell research work. In order to enhance the reflectance and improve the absorption possibility of near infrared photons, especially for high efficiency PERL cell application, the back surface structure is optimized in this work. Results show SiO2/Ag is a very good choice to replace SiO2/Al back reflectors. The maximum back surface reflectance is 97.82%. At the same time, SiO2/Ag has excellent internal angle dependence of reflectance, which is beneficial for surface textured cells. A ZnS/MgF2/SiO2/Al(Ag) superlattice can improve the back reflectance, but it is sensitive to incident angle inside the silicon wafer. If planar wafers are used to investigate all kinds of back reflectors, and an 8 degrees incident angle is fixed for typical spectrometry measurement, the results are easy to predict by Wvase software simulation. If a textured surface is considered, the light path inside the silicon wafer is very complicated and hard to calculate and simulate. The best way to evaluate the result is through experiment.

Thin-film silicon solar cells have the potential to convert sunlight into electricity at high efficiency, low cost and without generating pollutants. However, they need to become more competitive with conventional energy technologies by increasing their efficiency. One of the key efficiency limitations of using thin silicon absorber materials relates to the optical loss of low-energy photons, because the absorption coefficient of silicon decreases strongly for these low-energy photons in the red and near-infrared, such that the absorption length becomes longer than the absorber layer thickness. If, in contrast, the incident light was redirected and trapped into the plane of the silicon slab, a thin-film could absorb as much light as a thick layer. Diffractive textures can not only efficiently scatter the low-energy photons, but are also able to suppress the reflection of the incident sunlight. In order to take advantage of the full benefits that textures can offer, I outline a simple layer transfer technique that allows the structuring of a thin-film independently from both sides, and use absorption measurements to show that structuring on both sides is favourable compared to structuring on one side only. I also introduce a figure-of-merit that can objectively and quantitatively assess the benefit of the structuring itself, which allows me to benchmark state-of-the-art proposals and to deduce some important design rules. Minimising the parasitic losses, for example, is of critical importance, as the desired scattering properties are directly proportional to these losses. To study the impact of parasitics, I quantify the useful absorption enhancement of two different light trapping mechanisms, i.e. diffractive vs plasmonic, based on a fair and simple experimental comparison. The experiment demonstrates that diffractive light-trapping is a better choice for photovoltaic applications, because plasmonic structures accumulate the parasitical losses by multiple interactions with the trapped light. The results of this thesis therefore highlight the importance of diffractive structures as an effective way of trapping more light in a thinner solar cell device, and will help to define guidelines for new designs that may overcome the 30% power conversion efficiency limit.

This thesis discusses the growth of thin-film silicon layers suitable for solar cells using liquid phase epitaxy and the behaviour of oxide LPCVD silicon nitride stacks on silicon in a high temperature ambient.¶ The work on thin film cells is focussed on the characteristics of layers grown using liquid phase epitaxy. The morphology resulting from different seeding patterns, the transfer of dislocations to the epitaxial layer and the lifetime of layers grown using oxide compared with carbonised photoresist barrier layers are discussed. The second half of this work discusses boron doping of epitaxial layers. Simultaneous layer growth and boron doping is demonstrated, and shown to produce a 35um thick layer with a back surface field approximately 3.5um thick.¶ If an oxide/nitride stack is formed in the early stages of cell processing, then characteristics of the nitride may enable increased processing flexibility and hence the realisation of novel cell structures. An oxide/nitride stack on silicon also behaves as a good anti- reflection coating. The effects of a nitride deposited using low pressure chemical vapour deposition on the underlying wafer are discussed. With a thin oxide layer between the silicon and the silicon nitride, deposition is shown not to significantly alter effective life-times.¶ Heating an oxide/nitride stack on silicon is shown to result in a large drop in effective Lifetimes. As long as at least a thin oxide is present, it is shown that a high temperature nitrogen anneal results in a reduction in surface passivation, but does not significantly affect bulk lifetime. The reduction in surface passivation is shown to be due to a loss of hydrogen from the silicon/silicon oxide interface and is characterised by an increase in Joe. Higher temperatures, thinner oxides, thinner nitrides and longer anneal times are all shown to result in high Joe values. A hydrogen loss model is introduced to explain the observations.¶ Various methods of hydrogen re-introduction and hence Joe recovery are then discussed with an emphasis on high temperature forming gas anneals. The time necessary for successful Joe recovery is shown to be primarily dependent on the nitride thickness and on the temperature of the nitrogen anneal. With a high temperature forming gas anneal, Joe recovery after nitrogen anneals at both 900 and 1000oC and with an optimised anti-reflection coating is demonstrated for chemically polished wafers.¶ Finally the effects of oxide/nitride stacks and high temperature anneals in both nitrogen and forming gas are discussed for a variety of wafers. The optimal emitter sheet resistance is shown to be independent of nitrogen anneal temperature. With textured wafers, recovery of Joe values after a high temperature nitrogen anneal is demonstrated for wafers with a thick oxide, but not for wafers with a thin oxide. This is shown to be due to a lack of surface passivation at the silicon/oxide interface.

The continuous trend towards mega-functional, high-performance and ultra-miniaturized system has been driving the need for advances in novel materials with superior properties leading to thin components, high-density interconnect substrates and interconnections. Power supply and management is becoming a critical bottleneck for the advances in such mega-functional systems because power components do not scale down with the rest of the system resulting in bulky and stand-alone power modules. Amongst the power components, thin film capacitors are considered the most challenging to integrate because of several manufacturability concerns. The challenges are related to process compatibility of high permittivity dielectrics with substrates and high surface area electrodes, yield, leakage and losses. This thesis focuses on novel thin film capacitor technologies that address some of these critical challenges.
Thesis advisor has approved the addition of errata to this item. The abstract text in the metadata record has been modified to match the document text.

碩士
南榮技術學院
工程科技研究所碩士班
99
The output value of flat-panel displays various end-use applications with the strong demand continues to grow, while the thin film transistor (TFT) liquid crystal display (LCD) technology has become a major disposal, among which the growth of thin LCD TV applications, the most prominent. At present the panel makers are committed to integrate various technologies to develop high-quality, low-power thin LCD television, with an eye on the development of other new applications. This thesis is based on chemical vapor deposition (CVD) in the TFT-LCD manufacturing process to the existing process temperature of 300 degrees, will be made available lower the temperature to 200 degrees, and the choice of the glass substrate can be used alkali metals sodium or calcium ions of the glass to produce TFT-LCD panels, LCD panels help reduce production costs on the other hand, lower temperatures also contribute to the process of development towards flexible displays and glass cost reduction.

博士
國立清華大學
電子工程研究所
95
A low-dielectric-constant (low-k) material, siloxane-based hydrogen silsesquioxane (HSQ), is investigated as a passivation layer in bottom-gate hydrogenated amorphous silicon thin film transistors (a-Si:H TFTs). The low-k HSQ film passivated on TFT promotes the brightness and aperture ratio of TFT-LCD due to its high light transmittance and good planarization. Also, the performance of a-Si:H TFT with HSQ passivation has been improved, compared to a conventional silicon nitride (SiNx) passivated TFT, due to that the hydrogen bonds of HSQ assist the hydrogen incorporation to eliminate the density of states between back channel and passivation layer. Experimental results exhibit an improved field-effect mobility of 0.57 cm2/Vs and subthreshold swing of 0.68 V. Next, a novel spin-on low-k material, photosensitive Polymethylsilazane (PS-MSZ), directly patterned by i-line stepper has been investigated for BCE a-Si TFT passivation layer. The presence of PS-MSZ with good transmittance and planarization reduces the RC delay between gate and data-line, and promotes the aperture ratio of TFT-LCD panel. The direct patterning technique simplifies the process, decreasing cost without the vacuum system and etching steps. The TFT transfer characteristics are not significantly impacted by the PS-MSZ passivation layer. In addition, the PS-MSZ passivated TFT has low leakage current in reverse subthreshold region due to its spin-on deposition. On the other hand, another new direct pattern low-k material, polymer, will also be proposed to be a passivation layer and to compare with PS-MSZ film, which can also applied on TFT device. On study the back channel effect, the mechanism of back channel leakage between a-Si:H film and passivation layer has been demonstrated. There are two factors affected back channel leakage very much. These factors are fixed charge and interface states. These factors will impact TFT reverse subthreshold characteristics (operation bias at small negative gate voltage) and lead to back channel effect. Fixed charges bend the band and accumulate electrons at back channel. We use forward and reverse sweep measurement at different temperature to confirm back channel leakage mechanism. When TFT device is operated at Vg= 20 ~ -20V, there is a different phenomenon which let threshold voltage increased and back channel leakage decreased. There are lots of electrons trapping in amorphous silicon film when the initial operating voltage is a large positive bias. These trapping electrons will block other electrons entering amorphous silicon film, including back channel region. These trapping electrons in amorphous silicon film made an additional barrier which blocked electron transition, especially at small gate bias operation. This kind of conduction mechanism is similar to space-charge-limited current conduction (SCLC). These trapping electrons in amorphous silicon film are temporary. Therefore, these trapping electrons will be excited at a high temperature environment. Once trapping electrons excited, the blocking barrier decreases and the device conduction mechanism is back to initial type. Therefore, for TFT transfer characteristics, fixed charges existing passivation layer and interface states is the main reason which result in back channel leakage. The dual-gate a-Si:H TFT owns superior conducting ability than conventional TFT which contains an additional electron path at back channel. Positive back gate bias leads to an increasing in drain current. The dual-gate a-Si:H TFT also exhibits the better endurance against photo leakage current than conventional a-Si:H TFT. When dual gate driving bias becomes negative, conduction band and valence band are bending up by dual gate which lead the photo excited electron-hole pairs to be confined. The confined electron-hole pairs may be easily recombined by lots of DOS in a-Si:H film. Otherwise, under negative dual gate bias, Fermi level is near valence band. At this time, photo excited electron-hole pairs would probably be recombined immediately by those lots of traps when they generated.

碩士
國立臺灣科技大學
電子工程系
95
In order to realize the purpose of plastic substrate thin film transistor , We have successfully deposited semitransparent film that the main composition of the film is silicon nitride by using reactive sputtered method. And, it has light absorption (absorption coefficient from 0 to 56000 cm-1) that can be applied as heat retaining layer to get Low Temperature poly-Si on plastic substrates after excimer laser annealing. By adjusting the flow rate of Ar and N2, we can control the absorption coefficient of the semitransparent film at will.After get the optimum condition of the semitransparent and using this film as heat retaining layer for the 90nm thick silicon, we use excimer laser and have successfully obtained poly-Si on plastic substrates. It’s grain size can reache to 5um.

碩士
大同大學
光電工程研究所
97
This thesis will discuss two different chapters. First, fabrication of low temperature poly-silicon TFTs by using oxide and n+ a-Si by PECVD and the poly-Si and n+ poly-si are obtained by the EAA technique that we develop before. We will discuss the effect of off-state leakage on the different thickness of n+ poly-Si.

碩士
國立清華大學
電子工程研究所
88
Thin film Au(80)Sn(20) solder layer ( about 0.8um~2um of thickness ) was utilized for flip-chip bonding. For different optoelectronic devices, we tried several bonding parameters — reflow temperature, reflow arm z-position, solder thickness on chip or substrate or both — to get the optimized condition. From the results of shear force tests, we believed that thin film solder layer could provide acceptable shear strength. The flip-chip bonded 1.55um laser diode showed excellent L-I(CW) and I-V characteristics compared to pre-bonded bare chip. To verify its thermal stability, it was tested by thermal shock test. After 500 thermal cycles, the characteristics of bonded chips show no noticeable degradation. So it is believed that using thin film solder layer could obtain both acceptable mechanical strength and good thermal stability. We also tested the flip-chip bonded PIN photodiode utilizing its p-type diffusion window as bonding interface. Under higher reflow temperature ( 310℃), it showed lower contact resistance because of sufficient interdiffusion between Au and AuSn, but the dark current became larger due to the induced stress during reflow. Under lower reflow temperature (290℃), the dark current was close to that of pre-bonded bare chip, while the contact resistance became larger. In summary, the thin film flip-chip bonding technique showed good feasibility for integration of optoelectronic devices and silicon substrates.

碩士
國立暨南國際大學
光電科技碩士學位學程在職專班
100
Low Temperature Poly-Silicon is the silicon based material. It’s composed by many silicon crystalline grains size around 0.3 to several million um. High Temperature Solid Phase Crystallization (HSPC) that required annealing temperature higher than 900°C is the traditional way of making semi-conductive HSPC is not suitable for making liquid crystal display (LCD)， since glass will deformation at 650°C， which is much lower than required temperature for HSPC. Therefore， the Low Temperature Poly-Silicon membrane was developed for the manufacture of the LCD. Our study is focus on the most widely used technique called Excimer Laser Annealing. We used 308 nm Excimer laser to scan the Amorphous silicon. The Amorphous silicon then becomes polycrystalline silicon or non-crystalline silicon membrane. To help the non-crystalline silicon absorb laser energy, two layers of SiOX&SiNx were placed underneath the amorphous silicon. This layer can also help prevent the laser penetration and serve as the protection for the glass surface. In this study , we first exam how Excimer laser scan effects the Low Temperature Poly-Silicon crystal size by analysis laser frequency， coverage， and energy density. The optima carrier Mobility and Voltage ，an electric current was also measured and determined by Test Element Group The experiments show than， during the incomplete saturation phase , the grain size is depend on the amount of the energy that Amorphous-Silicon Thin Film absorbed. However ,the grain size become smaller due to the over during the saturated phase. This phoneme becomes very obvious as the laser energy increases. The carrier Mobility is in directly proportional to the grain size during incomplete saturation phase. However， the carrier Mobility decreases when grain size decreases. Although we can reach the best carrier Mobility during saturated phase, the overall variation also increase dramatically. Therefore, it’s not suitable for the mass production. In conclusion, the best laser wavelength is one energy level lower than the saturated phase energy level.

碩士
國立成功大學
工業與資訊管理學系專班
100
Corporates often spend their capital expenditures in developing new technologies and new products when facing the increasingly competitive market, by which product value can be increased or production cost can be reduced to enhance the competitive advantages. Therefore, the decision about the use of capital expenditure obtains more attention. However such a decision may encounter various kinds of risks and the decision maker must evaluate and measure the feasibility whether bring corporation the positive effect. To the amorphous silicon thin film solar manufacturers, existing product has worse competitiveness in the market. It need do the structured analysis of decision candidates before taking the capital expenditure action to develop new technologies and products. By using the Bayesian decision analysis, executing the prior analysis and posterior analysis with product acceptance rate and product return rate two uncertain factors to come out the decision model and decision rules. And then apply the real data in this model to calculate and analysis to verify the feasibility of this model. The purpose of the research is to assist the amorphous silicon thin film solar manufacturers in making decision by providing a systematic analytic decision procedure to prevent the input of unnecessary resource and reduce the possibility of expectation gap.

UV light detection has a lot of applications including secured satellite communication, solar and celestial observation and biological imaging. Wide bandgap materials are used to sense UV light. SiC is an excellent material for UV detection, having properties like high hardness, chemical inertness, thermal stability, high breakdown voltage etc. making it a very reliable and stable material for use in harsh/unknown environments. Growing SiC is a difficult task as it shows 250 different crystal structures and needs very high temperature to form crystalline film. Most of the studies use SiH4 (toxic) and other gaseous precursors for growth of SiC. We are proposing formation of crystalline SiC thin film with DC magnetron sputtering using highly pure, naturally and commercially abundant Silicon, Argon and Methane at relatively lower temperature. The technique is well known in industry and is compatible with silicon technology. SiC thin films were grown on Si Substrate. For the study of formation of crystalline films, we varied the deposition parameters. Flow rate of methane inside the chamber and DC power supplied to the target were varied to observe the change in film’s bonding, structure and crystallinity. Deposited films were characterized using FTIR, Raman, X-Ray Diffraction, Optical profilometer and UV Visible spectroscopy. Films grown were found to be polycrystalline and the study gave the clear picture to get high quality reproducible cubic SiC thin films. Optimized films were used to make a heterostructure of Al/SiC/Si/Al configuration and a planar structure of Al/SiC/Al on quartz substrate to observe the response in UV region. Study proposes that the deposited film could be used for UV detection in various applications

Integration of germanium (Ge) on low cost substrates such as silicon and steel open several applications such as low cost III-V photovoltaics, beyond silicon CMOS and optoelectronics applications. However, growth of germanium on silicon and steel is non-trivial owing to lattice mismatch of 4% and 50 % respectively. So far successful growth of Ge on Si has been shown by using complex methods such as molecular beam epitaxy (MBE) and Ultra High Vacuum Chemical vapour deposition (UHV-CVD). Despite their advantages the methods are not suitable for scale-up owing to their high-cost and low throughput. Alternatives such as liquid phase epitaxy from metal catalyst are industry scalable but lead to defective Ge films due to metal incorporation. In this work, we have developed a novel process for growth of epitaxial germanium films on silicon using liquid phase crystallization. The films are grown by melting and re-crystallization from pure “liquid phase” of germanium instead of a metal solution, thus eliminating problem of metal contamination. The liquid phase crystallization method is relatively simple and low-cost, and the Ge films so obtained are comparable in quality to MBE and CVD methods. The LPC method is wafer-scale and suitable for batch processing, making it commercially viable. The LPC Ge films are characterized for material quality using SEM, XRD, Raman measurements and for device quality using lifetime and Hall measurements. The films are found to be epitaxial with excellent electronic properties. The LPC Ge was used to demonstrate two novel application: a) low cost III-V photovoltaics, and b) on-chip Ge devices on Si. One way to significantly reduce cost of GaAs photovoltaics is to grow high-quality GaAs on low-cost Si wafers. However, direct integration of GaAs on Si leads to highly defective films due to their lattice mismatch. Unlike Si, Ge is lattice matched to GaAs. So better quality GaAs-on-silicon films can be grown by integrating an epitaxial Ge buffer, grown using LPC, between GaAs and Si. The GaAs films were grown on the Ge on Si substrates using MOCVD, and characterized using SEM, XRD and Raman measurements. To examine the device quality, room and low temperature photoluminescence (PL) and time resolved PL measurements were done. Results show that the GaAs films grow epitaxially on Ge-on-Si with room for further optimization. Ge photo-detectors find use in next-generation silicon photonics and as IR sensors. LPC Ge is a candidate for on-chip Ge-based IR devices. As proof of concept, MSM were fabricated on LPC-grown Ge-on-Si films using aluminum metal as contacts. The detectors were found to be responsive in IR range from 1100 nm to 1700 nm with moderate responsivity. Even more challenging than Si, is integration of Ge on steel. Steel is robust and low-cost substrate and stable at high temperatures. These qualities make Ge-on-steel interesting for low-cost, large-area, and flexible solar cells. However direct growth of any semiconductor on steel leads to defective films, primarily due to diffusion of iron from steel into semiconductor; deteriorating the electronic properties of the semiconductor. Introducing a “diffusion barrier” between steel and the semiconductor layer may solve this problem. Titanium nitride (TiN) was found to be a good barrier-layer because it is stable at high temperatures, does not contaminate semiconducting over layers and has very low iron diffusivity. TiN on steel as iron diffusion barrier was characterized using Secondary Ion Mass Spectrometry (SIMS). It was found that the diffusion estimation is non-trivial due to contribution from both bulk and grain boundaries which was for the first time explained and observed carefully in this work. The study reveals the importance of effective diffusion estimation for designing barrier layer for devices on steel. Thereafter, germanium was, for the first time, successfully crystallized on TiN on steel using laser annealing of amorphous Ge films as a first step towards realization of cGe/TiN/Steel stack for III-V integration on steel. Laser based annealing was used owing to low thermal budget requirement for device on steel to reduce iron diffusion problems. This work provides a low cost and scalable solution to the problem of integrating Ge on Si and steel with initial proof of concept applications.

碩士
國立交通大學
光電工程學系
100
In the driver system of thin-film transistor liquid-crystal display (TFT-LCD), gate drivers (or scan drivers) are the essential parts that sequentially control the gates of pixel TFTs. Therefore, the pixel TFTs can transfer correct data and store in the liquid crystal and storage capacitors. Recently, in the consumer electronic display products, the gate driver circuits have been integrated into the bottom plate glass of LCD module rather than providing form the conventional ICs. Although the electron mobility in a-Si TFTs is extremely low (≈0.3cm2/V-s), the traits of high uniformity and low cost of manufacturing a-Si TFTs have created the trend towards gate driver on array (GOA). Moreover, the application of GOA decreases the cost of ICs and results in the module lighter and thinner. In this thesis, we have proposed two main kinds of GOA, Type A and Type C. The features of Type A are the low noise and stable waveforms, and the threshold voltage drop cancellation method. On the other hand, Type C circuit is designed for the low power application and applying on the narrow bezel panel. Furthermore, in order to apply on products flexibly, Type B and Type D circuits are revised for the bi-directional function from Type A and Type C circuits, respectively. Finally, all of these circuits must integrate into panels for real assessments. Therefore, these circuits should be adjusted for the real panel specification and commercial IC timings. In addition, the device characteristics have to be well surveyed form several experiments including the uniformity, stability, and reliability. By stress experiments for devices and circuits, the results show the gate driver circuits still work normally after long-term use.

碩士
國立交通大學
光電工程學系
101
In this article, we investigate the performance of hydrogenated amorphous silicon-based thin-film fabricated by high-density plasma chemical vapor deposition system. The solar spectra in near infrared regime (<750 nm) can not be effective absorbed due to the high optical band gap of a-Si:H thin film (1.8 ~1.9 eV). In order to utilize the solar spectra in near infrared regime effectively, we develop the hydrogenated amorphous silicon-germanium alloys (a-SiGe:H) films with low optical band gap (1.4 to 1.6 eV). The single junction a-SiGe:H thin film solar cells with the band gap of 1.45 eV can be obtained by the optimization of Ge doping and deposition parameter. We demonstrate single-junction a-SiGe solar cells with the conversion efficiency of 5.26% and the broadband quantum efficiency in the range of 300-850 nm. We introduce a-SiGe thin film as the absorber layer of bottom sub-cell in stacked solar cells. As achieving current matching between the top sub-cell and bottom sub-cell in the a-Si/a-SiGe double junction solar cells, conversion efficiency can be reached up to 8.38%. Moreover, highly light-soaking stable a-Si/a-Si/a-SiGe triple junction solar cells were demonstrated with photo-induced degradation in conversion-efficiency as low as 2.5%. We also show the solar cells fabricated by different gas source and different substrate. By using disilane-plasma technology, the conversion efficiency of single-junction a-Si and a-SiGe solar cells achieves 9.01% and 4.76%. For n-i-p structure a-Si solar cells integrated into the back reflective substrate show the conversion efficiency of 8.47% through the optimized thickness of doped layers. In the future, our research will focus on tuning the optical and electrical performance of a-SiGe:H thin film fabricated by using disilane-plasma technology to obtain the double-junction and triple-junction thin film solar cells with high conversion efficiency.

碩士
國立中央大學
機械工程研究所
95
The technique of single-crystal Si layer transfer based on using Hydrogen ion implantation has been widely applied in the fabrication of SOI materials possessing nano-scale device layer with single-crystal quality. However, after Si layer transfer process, a lattice-defect region was formed near the surface of transferred Si layer. Therefore, this unwanted region usually needs an extra chemical mechanical polishing (CMP) process to remove it. The main purpose of this study is to avoid the above polishing process as well as simplify the manufacturing processes. In this study, the removal of lattice-defect region generated after layer transfer by Smart-cut® method used etching approach with specific etchants to etch out it at specific temperature. This etching process could also result in surface smooth of the Si transferred layer. Besides, depositing a polysilicon layer as a sacrificial layer has successfully improved the occurrence of channel effect during ion implantation process and then reduced the difference of ion penetration depth to initially modify the surface roughness of the as-split SOI thin film. The surface roughness could be further decreased after using etching approach to remove the lattice-defect region. The above two steps can make the final surface of the transferred single-crystal Si layer smooth and uniform.

碩士
國立臺灣科技大學
自動化及控制研究所
97
The microcrystalline silicon thin film solar cell consists of several thin films, such as the microcrystalline silicon thin film, the aluminum-doped zinc oxide transparent conductive film, and aluminum back-contact thin films. The purpose of this research is to find the optimization parameters of making the several thin films isolated well by laser scribing. In this study, we used three laser systems, Ultraviolet Laser, Fibre Laser, and Femtosecond Laser, to examine the relation between factors of laser systems and the quality characteristics of laser isolation processing. By using Taguchi Method, we could obtain factors and quality characteristics from following the L18 orthogonal array to set up the experiment. We defined the quality characteristics of scribing structure, such as upper width of V-cut line, lower width of V-cut line, V-cut depth, and the burrs above processing surface of microcrystalline silicon thin film. Therefore, the optimal factors combination for isolation processing of the microcrystalline silicon thin film were conducted via Taguchi Method and analytic hierarchy process theory. The results of laser scribing microcrystalline solar cell materials are as follows: AZO(200nm) scribed a minimum line width of 16.07 micrometers, AZO(500nm) scribed a minimum line width of 17.66 micrometers, microcrystalline silicon(38% crystallinity) scribed the smallest line 24.29 micrometers wide, microcrystalline silicon(68% crystallinity) scribed a minimum line width of 29.91 micrometers, and aluminum back contact(300nm) scribed the smallest line 11.57 micrometers wide. In additions, we can predict the results of laser isolation processing through simulation experiments by using the back propagation neural computing forecasting system. Through experimenting and computing, the error between actual value and predicted value could be converged within 2%. Finally, the results of laser isolation processing experiment were confirmed.