Дисертації з теми "SiC power device"

Power devices play key roles in the power electronics applications. In order for the power electronics designers to fully utilize the performance advantages of power devices, compact power device models are needed in the circuit simulator (Saber, P-spice, etc.). Therefore, it is very important to get accurate device models. However, there are many challenges due to the development of new power devices with new internal structure and new semiconductor materials (SiC, GaN, etc.). In this dissertation, enhanced power diode model is presented with an improvement in the reverse blocking region. In the current power diode model in the Saber circuit simulator, an empirical approach was used to describe the low-bias reverse blocking region by introducing an effect called â conduction loss,â a parameter that causes a linear relationship between the device voltage and current at low bias voltages with no physics meaning. Furthermore, this term is not sufficient to accurately describe the changes to the device characteristics as the junction temperature is varied. In the enhanced model, an analytical temperature dependent model for the reverse blocking characteristics has been developed for Schottky/JBS diodes by including the thermionic-emission mechanism in the low-bias range. The newly derived model equations have been implemented in Saber circuit simulator using MAST language. An automated parameter extraction software package developed for constructing silicon (Si) and silicon carbide (SiC) power diode models, which is called DIode Model Parameter extrACtion Tools (DIMPACT). This software tool extracts the data necessary to establish a library of power diode component models and provides a method for quantitatively comparing between different types of devices and establishing performance metrics for device development. This dissertation also presents a new Saber-compatible approach for modeling the inter-electrode capacitances of the Si CoolMOSTM transistor. This new approach accurately describes all three inter-electrode capacitances (i.e., gate-drain, gate-source, and drain-source capacitances) for the full operating range of the device. The model is derived using the actual charge distribution within the device rather than assuming a lumped charge or one-dimensional charge distribution. The comparison between the simulated data with the measured results validates the accuracy of the new physical model.
Ph. D.

The trend of electrification in transportation applications has led to the fast development of high-power-density power electronics converters. High-switching-frequency and high-temperature operations are the two key factors towards this target. Both requirements, however, are challenging the fundamental limit of silicon (Si) based devices. The emerging wide-bandgap, silicon carbide (SiC) power devices have become the promising solution to meet these requirements. With these advanced devices, the technology barrier has now moved to the compatible integration technology that can make the best of device capabilities in high-power-density converters. Many challenges are present, and some of the most important issues are explored in this dissertation. First of all, the high-temperature performances of the commercial SiC MOSFET are evaluated extensively up to 200 degree C. The static and switching characterizations show that the device has superior electrical performances under elevated temperatures. Meanwhile, the gate oxide stability of the device - a known issue to SiC MOSFETs in general - is also evaluated through both high-temperature gate biasing and gate switching tests. Device degradations are observed from these tests, and a design trade-off between the performance and reliability of the SiC MOSFET is concluded. To understand the interactions between devices and circuit parasitics, an experimental parametric study is performed to investigate the influences of stray inductances on the MOSFETs switching waveforms. A small-signal model is then developed to explain the parasitic ringing in the frequency domain. From this angle, the ringing mechanism can be understood more easily and deeply. With the use of this model, the effects of DC decoupling capacitors in suppressing the ringing can be further explained in a more straightforward way than the traditional time-domain analysis. A rule of thumb regarding the capacitance selection is also derived. A Power Electronics Building Block (PEBB) module is then developed with discrete SiC MOSFETs. Integrating the power stage together with the peripheral functions such as gate drive and protection, the PEBB concept allows the converter to be built quickly and reliably by simply connecting several PEBB modules. The high-speed gate drive and power stage layout designs are presented to enable fast and safe switching of the SiC MOSFET. Based on the PEBB platform, the state-of-the-art Si and SiC power MOSFETs are also compared in the device characteristics, temperature influences, and loss distributions in a high-frequency converter, so that special design considerations can be concluded for the SiC MOSFET. Towards high-temperature, high-frequency and high-power operations, integrated wire-bond phase-leg modules are also developed with SiC MOSFET bare dice. High-temperature packaging materials are carefully selected based on an extensive literature survey. The design considerations of improved substrate layout, laminated bus bars, and embedded decoupling capacitors are all discussed in detail, and are verified through a modeling and simulation approach in the design stage. The 200 degree C, 100 kHz continuous operation is demonstrated on the fabricated module. Through the comparison with a commercial SiC phase-leg module designed in the traditional way, it is also shown that the design considerations proposed in this work allow the SiC devices in the wire-bond structure to be switched twice as fast with only one-third of the parasitic ringing. To further push the performance of SiC power modules, a novel hybrid packaging technology is developed which combines the small parasitics and footprint of a planar module with the easy fabrication of a wire-bond module. The original concept is demonstrated on a high-temperature rectifier module with SiC JFET. A modified structure is then proposed to further improve design flexibility and simplify module fabrication. The SiC MOSFET phase-leg module built in this structure successfully reaches the switching speed limit of the device almost without any parasitic ringing. Finally, a new switching loop snubber circuit is proposed to damp the parasitic ringing through magnetic coupling without affecting either conduction or switching losses of the device. The concept is analyzed theoretically and verified experimentally. The initial integration of such a circuit into the power module is presented, and possible improvements are proposed.
Ph. D.

Silicon Carbide (SiC) is a wide band-gap semiconductor material with excel-lent material properties for high frequency, high power and high temperature elec-tronics. In this work different SiC field-effect transistors have been studied using theoretical methods, with the focus on both the devices and the methods used. The rapid miniaturization of commercial devices demands better physical models than the drift-diffusion and hydrodynamic models most commonly used at present.

The Monte Carlo method is the most accurate physical methods available and has been used in this work to study the performance in short-channel SiC field-effect devices. The drawback of the Monte-Carlo method is the computational power required and it is thus not well suited for device design where the layout requires to be optimized for best device performance. One approach to reduce the simulation time in the Monte Carlo method is to use a time-domain drift-diffusion model in contact and bulk regions of the device. In this work, a time-domain drift-diffusion model is implemented and verified against commercial tools and would be suitable for inclusion in the Monte-Carlo device simulator framework.

Device optimization is traditionally performed by hand, changing device pa-rameters until sufficient performance is achieved. This is very time consuming work without any guarantee of achieving an optimal layout. In this work a tool is developed, which automatically changes device layout until optimal device per-formance is achieved. Device optimization requires hundreds of device simulations and thus it is essential that computationally efficient methods are used. One impor-tant physical process for RF power devices is self heating. Self heating can be fairly accurately modeled in two dimensions but this will greatly reduce the computa-tional speed. For realistic influence self heating must be studied in three dimensions and a method is developed using a combination of 2D electrical and 3D thermal simulations. The accuracy is much improved by using the proposed method in comparison to a 2D coupled electro/thermal simulation and at the same time offers greater efficiency. Linearity is another very important issue for RF power devices for telecommunication applications. A method to predict the linearity is imple-mented using nonlinear circuit simulation of the active device and neighboring passive elements.

Silicon carbide is a promising wide bandgap semiconductormaterial for high-temperature, high-power, and high-frequencydevice applications. However, there are still a number offactors that are limiting the device performance. Among them,one of the most important and critical factors is the formationof low resistivity Ohmic contacts and high-temperature stableSchottky diodes on silicon carbide.

In this thesis, different metals (TiW, Ti, TiC, Al, and Ni)and different deposition techniques (sputtering andevaporation) were suggested and investigated for this purpose.Both electrical and material characterizations were performedusing various techniques, such as I-V, C-V, RBS, XRD, XPS,LEED, SEM, AFM, and SIMS.

For the Schottky contacts to n- and p-type 4H-SiC, sputteredTiW Schottky contacts had excellent rectifying behavior afterannealing at 500 ºC in vacuum with a thermally stableideality factor of 1.06 and 1.08 for n- and p-type,respectively. It was also observed that the SBH for p-type SiC(Φ_Bp) strongly depends on the choice the metal with alinear relationship Φ_Bp= 4.51 - 0.58Φ_m, indicating no strong Fermi-level pinning.Finally, the behavior of Schottky diodes was investigated byincorporation of size-selected Au nano-particles in Ti Schottkycontacts on silicon carbide. The reduction of the SBH isexplained by using a simple dipole layer approach, withenhanced electric field at the interface due to the small sizeof the circular patch (Au nano-particles) and large differenceof the barrier height between two metals (Ti and Au) on both n-and p-SiC.

For the Ohmic contacts, titanium carbide (TiC) was used ascontacts to both n- and p-type 4H-SiC epilayers as well as onAl implanted layers. The TiC contacts were epitaxiallydeposited using a co-evaporation method with an e-beam Tisource and a Knudsen cell for C₆₀, in a UHV system at low substrate temperature(500 ºC). In addition, we extensively investigatedsputtered TiW (weight ratio 30:70) as well as evaporated NiOhmic contacts on both n- and p-type epilayers of SiC. The bestOhmic contacts to n-type SiC are annealed Ni (>950ºC)with the specific contact resistance of ≈ 8× 10^-6Ω cm²with doping concentration of 1.1 × 10^-19cm^-3while annealed TiW and TiC contacts are thepreferred contacts to p-type SiC. From long-term reliabilitytests at high temperature (500 ºC or 600 ºC) invacuum and oxidizing (20% O₂/N₂) ambient, TiW contacts with a platinum cappinglayer (Pt/Ti/TiW) had stable specific contact resistances for>300 hours.

Keywords: silicon carbide, Ohmic and Schottky contacts,co-evaporation, current-voltage, capacitance-voltagemeasurement, power devices, nano-particles, Schottky barrierheight lowering, and TLM structures.

This thesis examines the packaging of high-temperature SiC power electronic devices. Current-voltage measurements were conducted on as-received and packaged SiC power devices. The planar structure was introduced and developed as a substitution for traditional wire-bonding vertical structure. The planar structure was applied to a high temperature (>250oC) SiC power device. Based on the current-voltage (I-V) measurements, the packaging structures were improved, materials were selected, and processes were tightly controlled. This study applies two types of planar structures, the direct bond and the bump bond, to the high-temperature packaging of high-temperature SiC diode. A drop in the reverse breakdown voltage was discovered in the packaging using a direct bond. The root cause for the drop in the breakdown voltage was identified and corrective solutions were evaluated. A few effective methods were suggested for solving the breakdown issue. The forward I-V curve of the planar packaging using direct bond showed excellent results due to the excellent electrical and thermal properties of sintered nanosilver. The packaging using a bump bond as an improved structure was processed and proved to possess desirable forward and reverse I-V behavior. The cross-sections of both planar structures were inspected. High-temperature packaging materials, including nano-silver paste, high-lead solder ball and paste, adhesive epoxy, and encapsulant, were introduced and evaluated. The processes such as stencil printing, low-temperature sintering, solder reflowing, epoxy curing, sputtering deposition, electroplating, and patterning of direct-bond copper (DBC) were tightly controlled to ensure high-quality packaging with improved performance. Finally, the planar packaging of the high temperature power device was evaluated and summarized, and the future work was recommended.
Master of Science

This paper describes the design, fabrication, and testing of a 1.2 kV, 6.5 mΩ, half-bridge, SiC MOSFET power module to evaluate the impact of parametric device tolerances on electrical and thermal performance. Paralleling power devices increases current handling capability for the same bus voltage. However, inherent parametric differences among dies leads to unbalanced current sharing causing overstress and overheating. In this design, a symmetrical DBC layout is utilized to balance parasitic inductances in the current pathways of paralleled dies to isolate the impact of parametric tolerances. In addition, the paper investigates the benefits of flexible PCB in place of wire bonds for the gate loop interconnection to reduce and minimize the gate loop inductance. The balanced modules have dies with similar threshold voltages while the unbalanced modules have dies with unbalanced threshold voltages to force unbalanced current sharing. The modules were placed into a clamped inductive DPT and a continuous, boost converter. Rogowski coils looped under the wire bonds of the bottom switch dies to observe current behavior. Four modules performed continuously for least 10 minutes at 200 V, 37.6 A input, at 30 kHz with 50% duty cycle. The modules could not perform for multiple minutes at 250 V with 47.7 A (23 A/die). The energy loss differential for a ~17% difference in threshold voltage ranged from 4.52% (~10 µJ) to -30.9% (~30 µJ). The energy loss differential for a ~0.5% difference in V_th ranged from -2.26% (~8 µJ) to 5.66% (~10 µJ). The loss differential was dependent on whether current unbalance due to on-state resistance compensated current unbalance due to threshold voltage. While device parametric tolerances are inherent, if the higher threshold voltage devices can be paired with devices that have higher on-state resistance, the overall loss differential may perform similarly to well-matched dies. Lastly, the most consistently performing unbalanced module with 17.7% difference in V_th had 119.9 µJ more energy loss and was 22.2°C hotter during continuous testing than the most consistently performing balanced module with 0.6% difference inV_th.
Master of Science
This paper describes the design, construction, and testing of advanced power devices for use in electric vehicles. Power devices are necessary to supply electricity to different parts of the vehicle; for example, energy is stored in a battery as direct current (DC) power, but the motor requires alternating current (AC) power. Therefore, power electronics can alter the energy to be delivered as DC or AC. In order to carry more power, multiple devices can be used together just as 10 people can carry more weight than 1 person. However, because the devices are not perfect, there can be slight differences in the performance of one device to another. One device may have to carry more current than another device which could cause failure earlier than intended. In this research project, multiple power devices were placed into a package, or "module." In a control module, the devices were selected with similar properties to one another. In an experimental module, the devices were selected with properties very different from one another. It was determined that the when the devices were 17.7% difference, there was 119.9 µJ more energy loss and it was 22.2°C hotter than when the difference was only 0.6%. However, the severity of the difference was dependent on how multiple device characteristics interacted with one another. It may be possible to compensate some of the impact of device differences in one characteristic with opposing differences in another device characteristic.

This work investigates three-dimensional power loop layout for application to a SiC based matrix converter, providing a symmetric, low-inductance solution. The thesis presents various layout types to achieve this design target, and details the implementation of a hybrid layout to the matrix converter phase-leg. This layout is more easily achievable with a surface-mount device package, which also offers benefits such as ease in manufacturing, and a compact package. In order to implement a surface-mount device, a PCB thermal management strategy should be utilized. An evaluation of these methods is also presented in the work. The final power loop solution that implements an aluminum nitride inlay is evaluated through simulated parasitic extraction and experimental double pulse tests. The layout achieves small, symmetric loop inductances. Finally, the full power, three-phase matrix converter demonstrates the successful implementation of this power loop layout.
Master of Science
In the United States, 40% primary energy consumption comes from electricity generation, which is the fastest growing form of end-use energy. Industries such as commercial airlines are increasing their use of electric energy, while phasing out the mechanical and pneumatic aircraft components, as they offer better performance and lower cost. Thus, implementation of high efficiency, electrical system can reduce energy consumption, fuel consumption and carbon emissions [1]. As more systems rely on this electric power, the conversion from one level of power (voltage and current) to another, is critical. In the quest to develop high efficiency power converters, wide bandgap semiconductor devices are being turned to. These devices, specifically Silicon Carbide (SiC) devices, offer high temperature and high voltage operation that a traditional Silicon (Si) device cannot. Coupled with fast switching transients, these metal oxide semiconductors field effect transistors (MOSFETs), could provide higher levels of efficiency and power density. This work investigates the benefits of a three-dimensional (3D) printed circuit board (PCB) layout. With this type of layout, a critical parasitic – inductance – can be minimized. As the SiC device can operate at high switching speeds, they incur higher di/dt, and dv/dt slew rates. If trace inductance is not minimal, overshoots and ringing will occur. This can be addressed by stacking PCB traces on top of one another, the induced magnetic field can be reduced. In turn, the system inductance is lowered as well. The reduction of this parameter in the system, reduces the overshoot and ringing. This particular work applies this technique to a 15kW matrix converter. This converter poses a particular design challenge as there are a large number of devices, which can lead to longer, higher inductance PCB traces. The goal of this work is to minimize the parasitic inductance in this converter for high efficiency, high power density operation.

L’émergence d’interrupteurs de puissance en SiC permet d’envisager des convertisseurs de puissance capables de fonctionner au sein des environnements sévères tels que la haute tension (> 10 kV ) et la haute température (> 300 °C). Aucune solution de commande spécifique à ces environnements n’existe pour le moment. Le développement de fonctions élémentaires en SiC (comparateur, oscillateur) est une étape préliminaire à la réalisation d’un premier démonstrateur. Plusieurs laboratoires ont développé des fonctions basées sur des transistors bipolaires, MOSFETs ou JFETs. Cependant les recherches ont principalement portées sur la conception de fonctions logiques et non sur l’intégration de drivers de puissance. Le laboratoire AMPERE (INSA de Lyon) et le Centre National de Microélectronique de Barcelone (Espagne) ont conçu un MESFET latéral double grille en SiC. Ce composant élémentaire sera à la base des différentes fonctions intégrées envisagées. L’objectif de ces recherches est la réalisation d’un convertisseur élévateur de tension "boost" monolithique et de sa commande en SiC. La démarche scientifique a consisté à définir dans un premier temps un modèle de simulation SPICE du MESFET SiC à partir de caractérisations électriques statique et dynamique. En se basant sur ce modèle, des circuits analogiques tels que des amplificateurs, oscillateurs, paires différentielles, trigger de Schmitt ont été conçus pour élaborer le circuit de commande (driver). La conception de ces fonctions s’avère complexe puisqu’il n’existe pas de MESFETs de type P et une polarisation négative de -15 V est nécessaire au blocage des MESFETs SiC. Une structure constituée d’un pont redresseur, d’un boost régulé avec sa commande basée sur ces différentes fonctions a été réalisée et simulée sous SPICE. L’ensemble de cette structure a été fabriqué au CNM de Barcelone sur un même substrat SiC semi-isolant. L’intégration des éléments passifs n’a pas été envisagée de façon monolithique (mais pourrait être considérée pour les inductances et capacités dans la mesure où les valeurs des composants intégrés sont compatibles avec les processus de réalisation). Le convertisseur a été dimensionné pour délivrer une de puissance de 2.2 W pour une surface de 0.27 cm2, soit 8.14 W/cm2. Les caractérisations électriques des différents composants latéraux (résistances, diodes, transistors) valident la conception, le dimensionnement et le procédé de fabrication de ces structures élémentaires, mais aussi de la majorité des fonctions analogiques. Les résultats obtenus permettent d’envisager la réalisation d’un driver monolithique de composants Grand Gap. La perspective des travaux porte désormais sur la réalisation complète du démonstrateur et sur l’étude de son comportement en environnement sévère notamment en haute température (> 300 °C). Des analyses des mécanismes de dégradation et de fiabilité des convertisseurs intégrés devront alors être envisagées
The new SiC power switches is able to consider power converters, which could operate in harsh environments as in High Voltage (> 10kV) and High Temperature (> 300 °C). Currently, they are no specific solutions for controlling these devices in harsh environments. The development of elementary functions in SiC is a preliminary step toward the realization of a first demonstrator for these fields of applications. AMPERE laboratory (France) and the National Center of Microelectronic of Barcelona (Spain) have elaborated an elementary electrical compound, which is a lateral dual gate MESFET in Silicon Carbide (SiC). The purpose of this research is to conceive a monolithic power converter and its driver in SiC. The scientific approach has consisted of defining in a first time a SPICE model of the elementary MESFET from electric characterizations (fitting). Analog functions as : comparator, ring oscillator, Schmitt’s trigger . . . have been designed thanks to this SPICE’s model. A device based on a bridge rectifier, a regulated "boost" and its driver has been established and simulated with the SPICE Simulator. The converter has been sized for supplying 2.2 W for an area of 0.27 cm2. This device has been fabricated at CNM of Barcelona on semi-insulating SiC substrate. The electrical characterizations of the lateral compounds (resistors, diodes, MESFETs) checked the design, the "sizing" and the manufacturing process of these elementary devices and analog functions. The experimental results is able to considerer a monolithic driver in Wide Band Gap. The prospects of this research is now to realize a fully integrated power converter in SiC and study its behavior in harsh environments (especially in high temperature > 300 °C). Analysis of degradation mechanisms and reliability of the power converters would be so considerer in the future

Silicon carbide (SiC), with its wide bandgap, high thermal conductivity and natural oxide is a substrate that has given rise to a new generation of power devices than can operate at high temperature, high power and high frequency, though the material is not without its problems. SiC "heterojunction devices" are layers of germanium (Ge) or silicon (Si) that are deposited via molecular beam epitaxy (MBE) or wafer bonded onto the SiC surface. These narrow bandgap thin films can provide a high mobility channel region overcoming SiC's crippling channel mobility, which is most often made worse by a high density of interface states. Concentrating predominantly on Ge/SiC heterojunctions, this thesis characterises the physical and electrical nature of these structures, investigating the rectifying properties of the heterojunction interface and the ability of these layers to support a depletion region. A physical analysis of the layers revealed that the Ge formed in an unexpectedly uniform fashion, given the large lattice mismatch involved. At a deposition temperature of 500oC the Ge initially clumped into wide, shallow islands before merging, forming at best a 300 nm polycrystalline layer with a surface roughness of only 6 nm. This was in contrast to MBE deposited Si/SiC layers that formed tall islands that at 1 μm thick, still had not merged. After being formed into Ge/SiC heterojunction diodes they were electrically characterised. The layers displayed near ideal (η = 1:05) turn-on characteristics, low turn-on voltage (approximately 0.3 V less than Ni/SiC SBDs), reasonable on-resistance (12 m­Ωcm2) and minimal leakage current. The devices were shown to suffer severe Fermi level pinning that defined the way the materials' bands aligned. This occurred as a result of an inhomogeneous interface that also caused fluctuations in the size of the Schottky barrier height across the interface. New characterisation techniques relating to these phenomena were applied to a heterojunction for the first time. MBE formed Ge/SiC layers and wafer bonded Si/SiC layers were formed into MOS capacitors through the deposition of the high-K dielectric hafnium oxide (HfO2). The increased conduction band offset between oxide and narrow bandgap semiconductor suppressed leakage problems often seen in HfO2/SiC structures. Capacitance-voltage results showed that they could both support a depletion region, though the best results came from the MBE Ge/SiC diodes. Current-voltage results showed that the more uniform Si/SiC devices could block 3.5 MV/cm.

Silicon Carbide (SiC) is a wide-bandgap (WBG) semiconductor materialwhich has several advantages such as higher maximum electric field, lowerON-state resistance, higher switching speeds, and higher maximum allowablejunction operation temperature compared to Silicon (Si). In the 1.2 kV - 1.7kV voltage range, power devices in SiC are foreseen to replace Si Insulatedgatebipolar transistors (IGBTs) for applications targeting high efficiency,high operation temperatures and/or volume reductions. In particular, theSiC Metal-oxide semiconductor field-effect transistor (MOSFET) – which isvoltage controlled and normally-OFF – is the device of choice due to the easeof its implementation in designs using Si IGBTs.In this work the reliability of SiC devices, in particular that of the SiCMOSFET, has been investigated. First, the possibility of paralleling two discreteSiC MOSFETs is investigated and validated through static and dynamictests. Parallel-connection was found to be unproblematic. Secondly, drifts ofthe threshold voltage and forward voltage of the body diode of the SiC MOSFETare investigated through long-term tests. Also these reliability aspectswere found to be unproblematic. Thirdly, the impact of the package on thechip reliability is discussed through a modeling of the parasitic inductancesof a standard module and the impact of those inductances on the gate oxide.The model shows imbalances in stray inductances and parasitic elementsthat are problematic for high-speed switching. A long-term test on the impactof humidity on junction terminations of SiC MOSFETs dies and SiCSchottky dies encapsulated in the same standard package reveals early degradationfor some modules situated outdoors. Then, the short-circuit behaviorof three different types (bipolar junction transistor, junction field-effect transistor,and MOSFET) of 1.2 kV SiC switching devices is investigated throughexperiments and simulations. The necessity to turn OFF the device quicklyduring a fault is supported with a detailed electro-thermal analysis for eachdevice. Design guidelines towards a rugged and fast short-circuit protectionare derived. For each device, a short-circuit protection driver was designed,built and validated experimentally. The possibility of designing diode-lessconverters with SiC MOSFETs is investigated with focus on surge currenttests through the body diode. The discovered fault mechanism is the triggeringof the npn parasitic bipolar transistor. Finally, a life-cycle cost analysis(LCCA) has been performed revealing that the introduction of SiC MOSFETsin already existing IGBT designs is economically interesting. In fact,the initial investment is saved later on due to a higher efficiency. Moreover,the reliability is improved, which is beneficial from a risk-management pointof-view. The total investment over 20 years is approximately 30 % lower fora converter with SiC MOSFETs although the initial converter cost is 30 %higher.
Kiselkarbid (SiC) är ett bredbandgapsmaterial (WBG) som har flera fördelar,såsom högre maximal elektrisk fältstyrka, lägre ON-state resitans, högreswitch-hastighet och högre maximalt tillåten arbetstemperatur jämförtmed kisel (Si). I spänningsområdet 1,2-1,7 kV förutses att effekthalvledarkomponenteri SiC kommer att ersätta Si Insulated-gate bipolar transistorer(IGBT:er) i tillämpningar där hög verkningsgrad, hög arbetstemperatur ellervolymreduktioner eftersträvas. Förstahandsvalet är en SiC Metal-oxidesemiconductor field-effect transistor (MOSFET) som är spänningsstyrd ochnormally-OFF, egenskaper som möjliggör enkel implementering i konstruktionersom använder Si IGBTer.I detta arbete undersöks tillförlitligheten av SiC komponenter, specielltSiC MOSFET:en. Först undersöks möjligheten att parallellkoppla tvådiskretaSiC MOSFET:ar genom statiska och dynamiska prov. Parallellkopplingbefanns vara oproblematisk. Sedan undersöks drift av tröskelspänning ochbody-diodens framspänning genom långtidsprov. Ocksådessa tillförlitlighetsaspekterbefanns vara oproblematiska. Därefter undersöks kapslingens inverkanpåchip:et genom modellering av parasitiska induktanser hos en standardmoduloch inverkan av dessa induktanser pågate-oxiden. Modellen påvisaren obalans mellan de parasitiska induktanserna, något som kan varaproblematiskt för snabb switchning. Ett långtidstest av inverkan från fuktpåkant-termineringar för SiC-MOSFET:ar och SiC-Schottky-dioder i sammastandardmodul avslöjar tidiga tecken pådegradering för vissa moduler somvarit utomhus. Därefter undersöks kortslutningsbeteende för tre typer (bipolärtransistor,junction-field-effect transistor och MOSFET) av 1.2 kV effekthalvledarswitchargenom experiment och simuleringar. Behovet att stänga avkomponenten snabbt stöds av detaljerade elektrotermiska simuleringar för allatre komponenter. Konstruktionsriktlinjer för ett robust och snabbt kortslutningsskyddtas fram. För var och en av komponenterna byggs en drivkrets medkortslutningsskydd som valideras experimentellt. Möjligheten att konstrueradiodlösa omvandlare med SiC MOSFET:ar undersöks med fokus påstötströmmargenom body-dioden. Den upptäckta felmekanismen är ett oönskat tillslagav den parasitiska npn-transistorn. Slutligen utförs en livscykelanalys(LCCA) som avslöjar att introduktionen av SiC MOSFET:ar i existerandeIGBT-konstruktioner är ekonomiskt intressant. Den initiala investeringensparas in senare pågrund av en högre verkningsgrad. Dessutom förbättrastillförlitligheten, vilket är fördelaktigt ur ett riskhanteringsperspektiv. Dentotala investeringen över 20 år är ungefär 30 % lägre för en omvandlare medSiC MOSFET:ar även om initialkostnaden är 30 % högre.

QC 20170524

Mes travaux de thèse dans les laboratoires SATIE de ENS de Cachan et Ampère de l’INSA de Lyon se sont déroulés dans le cadre du projet Gestion OptiMisée de l'Energie (GENOME) pour étudier le potentiel de certains composants de puissance (JFET, MOSFET et BJT) en carbure de silicium (SiC) dans des convertisseurs électroniques de puissance dédiés à des applications aéronautiques suite au développement de l'avion plus électrique. La première partie de mes travaux étudie la robustesse de MOSFET et BJT en SiC soumis à des régimes de court circuit. Pour les MSOFET SiC, en soumettant ces transistors à la répétition de plusieurs courts-circuits, nous observons une évolution du courant de fuite de grille qui semble être un bon indicateur de vieillissement. Nous définissons une énergie critique répétitive pour évaluer la robustesse à la répétition de plusieurs courts-circuits. Aucun effet significatif de la température ambiante n’a pu être mis en évidence sur la robustesse des MOSFET et BJT SiC sous contraintes de court-circuit. Pour les MOSFET, nous avons également constaté une élévation significative du courant de fuite de grille en augmentant de 600V à 750V la tension, ce qui se traduit également par une défaillance plus rapide. Après ouverture des boîtiers des MOSFET Rohm ayant présenté un court-circuit entre grille et source après défaillance, on remarque une fusion de la métallisation de source qui vient effectivement court-circuiter grille et source. Dans ce mode de défaillance particulier, le court-circuit entre grille et source auto-protège la puce en lui permettant de s’ouvrir.La deuxième partie de ce mémoire est consacrée à l’étude de JFET, MSOFET et BJT SiC en régime d’avalanche. Les JFET de SemiSouth et les BJT de Fairchild présentent une bonne robustesse à l’avalanche. Mais le test d'avalanche révèle la fragilité du MOSFET Rohm puisqu’il entre en défaillance avant d’entrer en régime d’avalanche. La défaillance du MOSFET Rohm et sa faible robustesse en régime d’avalanche sont liées à l’activation du transistor bipolaire parasite. Le courant d'avalanche n’est qu’une très faible partie du courant dans l’inductance et circule du drain/collecteur à la grille/base pour maintenir le transistor en régime linéaire. Une résistance de grille de forte valeur diminue efficacement le courant d'avalanche à travers la jonction drain-grille pour le JFET.La troisième partie concerne l’étude de la commutation de BJT SiC à très haute fréquence de découpage. Nous avons dans un premier temps cherché à valider des mesures de pertes par commutation. Après avoir vérifié l'exactitude de la méthode électrique par rapport à une méthode calorimétrique simplifiée, nous montrons que la méthode électrique est adaptée à l’estimation des pertes de commutation mais nécessite beaucoup d’attention. En raison de mobilité élevée des porteurs de charge dans le SiC, nous montrons que le BJT SiC ne nécessite pas l’utilisation de diode d’anti-saturation. Enfin, aucune variation significative des pertes de commutation n’a pu être constatée sur une plage de température ambiante variant de 25°C à 200°C.La quatrième partie concentre l’étude du comportement de MOSFET SiC sous contraintes HTRB (High Temperature Reverse Bias) et dans une application diode-less dans laquelle les transistors conduisent un courant inverse à travers le canal, exception faite de la phase de temps mort pendant laquelle c’est la diode de structure qui assurera la continuité du courant dans la charge. Les résultats montrent que la diode interne ne présente aucune dégradation significative lors de la conduction inverse des MOSFET. Le MOSFET Cree testé montre une dérive de la tension de seuil et une dégradation de l’oxyde de grille qui sont plus significatives lors des essais dans l’application diode-less que sous des tests HTRB. La dérive de la tension de seuil est probablement due au champ électrique intense régnant dans l’oxyde et aux pièges de charge dans l'oxyde de grille
My PhD work in laboratories SATIE of ENS de Cachan and Ampère of INSA de Lyon is a part of project GEstioN OptiMisée de l’Energie (GENOME) to investigate the potential of some Silicon carbide (SiC) power devices (JFET, MOSFET and BJT) in power electronic converters dedicated to aeronautical applications for the development of more electric aircraft.The first part of my work investigates the robustness of MOSFET and SiC BJT subjected to short circuit. For SiC MOSFETs, under repetition of short-term short circuit, a gate leakage current seems to be an indicator of aging. We define repetitive critical energy to evaluate the robustness for repetition of short circuit. The effect of room temperature on the robustness of SiC MOSFET and BJT under short circuit stress is not evident. The capability of short circuit is not improved by reducing gate leakage current for MOSFET, while BJT shows a better robustness by limiting base current. For MSOFET, a significant increase in gate leakage current accelerates failure for DC voltage from 600V to 750V. After opening Rohm MOSFETs with a short circuit between gate and source after failure, the fusion of metallization is considered as the raison of failure. In this particular mode of failure, the short circuit between gate and source self-protects the chip and opens drain short current.The second part of the thesis is devoted to the study of SiC JFET, MSOFET and BJT in avalanche mode. The SemiSouth JFET and Fairchild BJT exhibit excellent robustness in the avalanche. On the contrary, the avalanche test reveals the fragility of Rohm MOSFET since it failed before entering avalanche mode. The failure of Rohm MOSFET and its low robustness in avalanche mode are related to the activation of parasitic bipolar transistor. The avalanche current is a very small part of the current in the inductor. It flows from the drain/collector to the gate/base to drive the transistor in linear mode. A high-value gate resistance effectively reduces the avalanche current through the drain-gate junction to the JFET.The third part of this thesis concerns the study of switching performance of SiC BJT at high switching frequency. We initially attempted to validate the switching loss measurements. After checking the accuracy of the electrical measurement compared to calorimetric measurement, electrical measurement is adopted for switching power losses but requires a lot of attention. Thanks to high carrier charge mobility of SiC material, SiC BJT does not require the use of anti-saturation diode. Finally, no significant variation in switching losses is observed over an ambient temperature range from 25°C to 200°C.The fourth part focuses on the study of SiC MOSFET behavior under HTB (High Temperature Reverse Bias) and in diode-less application in which the transistors conduct a reverse current through the channel, except for the dead time during which the body diode ensure the continuity of the current in the load. The results show that the body diode has no significant degradation when the reverse conduction of the MOSFET. Cree MOSFET under test shows a drift of the threshold voltage and a degradation of the gate oxide which are more significant during the tests in the diode-less application than under HTRB test. The drift of the threshold voltage is probably due to intense electric field in the oxide and the charge traps in the gate oxide

Silicon Carbide (SiC) is a semiconductor with a set of superior properties, including wide bandgap, high thermal conductivity, high critical electric field and high electron mobility. This makes it an excellent material for unipolar and bipolar electronic device applications that can operate under high temperature and high power conditions. Despite major advancements in SiC bulk growth technology, during last decade, the crystalline quality of bulk grown material is still not good enough to be used as the active device structure. Also, doping of the material through high temperature diffusion is not possible while ion implantation leads to severe damage to the crystalline quality of the material. Therefore, to exploit the superior quality of the material, epitaxial growth is a preferred technology for the active layers in SiC-based devices. Horizontal Hot-wall chemical vapor deposition is probably the best way to produce high quality epitaxial layers where complete device structure with different doping type or concentrations can be grown during a single growth run. SiC exists in many different polytypes and to maintain the polytype stability during epitaxial growth, off-cut substrates are required to utilize step-flow growth. The major disadvantage of growth on off-cut substrates is the replication of basal plane dislocations from the substrate into the epilayer. These are known to be the main source of degradation of bipolar devices during forward current injection. The bipolar degradation is caused by expanding stacking faults which increases the resistance and leads to fatal damage to the device. Structural defects replicated from the substrate are also important for the formation of defects in the epitaxial layer. In this thesis we have developed an epitaxial growth process to reduce the basal plane dislocations and the bipolar degradation. We have further studied the properties of the epitaxial layer with a focus on morphological defects and structural defects in the epitaxial layer. The approach to avoid basal plane dislocation penetration from the substrate is to grow on nominally on-axis substrate. The main obstacle with on-axis growth is to avoid the formation of parasitic 3C polytype inclusions. The first results (Paper 1) on epitaxial growth on nominally on-axis Si-face substrates showed that the 3C inclusions nucleated at the beginning of the growth and expand laterally without following any particular crystallographic direction. Also, the extended defects in the substrate like micropipes, clusters of threading screw and edge dislocations do not give rise to 3C inclusion. The substrate surface damage was instead found to be the main source. To improve the starting surface different in-situ etching conditions were studied (Paper 2) and Si-rich conditions were found to effectively remove the substrate surface damages with lowest roughness and more importantly uniform distribution of steps on the surface. Therefore, in-situ etching under Si-rich conditions was performed before epitaxial growth. Using this 100 % 4H polytype was obtained in the epilayer on full 2” wafer (Paper 3) using an improved set of growth parameters with Si-rich conditions at the beginning of the growth. Simple PiN diodes were processed on the on-axis material, and tested for bipolar degradation. More than 70 % of these (Paper 4) showed a stable forward voltage drop during constant high current injection. High voltage power devices require thick epitaxial layers with low doping. In addition, the high current needs large area devices with a reduced number of defects. Growth and properties of thick epilayers have been studied in details (Paper 5) and the process parameters in Horizontal Hotwall chemical vapor deposition reactor are found to be stable during the growth of over 100 µm thick epilayers. An extensive study of epitaxial defect known as the carrot defect has been conducted to investigate the structure of the defect and its probable relation to the extended defects in the substrate (Paper 6). Other epitaxial defects observed and studied were different in-grown stacking faults which frequently occur in as-grown epilayers (Paper 7) and also play an important role in the device performance. Minority carrier lifetime is an important property especially for high power bipolar devices. The influence of structural defects on minority carrier lifetime has been studied (Paper 8) in several epilayers, using a unique high resolution photoluminescence decay mapping. The technique has shown the influence on carrier lifetime from different structural defects, and also revealed the presence of non-visible structural defects such as dislocations and stacking faults, normally not observed with standard techniques.
Kiselkarbid (SiC) är en halvledare med överlägsna materialegenskaper, stort bandgap, hög termisk konduktivitet, hög kritisk fältstyrka och hög elektron mobilitet. Dessa gör den till ett utmärkt material för unipolära och bipolära komponenter som kan användas vid höga temperaturer, höga spänningar och höga strömmar. Trots stora framsteg under de senaste åren inom SiC bulk tillväxt, är material kvalitén hos bulk material fortfarande inte tillräckligt bra för att användas för aktiva skikt i komponenterna. Dessutom är dopning av materialet genom diffusion vid höga temperaturer inte möjligt, medan dopning via jonimplantation ger upphov till stora skador i kristallstrukturen. Därför behövs epitaxiell tillväxt av de aktive skikten i SiC baserade komponenter, för att fullt kunna utnyttja materialets egenskaper. Horisontell CVD (Hot-Wall Chemical Vapor Deposition) är en av de bästa tekniker att producera epitaxiella skikt med hög kvalité, där kompletta komponent strukturer med olika dopnings typ och koncentrationer kan växas i samma körning. SiC existerar i många polytyper och för att bibehålla polytype stabiliteten under tillväxt, används substrat med lutande kristallplan för använda s.k. step-flow tillväxt. En stor nackdel med substrat med lutande kristallplan är dock att dislokationer i basalplanet kommer att propagera från substratet in i det epitaxiella skiktet under tillväxten. Dessa dislokationer är den huvudsakliga orsaken till den degradering av bipolära komponenter som uppstår då höga strömmar går igenom komponenten. Den bipolära degraderingen orsakas av expanderade staplingsfel, som successivt ökar resistansen och slutligen förstörs komponenten. Strukturella defekter som replikeras från substratet är ofta även orsaken till kritiska defekter som skapas i det epitaxiella skiktet under tillväxt. I den här avhandlingen har vi utvecklat en epitaxiell som minskar problemet med basalplans dislokationer och bipolär degradering. Vi har även studerat egenskaper hos de epitaxiella skikten med fokus på morfologiska och strukturella defekter. Tekniken att hindra dislokationerna att replikeras in i de epitaxiella skikten bygger på att använda substrat utan lutning hos kristallplanen, s.k. on-axis substrat. Det hittills stora problemet med att växa på on-axis substrat har varit svårigheterna att bibehålla polytyp stabiliteten och undvika framförallt 3C polytyp inklusioner. Första försöken (Papper 1) försöken att växa epitaxi på on-axis substrat på Si sidan visade att 3C inklusionerna alltid startade i början av tillväxten för att sedan sprida sig lateralt under den fortsatta tillväxten. Vi kunde också visa att strukturella defekter som mikropipor, eller kluster av skruv- eller kant- dislokationer inte orsakade 3C inklusionerna. Den dominerande orsaken till 3C inklusionerna var istället skador eller repor på substratets yta. För att förbättra ytan innan den epitaxiella tillväxten studerade vi olika in-situ etsningar av ytan (Papper 2), och vi fann att etsning under Si dominerande förhållanden effektivast tog bort de flesta skador på substratets yta och gav en yta med minst ojämnheter. Dessutom skapades en homogen fördelning av atomära steg på ytan, och denna förbehandling användes sedan inför den epitaxiella tillväxten. Genom att dessutom optimera tillväxt förhållandena i inledningen av tillväxten kunde vi till 100% bibehålla samma polytyp från substratet in i det epitaxiella skiktet för hela 2” substrat (Papper 3). Enkla bipolära PiN dioder tillverkades och testades med avseende på bipolär degradering och mer än 70% av dioderna (Papper 4) visade ett stabilt framspänningsfall vid höga strömtätheter. Kraftkomponenter för höga spänningar kräver tjocka epitaxiella skikt med låg dopning. Dessutom, för höga strömmar krävs komponenter med stor aktiv area där kravet på lägre defekt täthet blir allt viktigare. Vi har i detalj studerat tillväxt och egenskaper av tjocka skikt (Papper 5), och funnit att de flesta material egenskaperna är stabila vid tillväxt av över 100 mm tjocka skikt i vår horisontella CVD reaktor. Vi har även i detalj studerat uppkomst och egenskaper av en av de mest kritiska epitaxiella defekterna, dem s.k. moroten (Papper 6). Speciellt har vi studerat dess uppkomst i relation till strukturella defekter i substratet. Vi har även studerat ända epitaxiella defekter i form av olika typer av staplingsfel (Papper 7), som även dessa har stor inverkan på komponenter. Livstiden för minoritetsladdningsbärarna är en viktig egenskap hos speciellt bipolära komponenter. I (Papper 8) har vi studerat hur denna påverkas av strukturella defekter i de epitaxiella skikten. Vi har använt en unik mätmetod för att optiskt kunna mäta över hela skivor, med hög upplösning. Mätningarna har lyckats påvisa hur olika strukturella defekter påverkar livstiden, och även kunnat visa på förekomsten av defekter som inte har upptäckts med andra mätmetoder.

This thesis provides insight into state-of-the-art 1.2 kV silicon carbide (SiC) power semiconductor transistors, including the MOSFET, BJT, SJT, and normally-on and normally-off JFETs. Both commercial and sample devices from the semiconductor industry's well-known manufacturers were evaluated in this study. These manufacturers include: Cree Inc., ROHM Semiconductor, General Electric, Fairchild Semiconductor, GeneSiC Semiconductor, Infineon Technologies, and SemiSouth Laboratories. To carry out this work, static characterization of each device was performed from 25 ºC to 200 ºC. Dynamic characterization was also conducted through double-pulse tests. Accordingly, this thesis describes the experimental setup used and the different measurements conducted, which comprise: threshold voltage, transconductance, current gain, specific on-resistance, parasitic capacitances, internal gate resistance, and the turn on and turn off switching times and energies. For the latter, the driving method used for each device is described in detail. Furthermore, for the devices that require on-state dc currents, driving losses are taken into consideration. While all of the SiC transistors characterized in this thesis demonstrated low specific on-resistances, the SiC BJT showed the lowest, with Fairchild's FSICBH057A120 SiC BJT having 3.6 mΩ•cm2 (using die area) at 25 ºC. However, the on-resistance of GE's SiC MOSFET proved to have the smallest temperature dependency, increasing by only 59 % from 25 ºC to 200 ºC. From the dynamic characterization, it was shown that Cree's C2M0080120D second generation SiC MOSFET achieved dv/dt rates of 57 V/ns. The SiC MOSFETs also featured low turn off switching energy losses, which were typically less than 70 µJ at 600 V bus voltage and 20 A load current.
Master of Science

Les matériaux semi-conducteurs à grand gap tels que le carbure de silicium (SiC) et le nitrure de gallium (GaN) sont utilisés pour fabriquer des composants semi-conducteurs de puissance, qui vont jouer un rôle très important dans le développement des futurs systèmes de conversion d'énergie. L'objectif est de réaliser des convertisseurs avec de meilleurs rendements énergétiques et fonctionnant à haute température. Pour atteindre cet objectif, il est donc nécessaire de bien connaître les caractéristiques de ces nouveaux composants afin de développer des modèles qui seront utilisés lors de la conception des convertisseurs. Cette thèse est donc dédiée à la caractérisation et la modélisation des composants à grand gap, mais également l'étude des dispositifs de mesure des courants des commutations des composants rapides. Afin de déterminer les caractéristiques statiques des composants semi-conducteurs, une méthode de mesure en mode pulsé est présentée. Dans le cadre de cette étude, une diode SiC et un JFET SiC "normally-off" sont caractérisés à l'aide de cette méthode. Afin de mesurer les capacités inter-électrodes de ces composants, une nouvelle méthode basée sur l'utilisation des pinces de courant est proposée. Des modèles comportementaux d'une diode Si et d'un JFET SiC sont proposés en utilisant les résultats de caractérisation. Le modèle de la diode obtenu est validé par des mesures des courants au blocage (recouvrement inverse) dans différentes conditions de commutation. Pour valider le modèle du JFET SiC, une méthode de mesure utilisant une pince de courant de surface est proposée
Compared to traditional silicon (Si) semiconductor material, wide bandgap (WBG) materials like silicon carbide (SiC) and gallium nitride are gradually applied to fabricate power semiconductor devices, which are used in power converters to achieve high power efficiency, high operation temperature and high switching frequency. As those power devices are relatively new, their characterization and modeling are important to better understand their characteristics for better use. This dissertation is mainly focused on those WBG power semiconductor devices characterization, modeling and fast switching currents measurement. In order to measure their static characteristics, a single-pulse method is presented. A SiC diode and a "normally-off" SiC JFET is characterized by this method from ambient temperature to their maximal junction temperature with the maximal power dissipation around kilowatt. Afterwards, in order to determine power device inter-electrode capacitances, a measurement method based on the use of multiple current probes is proposed and validated by measuring inter-electrode capacitances of power devices of different technologies. Behavioral models of a Si diode and the SiC JFET are built by using the results of the above characterization methods, by which the evolution of the inter-electrode capacitances for different operating conditions are included in the models. Power diode models are validated with the measurements, in which the current is measured by a proposed current surface probe

The high-voltage SiC power semiconductor devices have been developed in recent years. They cause an urgent in the need for the power semiconductor packaging to have not only low interconnect resistance, less noise, less parasitic oscillations, improved reliability, and better thermal management, but also High-Voltage (HV) blocking capability. The existing power semiconductor packaging technologies includes wire-bonding interconnect, press pack, flip-chip technology, metal posts interconnected parallel plates structure (MIPPS), dimple array interconnection (DAI), power overlay (POL) technology, and embedded power (EP) technology. None of them meets the requirements of low profile and high voltage rating. The objective of the work in this dissertation is to propose and design a high-voltage power semiconductor device packaging method with low electric field stress and low profile to meet the requirments of high-voltage blocking capability. The main contributions of the work presented in this dissertation are: 1. Understanding the electric field distribution in the package. The power semiconductor packaging is simulated by using Finite Element Analysis (FEA) software. The electric field distribution is known and the locations of high electric field concentration are identified. 2. Development of planar high-voltage power semiconductor device packaging method With the proposed structure in the dissertation, the electric field distribution of a planar device package is improved and the high electric field intensity is relieved. 3. Development of design guidelines for the propsed planar high-voltage device packaging method. The influence of the structure dimensions and the material properties is studied. An optimal design is identified. The design guideline is given. 4. Fabrication and experimental verification of the proposed high-voltage device packaging method A detailed fabrication procedure which follows the design guideline is presented. The fabricated modules are tested by using a high power curve tracer. Test results verify the proposed method. 5. Simplification of the structure model of the proposed device package The package structure model is simplified through the elimination of power semiconductor device internal structure model. The simplified model can be simulated by a non-power device simulator. The simulation results of the simplified model match the simulation results of the complete model very well.
Ph. D.

Due to the superior characteristics compared to its silicon (Si) counterpart, the wide bandgap (WBG) semiconductor enables next-generation power electronics systems with higher efficiency and higher power density. With higher blocking voltage available, WBG devices, especially the silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET), have been widely explored in various medium-voltage (MV) applications in both industry and academia. However, due to the high di/dt and high dv/dt during the switching transient, potential overcurrent, overvoltage, and gate failure can greatly reduce the reliability of implementing SiC MOSFETs in an MV system. By utilizing the parasitic inductance between the Kelvin- and the power-source terminal, a short-circuit (SC) and overload (OL) dual-protection scheme is proposed for overcurrent protection. A full design procedure and reliability analysis are given for SC circuit design. A novel OL circuit is proposed to protect OL faults at the gate-driver level. The protection procedure can detect an SC fault within 50 nanoseconds and protect the device within 1.1 microsecond. The proposed method is a simple and effective solution for the potential overcurrent problem of the SiC MOSFET. For SiC MOSFETs in series-connection, the unbalanced voltages can result in system failure due to device breakdown or unbalanced thermal stresses. By injecting current during the turn-off transient, an active dv/dt control method is used for voltage balancing. A 6 kV phase-leg using eight 1.7 kV SiC MOSFETs in series-connection has been tested with voltage balanced accurately. Modeling of the stacked SiC MOSFET with active dv/dt control is also done to summarize the design methodology for an effective and stable system. This method provides a low-loss and compact solution for overvoltage problems when MV SiC MOSFETs are connected in series. Furthermore, a scalable auxiliary power network is proposed to prevent gate failure caused by unstable gate voltage or EMI interference. The two-stage auxiliary power network (APN) architecture includes a wireless power transfer (WPT) converter supplied by a grounded low voltage dc bus, a high step-down-ratio (HSD) converter powered from dc-link capacitors, and a battery-based mini-UPS backup power supply. The auxiliary-power-only pre-charge and discharge circuits are also designed for a 6 kV power electronics building block (PEBB). The proposed architecture provides a general solution of a scalable and reliable auxiliary power network for the SiC-MOSFET-based MV converter. For the WPT converter, a multi-objective optimization on efficiency, EMI mitigation, and high voltage insulation capability have been proposed. Specifically, a series-series-CL topology is proposed for the WPT converter. With the optimization and new topology, a 120 W, 48 V to 48 V WPT converter has been tested to be a reliable part of the auxiliary power network. For the HSD converter, a novel unidirectional voltage-balancing circuit is proposed and connected in an interleaved manner, which provides a fully modular and scalable solution. A ``linear regulator + buck" solution is proposed to be an integrated on-board auxiliary power supply. A 6 kV to 45 V, 100 W converter prototype is built and tested to be another critical part of the auxiliary power network.
Doctor of Philosophy
The wide bandgap semiconductor enables next-generation power electronics systems with higher efficiency and higher power density which will reduce the space, weight, and cost for power supply and conversion systems, especially for renewable energy. However, by pushing the system voltage level higher to medium-voltage of tens of kilovolts, although the system has higher efficiency and simpler control, the reliability drops. This dissertation, therefore, focusing on solving the possible overcurrent, overvoltage, and gate failure issues of the power electronics system that is caused by the high voltage and high electromagnetic interference environment. By utilizing the inductance of the device, a dual-protection method is proposed to prevent the overcurrent problem. The overcurrent fault can be detected within tens of nanoseconds so that the device will not be destroyed because of the huge fault current. When multiple devices are connected in series to hold higher voltage, the voltage sharing between different devices becomes another issue. The proposed modeling and control method for series-connected devices can balance the shared voltage, and make the control system stable so that no overvoltage problem will happen due to the non-evenly distributed voltages. Besides the possible overcurrent and overvoltage problems, losing control of the devices due to the unreliable auxiliary power supply is another issue. This dissertation proposed a scalable auxiliary power network with high efficiency, high immunity to electromagnetic interference, and high reliability. In this network, a wireless power transfer converter is designed to provide enough insulation and isolation capability, while a switched capacitor converter is designed to transfer voltage from several kilovolts to tens of volts. With the proposed overcurrent protection method, voltage sharing control, and reliable auxiliary power network, systems utilizing medium-voltage wide-bandgap semiconductor will have higher reliability to be implemented for different applications.

The emergence of SiC power devices requires evaluation of benefits and issues of the technology in applications. This is important since SiC power devices are still not as mature as their silicon counterparts. This research, in its own capacity, highlights some of the major challenges and analyzes them through extensive experimental measurements which are performed in many different conditions seeking to emulate various applications scenarios. It is shown that fast SiC unipolar devices, inherently reduce the switching losses while maintain low conduction losses comparable with contemporary bipolar technologies. This translates into lower temperature excursions and an enhanced conversion efficiency. However, such high switching rates may trigger problems in the device utilizations. The switching rates influenced by the device input capacitance can cause significant ringing in the output, especially in SiC SBDs. Measurements show that switching rate of MOSFETs increases with increasing temperature in turn on and reduces in turn off. Hence, the peak voltage overshoot and oscillation severity of the SiC SBD increases with temperature during diode turn off. This temperature dependence reduces at the higher switching rates. So accurate analytical models are developed for predicting the switching energy in unipolar SiC SBDs and MOSFET pairs and bipolar silicon PiN and IGBT pairs. A key parameter for power devices is electrothermal robustness. SiC MOSFETs have already demonstrated such merits compared to silicon IGBTs, however not for MOSFET body diodes. This research has quantified this in comparison with the similarly rated contemporary device technologies like CoolMOS. In a power MOSFET, high switching rates coupled with the capacitance of drain and body causes a displacement current in the resistive path of P body, inducing a voltage on base of the parasitic NPN BJT which might forward bias it. This may lead to latch up and destruction if the thermal limits are surpassed. Hence, trade offs between switching energy and electrothermal robustness are explored for the silicon, SiC and superjunction power MOSFETs. Measurements show that performance of body diodes of SiC MOSFETs is the most efficient due to least reverse recovery. The minimum forward current for inducing dynamic latch up decreases with increasing voltage, switching rate and temperature for all technologies. The CoolMOS exhibited the largest latch up current followed by the SiC and silicon power MOSFETs. Another problem induced by high switching rates is the electrical coupling between complementing devices in the same phase leg which manifests as short circuits across the DC link voltage. This has been understood for silicon IGBTs with known corrective techniques, however it is seen that due to smaller Miller capacitance resulting from a smaller die area, the SiC module exhibits smaller shoot through currents in spite of higher switching rates and a lower threshold voltage. Measurements show that the shoot through current exhibits a positive temperature coefficient for both technologies the magnitude of which is higher for the silicon IGBT. The effectiveness of common techniques of mitigating shoot through is also evaluated, showing that solutions are less effective for SiC MOSFET because of the lower threshold voltages and smaller margins for a negative gate bias.

This manuscript describes the design, development, and implementation of a linear high efficiency power amplifier. The symmetrical Doherty power amplifier utilizes TriQuint's 2nd Generation Gallium Nitride (GaN) on Silicon Carbide (SiC) High Electron Mobility Transistor (HEMT) devices (T1G6001032-SM) for a specified design frequency of 3.6 GHz and saturated output power of 40 dBm. Advanced Design Systems (ADS) simulation software, in conjunction with Modelithic's active and passive device models, were used during the design process and will be evaluated against the final measured results. The use of these device models demonstrate a successful first-pass design, putting less dependence on classical load pull analysis, thereby decreasing the design-cycle time. The Doherty power amplifier is a load modulated amplifier containing two individual amplifiers and a combiner network which provides an impedance inversion on the path between the two amplifiers. The carrier amplifier is biased for Class-AB operation and works as a conventional linear amplifier. The second amplifier is biased for Class-C operation, and acts as the peaking amplifier that turns on after a certain instantaneous power has been reached. When this power transition is met the carrier amplifier's drain voltage is already approaching saturation. If the input power is further increased, the peaking amplifier modulates the load seen by the carrier amplifier, such that the output power can increase while maintaining a constant drain voltage on the carrier amplifier. The Doherty power amplifier can improve the efficiency of a power amplifier when the input power is backed-off, making this architecture particularly attractive for high peak-to-average ratio (PAR) environments. The design presented in this manuscript is tuned to achieve maximum linearity at the compromise of the 6dB back-off efficiency in order to maintain a carrier-to- intermodulation ratio greater than 30 dB under a two-tone intermodulation distortion test with 5 MHz tone spacing. Other key figures of merit (FOM) used to evaluate the performance of this design include the power added efficiency (PAE), transducer power gain, scattering parameters, and stability. The final design is tested with a 20 MHz LTE waveform without digital pre-distortion (DPD) to evaluate its linearity reported by its adjacent channel leakage ratio (ACLR). The dielectric substrate selected for this design is 15 mil Taconic RF35A2 and was selected based on its low losses and performance at microwave frequencies. The dielectric substrate and printed circuit board (PCB) design were also modeled using ADS simulation software, to accurately predict the performance of the Doherty power amplifier. The PCB layout was designed so that it can be mounted to an existing 4" x 4" aluminum heat sink to dissipate the heat generated by the transistors while the part is being driven. The performance of the 3.6 GHz symmetrical Doherty power amplifier was measured in the lab and reported a maximum PAE of 55.1%, and a PAE of 48.5% with the input power backed-off by 6dB. These measured results closely match those reported by design simulations and demonstrate the models' effectiveness for creating a first-pass functional design.

The development of high power density three-phase ac converter has been a hot topic in power electronics area due to the increasing needs in applications like electric vehicle, aircraft and aerospace, where light weight and/or low volume is usually a must. Many challenges exist due to the complicated correlations in a three-phase power converter system. In addition, with the emerging SiC device technology the operating frequency of the converter can be potentially pushed to the range from tens of kHz to hundreds of kHz at higher voltage and higher power conditions. The extended frequency range brings opportunities to further improve the power density of the converter. Technologies based on existing devices need to be revisited. In this dissertation, a systematic methodology to analyze and design the high power density three-phase ac converter is developed. All the key factors of the converter design are explored from the high density standpoint. Firstly, the criteria for the passive filter selection are derived and the relationship between the switching frequency and the size of the EMI filter is investigated. A function integration concept as well as the physical design approach is proposed. Secondly, a topology evaluation method is presented, which provides the insight into the relationships between the system constraints, operating conditions and design variables. Four topologies are then compared with the proposed approach culminating with a favored topology under the given conditions. Thirdly, a novel average model is developed for the selected topology, and used for devising a carrier-based control approach with simple calculation and good regulation performance. Fourthly, the converter failure mode operation and corresponding protection approaches are discussed and developed. Finally, a 10 kW three-phase ac/ac converter is built with the SiC devices. All the key concepts and ideas developed in this work are implemented in this hardware system and then verified by the experimental results.
Ph. D.

In recent years, the SiC power semiconductor has emerged as an attractive alternative that pushes the limitations of junction temperature, power rating, and switching frequency of Si devices. These advanced properties will lead converters to higher power density. However, the reliability of the SiC semiconductor is still under investigation, and at the same time, the standard Si device packages do not meet the requirement of high temperature operation. In order to take full advantage of SiC semiconductor devices, high density, high temperature device packaging needs to be developed. In this dissertation, a high temperature wirebond package for multi-chip phase-leg power module using SiC devices was designed, developed, fabricated and tested. The details of the material selection and thermo-mechanical reliability evaluation are described. High temperature power test shows that the presented package can perform well at the high junction temperature. In order to increase the power density, reduce the parasitic parameters, and enhance the electrical, thermo-mechanical performance over wirebond packages, planar package is utilized to better take advantages of SiC device. This dissertation proposed a novel package, in which the interconnections can be formed on small dimensional pads and enclosed pads that may baffle the regular solder based connection in other planar packages. Electrical and thermo-mechanical tests of the prototype module demonstrate the functionality and reliability of the presented planar packaging methodology. In this dissertation, together with the design example, the manual module layout design and automatic module layout design process are also presented. Furthermore, a systematic optimal design process and parametric study of the heatsink-fan cooling system by applying the analytical model is described. This dissertation also established a systematic testing procedure which can rapidly detect defects and reduce the risk in high temperature packaging testing. Finally, a wirebond module and a planar module are designed for 175 ºC junction temperature and 250 ºC junction temperatures. All the key concepts and ideas developed in this work are implemented in the prototype module development and then verified by the experimental results.
Ph. D.

Auxiliary power supply (APS) plays a key role in ensuring the safe operation of the main circuit elements including gate drivers, sensors, controllers, etc. in medium voltage (MV) silicon carbide (SiC)-based converter systems. Such a converter requires APS to have high insulation capability, low common-mode coupling capacitance (Ccm ), and high-power density. Furthermore, considering the lifetime and simplicity of the auxiliary power supply system design in the MV converter, partial discharge (PD) free and multi-load driving ability are the additional two factors that need to be addressed in the design. However, today’s state-of-the-art products have either low power rating or bulky designs, which does not satisfy the demands. To improve the current designs, this thesis presents a 1 MHz isolated APS design using gallium nitride (GaN) devices with MV insulation reinforcement. By adopting LCCL-LC resonant topology, the proposed APS is able to supply multiple loads simultaneously and realize zero voltage switching (ZVS) at any load conditions. Since high reliability under faulty load conditions is also an important feature for APS in MV converter, the secondary side circuit of APS is designed as a regulated stage. To achieve MV insulation (> 20 kV) as well as low Ccm value (< 5 pF), a current-based transformer with a single turn structure using MV insulation wire is designed. Furthermore, by introducing different insulated materials and shielding structures, the APS is capable to achieve different partial discharge inception voltages (PDIV). In this thesis, the transformer design, resonant converter design, and insulation strategies will be detailly explained and verified by experiment results. Overall, this proposed APS is capable to supply multiple loads simultaneously with a maximum power of 120 W for the sending side and 20 W for each receiving side in a compact form factor. ZVS can be realized regardless of load conditions. Based on different insulation materials, two different receiving sides were built. Both of them can achieve a breakdown voltage of over 20 kV. The air-insulated solution can achieve a PDIV of 6 kV with Ccm of 1.2 pF. The silicone-insulated solution can achieve a PDIV of 17 kV with Ccm of 3.9 pF.
M.S.
Recently, 10 kV silicon carbide (SiC) MOSFET receives strong attention for medium voltage applications. Asit can switch at very high speed, e.g. > 50 V/ns, the converter system can operate at higher switching frequency condition with very small switching losses compared to silicon (Si) IGBT [8]. However, the fast dv/dt noise also creates the common mode current via coupling capacitors distributed inside the converter system, thereby introducing lots of electromagnetic interference (EMI) issues. Such issues typically occur within the gate driver power supplies due to the high dv/dt noises across the input and output of the supply. Therefore, the ultra-small coupling capacitor (<5 pF) of a gate driver power supply is strongly desired.[37] To satisfy the APS demands for high power modular converter system, a solution is proposed in this thesis. This work investigates the design of 1 MHz isolated APS using gallium nitride (GaN) devices with medium voltage insulation reinforcement. By increasing switching frequency, the overall converter size could be reduced dramatically. To achieve a low Ccm value and medium voltage insulation of the system, a current-based transformer with a single turn on the sending side is designed. By adopting LCCL-LC resonant topology, a current source is formed as the output of sending side circuity, so it can drive multiple loads importantly with a maximum of 120 W. At the same time, ZVS can use realized with different load conditions. The receiving side is a regulated stage, so the output voltage can be easily adjusted and it can operate in a load fault condition. Different insulation solutions will be introduced and their effect on Ccm will be discussed. To further reduce Ccm, shielding will be introduced. Overall, this proposed APS can achieve a breakdown voltage of over 20 kV and PDIV up to 16.6 kV with Ccm<5 pF. Besides, multi-load driving ability is able to achieve with a maximum of 120 W. ZVS can be realized. In the end, the experiment results will be provided.

The knowledge about the reliability of power electronics is necessary for the design of converters. Especially for offshore applications it is essential to know, which fatigue processes happen and how the lifetime can be estimated. Numerical simulation is an important tool for the development of power electronic systems. This thesis analyse the thermal and thermal-mechanical behaviour of packages for power semiconductor devices with the help of simulations. One topic is the evaluation of different thermal models. The main focus is on the description of the thermal cross-coupling between the devices and the influence to the lifetime estimation. The power module is a well established package for power semiconductor devices. It will be explained how the heating period of power cycles influences the failure mode of this package type. Additionally, it will evaluated how SiC devices and DAB substrates influence the power cycling capability. The press-pack is in focus for high power applications as the package short-circuits during an electrical failure without external auxiliary systems. However, the knowledge about the power cycling behaviour is currently limited. With the help of simulations this behaviour will be analysed and possible weak points will be also derived. In the end of the work it will be discussed, how the lifetime can be estimated with help of FEM simulations
Für die Entwicklung von Umrichtern ist die Kenntnis über die Zuverlässigkeit der Leistungselektronik ein wichtiges Kernthema. Insbesondere für Offshore-Anwendungen ist das Wissen über die stattfindenden Ermüdungsprozesse und die Abschätzung der zu erwartenden Lebensdauer der Bauteile essentiell. Hierfür hat sich die Simulation als ein wichtiges Werkzeug für die Entwicklung und Lebensdauerbewertung von leistungselektronischen Anlagen etabliert. In der folgenden Arbeit wird das thermische und das thermisch-mechanische Verhalten der Leistungselektronik mittels Simulationen untersucht. Hierzu wird ein Vergleich zwischen verschiedenen thermischen Modellen für Leistungsbauelemente durchgeführt. Schwerpunkt ist die Beschreibung der thermischen Kopplung zwischen den Chips und deren Einfluss auf die Lebensdauerabschätzung. Ein weiterer Schwerpunkt ist das Leistungsmodul, welches sich als ein Standardgehäuse etabliert hat. Dazu wird erklärt, wie die Variation der Einschaltzeit im aktiven Lastwechseltest den Fehlermodus dieses Gehäusetyps beeinflusst. Weiterhin wird untersucht, wie SiC als Leistungshalbleiter und DAB als Substrat die Zuverlässigkeit beein- flusst. Der Press-Pack ist für Hochleistungsapplikationen von hohem Interesse, da dieses Gehäuse im elektrischen Fehlerfall ohne äußere Unterstützung kurzschliesst. Jedoch ist das Wissen über diese Gehäusetechnologie unter aktiven Lastwechselbedingungen sehr limitiert. Mit Hilfe von Simulationen wird dieses Verhalten untersucht und mögliche Schwachpunkte abgeleitet. Am Ende der Arbeit werden Möglichkeiten untersucht, wie Mithilfe von FEM Simulationen die Lebensdauer von Leistungsmodulen evaluiert werden kann

Classiquement, la chaîne de conversion de l’énergie électrique des centrales photovoltaïques comporte un champ photovoltaïque (PV) délivrant une tension maximale de 1kV suivi d’un hacheur élévateur connecté à un onduleur de tension triphasé. Cette chaîne de conversion à deux étages (DC/DC + DC/AC) est ensuite raccordée sur le réseau moyenne tension au travers d’un transformateur BT/HTA. Dans l’objectif de simplifier les systèmes de conversion PV, ce travail de recherche s’intéresse à l’étude et la mise en œuvre d’une topologie DC/AC n’employant qu’un seul étage de conversion : l’Onduleur de Courant triphasé. Bien que relativement simple, l’Onduleur de Courant présente comme inconvénient majeur les pertes par conduction. Pour pallier ce problème, des interrupteurs à grand-gap au Carbure de Silicium (SiC) sont employés, ce qui permet de convertir de l’énergie de façon performante (η>98.5%) tout en gardant une fréquence de commutation élevée (plusieurs dizaines de kHz). Les modules à semi-conducteurs de puissance du marché n’étant pas compatibles avec ce type de convertisseur, des modules particuliers en SiC ont été développés dans le cadre de la thèse. La caractérisation dynamique de ces nouveaux modules est réalisée dans le but de servir de base à la conception d’un démonstrateur de l’Onduleur de Courant d’une puissance nominale de 60kW. Enfin, le rendement de la partie semi-conducteur de puissance est évalué par une méthode calorimétrique confirmant l’aptitude de la topologie à fonctionner à des fréquences de commutation supérieures. L’originalité de ces travaux réside principalement dans la conception, caractérisation et mise en œuvre de ce nouveau module de puissance adapté à cette topologie connue, mais peu étudiée à l’heure actuelle avec des interrupteurs au SiC
Classically, the energy conversion architecture found in photovoltaic (PV) power plants comprises a multitude of solar arrays delivering a maximum voltage of 1kV followed by a step-up chopper connected to a three-phase voltage source inverter. This two-stage conversion system (DC/DC + DC/AC) is then connected to the MV grid through a LV/MV transformer. In order to simplify the PV systems, this research work focuses on the study and implementation of a DC/AC topology employing a single conversion stage: the three-phase current source inverter (CSI). Although relatively simple, the CSI presents as major drawback the conduction losses. To deal with this problem, wide-bandgap silicon carbide (SiC) semiconductors are used, which allows to efficiently convert energy (η> 98.5%) while keeping a relatively high switching frequency (several tens of kHz). Nonetheless, since the available power semiconductor modules on the market are not compatible with the CSI, a novel 1.7kV SiC-based module is developed in the context of the thesis. Thus, the dynamic characterization of the new SiC device is carried out and serves as a basis for the design of a 60kW Current Source Inverter prototype. Finally, the inverter’s semiconductor efficiency is evaluated through a calorimetric method, confirming the ability of the topology to operate at higher switching frequencies. At the present time, little research has been conducted on the CSI implementation with SiC devices. The originality of this work lies mainly in the design, characterization and implementation of the new SiC power module adapted to this well-known inverter topology

The knowledge about the reliability of power electronics is necessary for the design of converters. Especially for offshore applications it is essential to know, which fatigue processes happen and how the lifetime can be estimated. Numerical simulation is an important tool for the development of power electronic systems. This thesis analyse the thermal and thermal-mechanical behaviour of packages for power semiconductor devices with the help of simulations. One topic is the evaluation of different thermal models. The main focus is on the description of the thermal cross-coupling between the devices and the influence to the lifetime estimation. The power module is a well established package for power semiconductor devices. It will be explained how the heating period of power cycles influences the failure mode of this package type. Additionally, it will evaluated how SiC devices and DAB substrates influence the power cycling capability. The press-pack is in focus for high power applications as the package short-circuits during an electrical failure without external auxiliary systems. However, the knowledge about the power cycling behaviour is currently limited. With the help of simulations this behaviour will be analysed and possible weak points will be also derived. In the end of the work it will be discussed, how the lifetime can be estimated with help of FEM simulations.
Für die Entwicklung von Umrichtern ist die Kenntnis über die Zuverlässigkeit der Leistungselektronik ein wichtiges Kernthema. Insbesondere für Offshore-Anwendungen ist das Wissen über die stattfindenden Ermüdungsprozesse und die Abschätzung der zu erwartenden Lebensdauer der Bauteile essentiell. Hierfür hat sich die Simulation als ein wichtiges Werkzeug für die Entwicklung und Lebensdauerbewertung von leistungselektronischen Anlagen etabliert. In der folgenden Arbeit wird das thermische und das thermisch-mechanische Verhalten der Leistungselektronik mittels Simulationen untersucht. Hierzu wird ein Vergleich zwischen verschiedenen thermischen Modellen für Leistungsbauelemente durchgeführt. Schwerpunkt ist die Beschreibung der thermischen Kopplung zwischen den Chips und deren Einfluss auf die Lebensdauerabschätzung. Ein weiterer Schwerpunkt ist das Leistungsmodul, welches sich als ein Standardgehäuse etabliert hat. Dazu wird erklärt, wie die Variation der Einschaltzeit im aktiven Lastwechseltest den Fehlermodus dieses Gehäusetyps beeinflusst. Weiterhin wird untersucht, wie SiC als Leistungshalbleiter und DAB als Substrat die Zuverlässigkeit beein- flusst. Der Press-Pack ist für Hochleistungsapplikationen von hohem Interesse, da dieses Gehäuse im elektrischen Fehlerfall ohne äußere Unterstützung kurzschliesst. Jedoch ist das Wissen über diese Gehäusetechnologie unter aktiven Lastwechselbedingungen sehr limitiert. Mit Hilfe von Simulationen wird dieses Verhalten untersucht und mögliche Schwachpunkte abgeleitet. Am Ende der Arbeit werden Möglichkeiten untersucht, wie Mithilfe von FEM Simulationen die Lebensdauer von Leistungsmodulen evaluiert werden kann.

L'objectif du projet VELSIC a été de démontrer la faisabilité de jonctions p+/n- profondes dans le semiconducteur 4H-SiC, de haute qualité électrique, comprenant une zone p++ réalisée par un procédé original d'épitaxie localisée à basse température (1100 – 1200°C), en configuration VLS (Vapeur - Liquide - Solide). Cette technique innovante de dopage par épitaxie utilise le substrat de SiC mono cristallin comme un germe de croissance sur lequel un empilement enterré de Al - Si est porté à fusion pour constituer un bain liquide, lequel est alimenté en carbone par la phase gazeuse. Cette méthode se positionne comme une alternative avantageuse à l'implantation ionique, actuellement utilisée par tous les fabricants de composants en SiC, mais qui présente des limitations problématiques encore non résolues à ce jour. Les travaux de thèse ont exploré toutes les facettes du processus complet de fabrication de diodes de test, avec une attention particulière portée sur l'optimisation de la gravure de cuvettes dans le substrat SiC. Le cœur des travaux a été concentré sur l'optimisation de l'épitaxie VLS localisée. L'étude a confirmé la nécessité de limiter la vitesse de croissance vers 1 µm/h pour conserver une bonne cristallinité du matériau épitaxié. Elle a également mis en évidence l'action directe du champ électromagnétique radiofréquence sur la phase liquide, conduisant à une très forte influence du diamètre des cuvettes gravées sur l'épaisseur du SiC déposé. Un remplissage quasiment complet des cuvettes de 1 µm de profondeur à très fort dopage p++ a été démontré. À partir des couches VLS optimisées, des démonstrateurs de types diodes p+/n- ont été fabriqués. Sur les meilleurs échantillons, sans passivation ni protection périphérique, des tensions de seuil en régime direct (entre 2,5 et 3 V) ont, pour la première fois, été mesurées, sans recourir à un recuit haute température après épitaxie. Elles correspondent aux valeurs attendues pour une vraie jonction p-n sur 4H-SiC. Des densités de courant de plusieurs kA/cm2 ont également pu être injectées pour des tensions situées autour de 5 - 6 V. En régime de polarisation inverse, aucun claquage n'est observé jusqu'à 400 V et les densités de courant de fuite à faible champ électrique dans la gamme 10-100 nA/cm2 ont été mesurées. Toutes ces avancées si situent au niveau de l'état de l'art pour des composants SiC aussi simples, toutes techniques de dopage confondues
The objective of the VELSIC project has been to demonstrate the feasibility of 1 µm deep p+/n- junctions with high electrical quality in 4H-SiC semiconductor, in which the p++ zone is implemented by an original low-temperature localized epitaxy process ( 1100 - 1200 °C ), performed in the VLS (Vapor - Liquid - Solid) configuration. This innovative epitaxy doping technique uses the monocrystalline SiC substrate as a crystal growth seed. On the substrate (0001-Si) surface, buried patterns of Al - Si stack are fused to form liquid islands which are fed with carbon by C3H8 in the gas phase. This method is investigated as a possible higher performance alternative to the ion implantation process, currently used by all manufacturers of SiC devices, but which still experiences problematic limitations that are yet unresolved to date. Although the main focus of the study has been set on the optimization of localized VLS epitaxy, our works have explored and optimized all the facets of the complete process of test diodes, from the etching of patterns in the SiC substrate up to the electrical I - V characterization of true pn diodes with ohmic contacts on both sides.Our results have confirmed the need to limit the growth rate down to 1 µm/h to maintain good crystallinity of the epitaxial material. It has also highlighted the direct action of the radiofrequency electromagnetic field on the liquid phase, leading to a very strong influence of the diameter of the etched patterns on the thickness of the deposited SiC. A nearly complete filling of the 1 µm deep trenches with very high p++ doping has been demonstrated. Using optimized VLS growth parameters, p+/n- diode demonstrators have been processed and tested. On the best samples, without passivation or peripheral protection, high direct-current threshold voltages, between 2.5 and 3 V, were measured for the first time without any high-temperature annealing after epitaxy. These threshold voltage values correspond to the expected values for a true p-n junction on 4H-SiC. Current densities of several kA/cm2 have also been injected at voltages around 5 - 6 V. Under reverse bias conditions, no breakdown is observed up to 400 V and low leakage current densities at low electric field, in the range 10 - 100 nA/cm2, have been measured. All these advances align with or exceed state-of-the-art results for such simple SiC devices, obtained using any doping technique

A DC-DC converter is used in electrified and hybrid vehicles to supply powerto the low voltage (ex. 24V) system including headlights, horn, air conditioningsystem, wipers, radio, etc. The converter is fed from a high voltage (ex. 650V)battery, which is available in electric/hybrid vehicles, and transfers a relativelyhigh power. SCANIA’s conventional converters, used so far, have silicon-basedswitches, i.e., Si IGBT; and there is an intention to replace the converter with theupgraded counterpart in which SiC-based transistors (SiC-MOSFET) are usedinstead. Wide band-gap silicon carbide (SiC) semiconductor material offers possibilitiesof faster switching, high-temperature operation, and higher breakdownvoltage for power transistors. SCANIA is investigating the reliability of thesecond generation converter in which the Si IGBT transistors are replaced bySiC-MOSFET transistors. In this thesis, the reliability of a SiC-based switchesused in DC-DC converter of electrified trucks is investigated. The investigationis principally based on different reliability tests results carried out in both switchand converter levels.To investigate the reliability of SIC MOSFET transistors, first different failuremechanisms, such as gate oxide layer degradation, high-frequency side effects,etc., are introduced, and corresponding test results are presented and discussed.On converter level, the reliability study of SCANIA’s first generation converteris considered, and the weak components in the converter are identified.In this thesis, the test results provided by SiC-MOSFET and converter suppliersare analyzed and compared with the similar test results conducted on the Sibasedconverter. In additions, SCANIA performs some particular tests based onits own standardization related to different environmental working conditions,such as high ambient temperature and high vibration situation, to assure thematurity and robustness of the SiC-based converter. These test results arepresented and discussed.By comparing investigation outcomes acquired from different suppliers and customers,it is shown that the SiC MOSFET transistor is more efficient that Sibasedtransistor. It is also demonstrated that SiC MOSFET is more robust andreliable in high power, high voltage, and high switching frequency applications.The SCANIA’s second generation DC-DC converter has shown advantages overthe first generation; it is more efficient, lighter, and more compact. From thereliability point of view, the second generation has passed almost all relevanttests.
En DC-DC-omvandlare används i elektrifierade fordon för att ge ström åt dess lågspänningssystem (ex. 24V) vilket kan omfatta bl.a. inklusive strålkastare, horn, luftkonditioneringssystem, vindrutetorkare, radio etc. Omvandlaren matas från fordonets högspänningsbatteri (ex 650VDC) och överför en relativt hög ef- fekt till lågspänningssystemet. SCANIAs befintliga omvandlare använder sig av kiselbaserade transistorer (Si IGBT), och det finns en avsikt att ersätta omvandlaren med en uppgraderad motsvarighet vid vilken kiselkarbidbaserade transistorer (SiC MOSFET) används istället. SiC-baserade halvledarmaterial erbjuder bl.a. möjlighet till högre switch-frekvenser, högre drifttemperatur och högre spänningstålighet. I denna avhandling utreds tillförlitligheten av SiC-baserade transistorer som används i DC-DC-omvandlare inom elektrifier- ade fordonsbranschen. Undersökningen baseras huvudsakligen på resultat från olika tillförlitlighetstester utförda på både transistor- och omvandlarnivå. För att undersöka och analysera tillförlitligheten hos SiC MOSFET-transistorer har olika felmekanismer såsom nedbrytning av ”gate oxid”-skiktet, högfrekventa biverkningar, etc., presenterats och diskuterats tillsammans med motsvarande testresultat. För jämförelse har man på omvandlarnivå, utrett tillförlitligheten av Scania’s befintliga omvandlare och identifierat dess svaga komponenterna. I denna studie har testresultaten, som tillhandahålls av leverantörer av SiC- MOSFET transistorer, analyserats och jämförts med liknande testresultat som har genomförts på Si-baserade omvandlare. Utöver det utför Scania vissa speci- fika tester som är baserade på egna standardiserade prover, för att försäkra sig om omvandlarens mognad och robusthet. Dessa är relaterade till olika miljöförhållanden, t.ex. hög omgivningstemperatur och hög vibrationsnivå. Testresultaten presenteras och diskuteras i avhandlingen. Genom att jämföra testresultat från olika leverantörer kan man dra slutsatsen att SiC MOSFET-transistorer är effektivare än Si-transistorer. Dessutom visade sig att SiC MOSFET är mer robust och tillförlitlig i applikationer som kräver högre effekter, högre spänningar och högre switching-frekvenser. Den andra generationen av Scania’s DC-DC-omvandlare har visat flera förde- lar över den första generationen; nämligen att den är mer effektiv, lättare, mer kompakt och billigare. Från ett tillförlitlighetsperspektiv har den andra generationen har passerat nästan alla relevanta tester.

L'objectif du projet CONCIGI-HT (CONvertisseur alternatif-continu Compact à Isolement Galvanique Intégré Haute Tension) est d'augmenter le rendement des chaînes de traction tout en réduisant la masse et le volume de la fonction de conversion Alternatif/Continu. Pour cela, l'ensemble transformateur basse fréquence - redresseur est remplacé par une structure multi-convertisseurs, directement connectée à la caténaire haute tension et intégrant des transformateurs fonctionnant en moyenne fréquence (plusieurs kHz). Cette thèse concerne plus particulièrement la caractérisation et la mise en œuvre de composants semi-conducteurs haute tension dans des structures de conversion statiques à étage intermédiaire moyenne fréquence. L'étude est effectuée sur la base d'une chaîne de traction de 2 MW fonctionnant sur un réseau 25 kV/50 Hz. Le premier chapitre présente l'état de l'art de l'Automotrice à Grande Vitesse (AGV) récemment produite par ALSTOM. C'est la chaîne de traction de cet engin qui sert de référence pour l'étude des nouvelles topologies à transformateur moyenne fréquence. Le deuxième chapitre décrit tout d'abord la structure d'une chaîne de traction classique et présente ensuite deux topologies multicellulaires à transformateur moyenne fréquence applicables en traction électrique ferroviaire (la structure indirecte à redresseur de courant MLI et convertisseur DC/DC à résonance ainsi que la topologie directe associant des convertisseurs duaux). Les avantages et inconvénients de ces topologies sont mis en évidence. Le troisième chapitre concerne la mise en œuvre et la caractérisation en commutation douce de composants Silicium 6,5 kV dans les deux topologies présentées précédemment. Deux bancs de test, représentant un étage élémentaire de conversion, ainsi que des allumeurs spécifiques dédiés à la commutation douce, ont été réalisés. Ils permettent l'étude des semi-conducteurs en régime permanent dans des conditions nominales de fonctionnement (3,6 kV / 100 A). Le quatrième chapitre présente la mise en œuvre et la caractérisation de composants en carbure de silicium (SiC). Pour cela des modules de puissance à base de puces 10 kV (MOSFET et Diodes) ont été réalisés. Les résultats expérimentaux, obtenus sur les bancs de test réalisés au chapitre précédent, mettent en évidence une réduction significative des pertes et démontrent la viabilité de la topologie à convertisseurs duaux pour une application en 25 kV/50 Hz. La conclusion présente un premier design d'un bloc élémentaire et les gains en masse et volume ainsi que les économies d'énergies qui pourront être obtenus par rapport à une structure classique
The objective of the CONCIGI-HT project (Compact AC/DC converter with Integrated High Voltage Galvanic Insulation) is to increase the efficiency of traction drives while reducing the mass and volume of the AC/DC conversion. To do that, the part low-frequency transformer - rectifier is replaced by a multi-converter topology, directly connected to the high voltage power supply and incorporating medium frequency transformers (several kHz). This thesis relates more particularly to the characterization and implementation of high voltage semiconductors in conversion topologies with intermediate medium frequency link. The study is performed on the basis of a traction drive of 2 MW operating on a 25 kV/50 Hz power supply. The first chapter presents the state of the art of the Automotrice à Grande Vitesse (AGV) recently produced by ALSTOM. The traction drive of this vehicle is used as a reference for the study of new topologies with medium frequency transformer. The second chapter first describes the structure of a conventional traction drive and then presents two multicellular topologies with medium frequency transformer applicable to railway traction (the indirect structure with PWM rectifier and DC/DC resonant converter and the direct topology combining dual converters). The advantages and disadvantages of these topologies are highlighted. The third chapter deals with the implementation and soft switching characterization of 6.5 kV Silicon components in both topologies presented above. Two test benches, representing a basic conversion stage, as well as specific drivers dedicated to the soft switching, has been made. They allow the study of semiconductors in nominal operating conditions (3.6 kV / 100 A). The fourth chapter presents the implementation and characterization of silicon carbide components (SiC). For this, power modules based on 10 kV chips (MOSFET and Diodes) have been achieved. The experimental results obtained on test benches made in the previous chapter, show a significant reduction in losses and demonstrate the viability of the dual converter topology for a 25 kV/50 Hz application. The conclusion presents the first design of an elementary block and gains in mass and volume as well as the energy savings that can be achieved compared to a conventional structure

Advances in wide-bandgap semiconductor devices have increased the allowable operating temperature of power electronic systems. High-temperature devices can benefit applications such as renewable energy, electric vehicles, and space-based power electronics that currently require bulky cooling systems for silicon power devices. Cooling systems can typically be reduced in size or removed by adopting wide-bandgap semiconductor devices, such as silicon carbide. However, to do this, semiconductor device packaging with high reliability at high temperatures is necessary. Transient liquid phase (TLP) die-attach has shown in literature to be a promising bonding technique for this packaging need. In this work TLP has been comprehensively investigated and characterized to assess its viability for high-temperature power electronics applications. The reliability and durability of TLP die-attach was extensively investigated utilizing electrical resistivity measurement as an indicator of material diffusion in gold-indium TLP samples. Criteria of ensuring diffusive stability were also developed. Samples were fabricated by material deposition on glass substrates with variant Au–In compositions but identical barrier layers. They were stressed with thermal cycling to simulate their operating conditions then characterized and compared. Excess indium content in the die-attach was shown to have poor reliability due to material diffusion through barrier layers while samples containing suitable indium content proved reliable throughout the thermal cycling process. This was confirmed by electrical resistivity measurement, EDS, FIB, and SEM characterization. Thermal and mechanical characterization of TLP die-attached samples was also performed to gain a newfound understanding of the relationship between TLP design parameters and die-attach properties. Samples with a SiC diode chip TLP bonded to a copper metalized silicon nitride substrate were made using several different values of fabrication parameters such as gold and indium thickness, Au–In ratio, and bonding pressure. The TLP bonds were then characterized for die-attach voiding, shear strength, and thermal impedance. It was found that TLP die-attach offers high average shear force strength of 22.0 kgf and a low average thermal impedance of 0.35 K/W from the device junction to the substrate. The influence of various fabrication parameters on the bond characteristics were also compared, providing information necessary for implementing TLP die-attach into power electronic modules for high-temperature applications. The outcome of the investigation on TLP bonding techniques was incorporated into a new power module design utilizing TLP bonding. A full half-bridge inverter power module for low-power space applications has been designed and analyzed with extensive finite element thermo-mechanical modeling. In summary, TLP die-attach has investigated to confirm its reliability and to understand how to design effective TLP bonds, this information has been used to design a new high-temperature power electronic module.
Ph.D.
Doctorate
Electrical Engineering and Computer Science
Engineering and Computer Science
Electrical Engineering

Ce mémoire traite de la simulation et de la conception du transistor VDMOS de puissance. On propose un outil de conception de modèles pour ce transistor, qui est base d'une part sur l'analyse des mécanismes dont la structure est le siège, d'autre part sur la géométrie (layout) et la technologie, et enfin sur la prise en compte de la topologie d'un schéma équivalent établi antérieurement au laboratoire. Plus précisément, on effectue tout d'abord une étude des mécanismes-conduction, tenue en tension, étude dynamique-intervenant dans les diverses zones de la structure du composant. En se basant sur les aspects de modélisation antérieurement développes au LAAS, nous proposons ensuite une nouvelle méthodologie de conception des modèles VDMOS. Celle-ci prend en compte les équations de fonctionnement, le dessin des masques, la technologie et les lois de dépendance entre les paramètres. Pour ce faire, nous développons un logiciel nomme power mosfet's designer qui permet à partir des données de la physique, de la géométrie et de la technologie de la structure, de générer le modèle VDMOS et de connaitre les performances électriques du dispositif dans une application de circuit spécifiée a priori. On procède ensuite à la validation de ce logiciel sur des composants industriels. On l'applique à l'étude de nouvelles générations de structures VDMOS telles que le transistor VDMOS à double niveau d'oxyde de grille intercellulaire. Un exemple d'analyse spéculative du transistor VDMOS élaboré sur un autre matériau que le silicium est enfin proposé : on étudie le cas où le substrat est en carbure de silicium (sic)