Дисертації з теми "Semiconductor invertor"

Die vorliegende Arbeit befasst sich mit der Entwicklung, Herstellung und Untersuchung von ZnO-basierten Feldeffekttransistoren (FET). Dabei werden im ersten Teil Eigenschaften von ein- und mehrschichtigen Isolatoren mit hohen Dielektrizitätskonstanten betrachtet, die mittels gepulster Laserabscheidung (PLD) dargestellt wurden. Die elektrischen und kapazitiven Eigenschaften dieser Isolatoren innerhalb von Metall-Isolator-Metall (MIM) bzw. Metall-Isolator-Halbleiter (MIS) Übergängen wurden untersucht. Letzterer wurde schließlich als Gate-Struktur in Metall-Isolator-Halbleiter-FET (MISFET) mit unten (backgate) bzw. oben liegendem Gate (topgate) genutzt. Der zweite Teil konzentriert sich auf Metal-Halbleiter-FET (MESFET), die einen Schottky-Kontakt alsGate nutzen. Dieser wurde mittels reaktiver Kathodenzerstäubung (Sputtern) von Ag, Pt, Pd oder Au unter Einflußvon Sauerstoff hergestellt. ZnO-MESFET stellen eine vielversprechende Alternative zu den bisher in der Oxid-basierten Elektronik verwendeten MISFET dar. Durch die Variation des verwendeten Gate-Metalls, Dotierung, Dicke und Struktur des Kanals und Kontakstruktur, wurde ein Herstellungsstandard gefunden, der zu weiteren Untersuchungen herangezogen wurde. So wurde die Degradation der MESFET unter Belastung durch dauerhaft angelegte Spannung, Einfluss von Licht und erhöhten Temperaturen sowie lange Lagerung getestet. Weiterhin wurden ZnO-MESFET auf industriell genutztem Glasssubstrat hergestellt und untersucht, um die Möglichkeit einer großflächigen Anwendung in Anzeigeelementen aufzuzeigen. Einfache integrierte Schaltungen, wie Inverter und ein NOR-Gatter, wurden realisiert. Dazu wurden Inverter mit sogenannten Pegelschiebern verwendet, welche die Ausgangsspannung des Inverters so verschieben, dass eine logische Aneinanderreihungvon Invertern möglich wird. Schließlich wurden volltransparente MESFET und Inverter, basierend auf neuartigen transparenten gleichrichtenden Kontakten demonstriert.

Thesis (Masters Diploma (Electrical Engineering)--Cape Technikon, Cape Town,1991
A detailed study into the development of a three phase motor drive, inverter and microprocessor controller using a scalar control method. No mathematical modelling of the system was done as the drive was built around available technology. The inverter circuit is of a Vo~tage source inverter configuration whicp uses MOSFETs switching at a base frequency of between 1.2 KHz and 2 KHz. Provision has been made for speed control and dynamic braking for special applications, since the drive is not going to be put into a specific application as yet, it was felt that only a basic control should be implemented and space should be left for special requests from prospective customers. The pulses for the inverter are generated from the HEF 4752 I.e. under the control of the micro processor thus giving the processor full control over the inverter and allowing it to change almost any parameter at any time. Although the report might seem to cover a lot of unimportant ground it is imperative that the reader is supplied with the back-ground information in order to understand where A.e. drives failed in the past and where A.e. drives are heading in the future. As well as where this drive seeks to use available technology to the best advantage.

Thèse Ecole polytechnique fédérale de Lausanne EPFL, no 4145 (2008), Faculté des sciences de base SB, Programme doctoral Physique, Institut de photonique et d'électronique quantiques IPEQ (Laboratoire de physique des nanostructures LPN). Dir.: Elyahou Kapon.

Els avenços en les tecnologies d'energia renovable encara permeten obtenir bons rendiments amb un cost menor que els preus dels combustibles fòssils. L'energia fotovoltaica (cèl·lules solars) és la tecnologia d'energia solar més desenvolupada pel fet que converteix directament l'energia de la llum solar en electricitat. Les cèl·lules solars orgàniques basades en polímers: materials de fullerne (PSC) es consideren una font d'energia prometedora de baix cost. Avui dia, els PSC han d'exhibir alta eficiència, llarga vida útil, fabricació de baix cost i qualitats amigables amb el medi ambient per a la seva comercialització a gran escala. Aquí es va descriure la fabricació, el modelatge i la caracterització de cèl·lules solars orgàniques basades en polímers amb arquitectura invertida (iPSCs). La tesi se centra en l'estudi de la millora simultània de l'eficiència i l'estabilitat a llarg termini dels iPSCs basats en polímers: fullerens. Els polímers PTB7 i PTB7-Th es van usar com materials donants d'electrons, mentre que el fullereno PC70BM es va usar com a acceptor d'electrons. Es van usar òxid de zinc (ZnO) i òxid de titani (TiOx) com capes de transport d'electrons (ETL), a més es va usar PFN per a propòsits de comparació. Tots els dispositius iPSC es van caracteritzar per mètodes òptics, elèctrics i fotofísics per tal de comprendre els mecanismes de pèrdua involucrats en el procés de degradació. Es van usar models de circuits equivalents per analitzar les característiques de J-V en la foscor i es van usar dades d'impedància espectroscòpica per identificar l'origen dels mecanismes de pèrdua. En aquesta tesi es van demostrar cèl·lules solars orgàniques d'alta eficiència i estables basades en PTB7: PC70BM i PTB7-Th: PC70BM amb arquitectura invertida. A més, el TiOx utilitzat com a capa de transport d'electrons és crucial per millorar l'eficiència i l'estabilitat dels iPSCs. Finalment, també es va demostrar que les capes de ZnO dipositades mitjançant impressió per raig de tinta es poden aplicar amb èxit a la fabricació de iPSCs d'alta eficiència a escala de laboratori.
Los avances en tecnologías de energía renovable permiten obtener buenos rendimientos con un costo menor que los precios de los combustibles fósiles. La fotovoltaica es la tecnología de energía solar más desarrollada debido a que convierte directamente la energía de la luz solar en electricidad. Las células solares orgánicas basadas en polímeros: materiales de fullereno (PSC) se consideran una fuente de energía prometedora de bajo costo. Hoy en día, PSC deben exhibir alta eficiencia, larga vida útil, fabricación de bajo costo y cualidades amigables con el medio ambiente para su comercialización a gran escala. Aquí se describió la fabricación,modelado y caracterización de células solares orgánicas basadas en polímeros con arquitectura invertida (iPSCs). La tesis se centra en el estudio de mejoras simultáneas de la eficiencia y estabilidad a largo plazo de iPSCs basados en polímeros: fullerenos. Los polímeros PTB7 y PTB7-Th se usaron como materiales donantes de electrones, mientras que el PC70BM se usó como aceptor de electrones. Se usaron óxido de zinc (ZnO) y titanio (TiOx) como capas de transporte de electrones (ETL), además se usó PFN para propósitos de comparación. Todos los dispositivos iPSC se caracterizaron por métodos ópticos, eléctricos y fotofísicos con el fin de comprender mecanismos de pérdida involucrados en el proceso de degradación. Se usaron modelos de circuitos equivalentes para analizar las características de J-V en oscuridad y se usaron datos de impedancia espectroscópica para identificar el origen de los mecanismos de pérdida. En esta tesis se demostraron células solares orgánicas de alta eficiencia estables basadas en PTB7: PC70BM y PTB7-Th: PC70BM con arquitectura invertida. Además, TiOx utilizado como capa transportadora de electrones crucial para mejorar la eficiencia y la estabilidad de los iPSCs. Finalmente, también se demostró que las capas de ZnO depositadas mediante impresión por chorro de tinta se pueden aplicar con éxito para fabricación de iPSCs de alta eficiencia a escala de laboratorio.
The advances on the renewable energy technologies still allow obtaining good performances with lower cost than fossil fuel prices. Photovoltaics (solar cells) is the most developed solar energy technology due to converts directly the sunlight energy into electricity. The organic solar cells based on polymer:fullerne materials (PSCs) are considered as a promising low-cost energy source. Nowadays, the PSCs must exhibit high efficiency, long lifetime, low-cost fabrication, and environmentally friendly qualities for their large-scale commercialization. Herein the fabrication, modelling and characterization of polymer-based organic solar cells with inverted architecture (iPSCs) were described. The thesis focuses on the study of the simultaneous improvement of efficiency and long-term stability of iPSCs based on polymer:fullerenes. The polymers PTB7 and PTB7-Th were used as electron donor materials, whereas the fullerene PC70BM was used as the electron acceptor. Zinc oxide (ZnO) and titanium oxide (TiOx) were used as electron transport layers (ETL), moreover PFN was used for comparison purposes. All iPSC devices were characterized by optical, electrical and photophysical methods in order to understand the loss mechanisms involved in the degradation process. Equivalent circuit models were used to analyze the J-V characteristics in the dark and impedance spectroscopy data was used to identify the origin of the loss mechanisms. High efficient and stable organic solar cells based on PTB7:PC70BM and PTB7-Th:PC70BM with inverted architecture were demonstrated in this thesis. Moreover, TiOx used as an electron transport layer is crucial for improving the efficiency and the stability of iPSCs. Finally, it was also demonstrated that ZnO layers deposited by inkjet printing can be successfully applied to the fabrication of high efficiency iPSCs at laboratory scale.

Ion sensitive field effect transistors (ISFETs) have long been used as analogue chemical sensors particularly for biomedical applications. However, there are some applications where a "yes" / "no" type answer regarding pH change is sufficient. For example, in DNA sequencing the question is whether a chain extension reaction took place or not. Detecting this at the sensing point reduces the sensing process to pH change threshold detection. It eliminates the need for analogue to digital conversion and facilitates an all digital sensory system. This thesis presents Novel Floating Gate ISFET based Chemical Inverters that were created with semiconductor based biomedical applications in mind. It starts by allowing two ISFETs to share the same ion sensing membrane and a common floating gate. Arranging them in a simple FG inverter configuration, their switching may be triggered by either the reference voltage or chemical pH change. In order to enhance its input noise immunity, a chemical Schmitt Trigger is presented. Using ISFETs for the detection of minute pH changes have been a challenge. A simple method to locally scale input referred chemical signal at the ISFET's floating gate is presented. It is based on using the ratio of capacitive coupling to the floating gate. The chemical signal is coupled via the passivation capacitance (Cpass) while an electrical input (V2) is coupled via a poly capacitance (C2). V2 sees the chemical signal with a scaling of Cpass/C2, which can be designed. Finally, ISFETs suffer from initial trapped charges that cause mismatch between devices in the same die. A fast matching method is presented here, that can be used to hugely reduce mismatch of arrays of FG devices. It is based on using indirect bidirectional tunnelling. Two tunnelling structures are added to each ISFET's FG, one adds electrons to it while the other removes them. It is possible to match all ISFETs' initial FG voltages to a point where both tunnelling currents reach equilibrium.

A DC to AC inverter can be classified in different topologies; some of these topologies are three level and multilevel inverter. Both types have some advantages and disadvantages. Three level inverters can be applied for low power applications because it is cheaper and has less semiconductor losses at high switching frequencies with poor total harmonic distortion (THD). Multilevel inverters (MLI) can be applied for higher power applications with less THD. However, the MLI has more cost and conductive power losses in comparison with three level inverters. In order to overcome the limitations of three and multilevel topologies, this thesis presents a new controlling topology of multilevel DC/AC inverters. The proposed multilevel inverter topology is based on a current source inverter, which consists of a buck/boost, boost and flyback converters, and an H-bridge inverter. The output voltage of the inverter is shaped through the control of just one main semiconductor switch. This new topology offers almost step-less output voltage without the need for multi DC source or several capacitor banks as in the case of other multilevel inverter topologies. The efficiency of the proposed topology is higher than other inverter topologies for medium power applications (2-10 kW). The proposed topology also generates smaller Total Harmonic Distortion (THD) compared to other inverter topologies. The two main key aspects of the proposed circuit is to keep the switching losses as low as possible and this is achieved through the control of a single switch at relatively low frequency and also to generate an improved AC Voltage waveform without the need for any filtering devices. The output frequency and voltage of the proposed circuit can be easily controlled according to the load requirements. The proposed inverter topology is ideal for the connection of renewable energy; this is due to its flexibility in varying its output voltage without the need of fixed turns-ratio transformers used in existing DC/AC inverter topologies. The harmonic contents of the output of this proposed topology can be controlled without the need of any filter. The simulation and practical implementation of the proposed circuits are presented. The practical and simulation results show excellent correlation.

This study focuses on the investigation of the key parameters that determine the optical and electrical characteristics of inverted top-emitting organic light emitting diodes (OLED). A co-deposition of small molecules in vacuum is used to establish electrically doped films that are applied in n-i-p layered devices. The knowledge about the functionality of each layer and parameter is important to develop efficient strategies to reach outstanding device performances. In the first part, the thin film optics of top-emitting OLEDs are investigated, focusing on light extraction via cavity tuning, external outcoupling layers (capping layer), and the application of microlens films. Optical simulations are performed to determine the layer configuration with the maximum light extraction efficiency for monochrome phosphorescent devices. The peak efficiency is found at 35%, while varying the thickness of the charge transport layers, the semitransparent anode, and the capping layer simultaneously. Measurements of the spatial light distribution validate, that the capping layer influences the spectral width and the resonance wavelength of the extracted cavity mode, especially for TM polarization. Further, laminated microlens films are applied to benefit from strong microcavity effects in stacked OLEDs by spatial mixing of external and to some extend internal light modes. These findings are used to demonstrate white top-emitting OLEDs on opaque substrates showing power conversion efficiencies up to 30 lm/W and a color rendering index of 93, respectively. In the second part, the charge carrier management of n-i-p layered diodes is investigated as it strongly deviates from that of the p-i-n layered counterparts. The influence of the bottom cathode material and the electron transport layer is found to be negligible in terms of driving voltage, which means that the assumption of an ohmic bottom contact is valid. The hole transport and the charge carrier injection at the anode is much more sensitive to the evaporation sequence, especially when using hole transport materials with a glass transition temperature below 100°C. As a consequence, thermal annealing of fabricated inverted OLEDs is found to drastically improve the device electronics, resulting in lower driving voltages and an increased internal efficiency. The annealing effect on charge transport comes from a reduced charge accumulation due to an altered film morphology of the transport layers, which is proven for electrons and for holes independently. The thermal treatment can further lead to a device degradation. Finally, the thickness and the material of the blocking layers which usually control the charge confinement inside the OLED are found to influence the recombination much more effectively in inverted OLEDs compared to non-inverted ones.

Ingeniero Civil Electricista
El presente trabajo aborda los conceptos básicos, sobre electrónica, semiconductores de potencia, controladores digitales de señales y software de simulación en electrónica de potencia, para lograr diseñar y construir un inversor MPPT fotovoltaico de 2kW de potencia nominal que sirva como base para desarrollos en esta área. Se presenta una introducción al tema, los objetivos de la memoria y una breve descripción del estado del arte, conocimientos necesarios para desarrollar un equipo de estas características. En función de estos antecedentes se presenta el diseño y simulación de la primera etapa de conversión, correspondiente al módulo Boost, utilizado para realizar un seguimiento de máxima potencia al sistema fotovoltaico. A continuación, se muestra la segunda etapa de conversión, de corriente continua a alterna, mediante un puente inversor completo. Se diseñan los sensores a utilizar, que son de voltaje DC, voltaje AC, corriente y temperatura. Se presenta el diseño de las etapas necesarias de control realimentado, que se programan en un microcontrolador. Esta etapa incluye la determinación de la tensión de máxima transferencia, se sincroniza el inversor con la red y se limita el trabajo del equipo dentro de rangos seguros de operación. Con el software PSim, se simula cada etapa de conversión de potencia, lo que permite realizar un diseño rápido y seguro. Se logra probar los ciclos de control diseñados para el sistema y ver el tipo de comportamiento ante perturbaciones. Se presenta en detalle la fase de construcción de cada uno de los módulos diseñados, reportando los planos, dispositivos y elementos de integración. Se realizan pruebas de potencia para el módulo Boost y el Inversor, ajustando los sensores. Por último se realizan pruebas de control realimentado como seguidor de tensión y seguidor de fase. Se finaliza con los resultados de las características relevantes del equipo, como lo son la eficiencia (80%) y costo de construcción estimado ($1466 US), para luego realizar un análisis de recuperación del capital en base a la energía generada. Como trabajo futuro se requiere de las pruebas de inyección de potencia a la red y de transferencia de máxima potencia conectando un panel fotovoltaico como fuente primaria de energía.

Over the last few decades, bulk-heterojunction organic photovoltaic devices comprising an intimately mixed donor-acceptor blend have gained serious attention due to their potential for being cheap, light weight, flexible and environmentally friendly. In this thesis, APFO-3/PCBM bulk-heterojunction based organic photovoltaic devices with an inverted layer sequence were investigated systematically. Doctor blade coating is a technique that is roll-to-roll compatible and cost efficient and has been used to fabricate the solar cells.

Initial studies focused on optimization of the electrodes. A thin film of the conductive polymer PEDOT:PSS was chosen to be the transparent anode. Different PEDOT:PSS films with respect to the film thickness and deposition temperature were characterized in terms of conductivity and transmission. Decent conductance and transmittance were obtained in the films deposited with wet film thickness setting of 35 μm, The cathode was fabricated from a metal bilayer comprising Al and Ti with an area about 1 cm², and the best-working cathodes contained a 70 nm thick Al layer covered by a thin Ti layer of about 10 -15 nm.

Optimized coating temperature and wet film thickness settings for the active layer and PEDOT:PSS layer were experimentally determined. The highest efficiency of the APFO-3/PCBM based inverted solar cells fabricated by doctor blading was 0.69%, which exceeded the efficiency of spin-coated inverted cells.

A higher efficiency (0.8 %) was achieved by adding a small amount of high molecular weight polystyrene to the active layer. Morphological changes after adding of the polystyrene were observed by optical microscopy and AFM. A coating temperature dependent phase separation of the APFO-3/PCBM/polystyrene blend was found.

 

Thin-film transistors (TFTs) capable of low-voltage and high-frequency operation will be required to reduce the power consumption of next generation electronic devices driven by microelectronic components such as inverters, ring oscillators, and backplane circuits for mobile displays. To produce high performance TFTs, transparent oxide-semiconductors are becoming an attractive alternative to hydrogenated amorphous silicon (a-Si:H)- and organic-based materials because of their high electron mobility vlaues and low processing temperatures, making them compatible with flexible substrates and opening the potential for low production costs. Practical electronic devices are expected to use p- and n-channel TFT-based complementary inverters to operate with low power consumption, high gain values, and high and balanced noise margins. The p- and n-channel TFTs should yield comparable output characteristics despite differences in the materials used to achieve such performance. However, most oxide semiconductors are n-type, and the only high performance, oxide-based TFTs demonstrated so far are all n-channel, which prevents the realization of complementary metal-oxide-semiconductor (CMOS) technologies. On the other hand, ambipolar TFTs are very attractive microelectronic devices because, unlike unipolar transistors, they operate independently of the polarity of the gate voltage. This intrinsic property of ambipolar TFTs has the potential to lead to new paradigms in the design of analog and digital circuits. To date, ambipolar TFTs and their circuits, such as inverters, have shown very limited performance when compared with that obtained in unipolar TFTs. For instance, the electron and hole mobilities typically found in ambipolar TFTs (ATFTs) are, typically, at least an order of magnitude smaller than those found in unipolar TFTs. Furthermore, for a variety of circuits, ATFTs should provide balanced currents during p- and n-channel operations. Regardless of the selection of materials, achieving these basic transistor properties is a very challenging task with the use of current device geometries. This dissertation presents research work performed on oxide TFTs, oxide TFT-based electronic circuits, organic-inorganic hybrid complementary inverters, organic-inorganic hybrid ambipolar TFTs, and ambipolar TFT-based complementary-like inverters in an attempt to overcome some of the current issues. The research performed first was to develop low-voltage and high-performance oxide TFTs, with an emphasis on n-channel oxide TFTs, using high-k and/or thin dielectrics as gate insulators. A high mobility electron transporting semiconductor, amorphous indium gallium zinc oxide (a-IGZO), was used as the n-channel active material. Such oxide TFTs were employed to demonstrate active matrix organic light emitting diode (AMOLED) display backplane circuits operating at low voltage. Then, high-performance hybrid complementary inverters were developed using unipolar TFTs employing organic and inorganic semiconductors as p- and n-channel layers, respectively. An inorganic a-IGZO and pentacene, a widely used organic semiconductor, were used as the n- and p-channel semiconductors, respectively. By the integration of the p-channel organic and n-channel inorganic TFTs, high-gain complementary inverters with high and balanced noise margins were developed. A new approach to find the switching threshold voltage and the optimum value of the supply voltage to operate a complementary inverter was also proposed. Furthermore, we proposed a co-planar channel geometry for the realization of high-performance ambipolar TFTs. Using non-overlapping horizontal channels of pentacene and a-IGZO, we demonstrate hybrid organic-inorganic ambipolar TFTs with channels that show electrical properties comparable to those found in unipolar TFTs with the same channel aspect ratios. A key characteristic of this co-planar channel ambipolar TFT geometry is that the onset of ambipolar operation is mediated by a new operating regime where one of the channels can reach saturation while the other channel remains off. This allows these ambipolar TFTs to reach high on-off current ratios approaching 104. With the new design flexibility we demonstrated organic-inorganic hybrid ambipolar TFT-based complementary-like inverters, on rigid and flexible substrates, that show a significant improvement over the performance found in previously reported complementary-like inverters. From a materials perspective, this work shows that future breakthroughs in the performance of unipolar n-channel and p-channel semiconductors could be directly transposed into ambipolar transistors and circuits. Hence, we expect that this geometry will provide new strategies for the realization of high-performance ambipolar TFTs and novel ambipolar microelectronic circuits.

Solar energy is an abundant renewable source, which is expected to play an increasing role in the grid's future infrastructure for distributed generation. The research described in the thesis focuses on the analysis of integrating multi-megawatt photovoltaics (PV) systems with battery energy storage into the existing grid and on the theory supporting the electrical operation of components and systems. The PV system is divided into several sections, each having its own DC-DC converter for maximum power point tracking and a two-level grid connected inverter with different control strategies. The functions of the battery are explored by connecting it to the system in order to prevent possible voltage fluctuations and as a buffer storage in order to eliminate the power mismatch between PV array generation and load demand. Computer models of the system are developed and implemented using the PSCADTM/EMTDCTM software.

Ces dernières années, l’utilisation des systèmes de transport aérien s'est considérablement amplifié. Par conséquent, les considérations environnementales actuelles poussent à réduire leur utilisation. Des projets tels que Clean Sky 2 tentent d’apporter une réponse à ce problème, en proposant une réduction des émissions de CO2 et des nuisances sonores. Le recours à l’hybridation de la propulsion des avions réduirait ces émissions en réduisant la taille et la masse des systèmes et en utilisant des systèmes électriques plus efficaces ce qui permettrai d’augmenter le nombre de passager. Cela permettrait de réduire la consommation de carburant et donc les émissions polluantes. Ces travaux s'inscrivent dans le cadre du projet européen HASTECS Clean Sky 2 qui vise à optimiser l'ensemble de la chaîne électrique de l'avion à propulsion hybride en intégrant toutes les contraintes aéronautiques telles que les décharges partielles pour les équipements électriques placés en zone non pressurisée. Le projet HASTECS s'est fixé le défi de doubler la densité de puissance des machines électriques pour passer de 5 kW/kg à 10 kW/kg, y compris leur refroidissement, tandis que pour l'électronique de puissance, avec son système de refroidissement, le but sera de passer à 15 kW/kg en 2025 et à 25 kW/kg en 2035. Pour augmenter la densité de puissance, la masse du système de refroidissement doit être diminuée dans un premier temps soit en optimisant ses composants, ce qui est fait par le 4ème lot de travail (WP4), soit en réduisant les pertes. La réduction des pertes de l'onduleur pourrait être obtenue en utilisant de semi-conducteurs de faible calibre en tension, en jouant sur les stratégies de modulation ou en utilisant des semi-conducteurs plus performants. La première option peut être faite en utilisant des architectures multi-niveaux pour éviter l'association en série direct. Contrairement à l'association directe en série, l'association parallèle est plus facile à gérer en termes de commande de interrupteurs, ce qui a été autorisé dans nos études. Plusieurs topologies d'onduleurs (topologies à 2, 3 et 5 niveaux) et stratégies de modulation (PWM, injection de troisième harmonique, PWM discontinu et pleine onde) ont été comparées en utilisant plusieurs technologies de semi-conducteurs pour choisir la solution la plus performante en termes de rendement et de densité de puissance. Pour le profil de mission considéré, l'onduleur pourrait être dimensionné pour le point de puissance maximum (décollage) ou la phase de vol la plus longue (croisière). Une étude comparative des stratégies de modulation a été réalisée pour mettre en évidence la structure et la modulation présentant les meilleures performances afin de minimiser les pertes pour les points de dimensionnement choisis en utilisant les topologies les plus intéressantes pour le profil de mission étudié en utilisant deux configurations différentes de bobinage du moteur électrique proposées par le WP1
Recently, the use of air transport systems has increased considerably. Therefore, the current environmental considerations are pushing to reduce their ecological impact. Projects such as Clean Sky 2 provide an answer to this problem, by proposing a reduction in CO2 emissions and noise pollution. The development of a hybrid-electric aircraft would reduce these emissions by reducing the size and weight of the systems and using more efficient electrical systems. This would reduce fuel consumption and therefore pollutant emissions. This work takes part into HASTECS Clean Sky 2 European project which aims to optimize the complete electrical chain of the hybrid aircraft integrating all aeronautical constraints such as partial discharges for electrical equipment placed in the non-pressurized zone. HASTECS project has set itself the challenge of doubling the specific power of electric machines including their cooling from 5 kW/kg to 10 kW/kg, while the power electronics, with their cooling system, would evolve from 15 kW/kg in 2025 to 25 kW/kg in 2035. To increase the specific power, the cooling system mass should be decreased either by optimizing its components which is done by the 4th work package (WP4) or by reducing power losses. Inverter losses reduction could be achieved by using small voltage rating components, by playing on modulation strategies or by using more performant semiconductors. The first option could be done by using multilevel architectures to avoid the direct series association. Unlike direct series association, the parallel one is easier to manage in terms of switches command so it was allowed in our studies. Several inverter topologies (2-, 3- and 5-level topologies) and modulation strategies (PWM, third harmonic injection, discontinuous PWM and full-wave) were compared using several semiconductors generations to choose the most performant solution in terms of efficiency and specific power. For the considered mission profile, the inverter could be sized for the maximum power point (takeoff) or the most extended flight phase (cruise). A comparative study of modulation strategies was carried out to highlight the structure and modulation presenting the best performance to minimize the losses for the chosen sizing points using most interesting topologies for the studied mission profile using two electrical motor windings configurations proposed by WP1

Die enorme Steigerung der Leistungsfähigkeit integrierter Schaltkreise wird seit über 50 Jahren im Wesentlichen durch eine Verkleinerung der Bauelementdimensionen erzielt. Aufgrund des Erreichens physikalischer Grenzen kann dieser Trend, unabhängig von der Lösung technologischer Probleme, langfristig nicht fortgesetzt werden. Diese Arbeit beschäftigt sich mit der Entwicklung und Herstellung neuartiger Transistoren und Schaltungen, welche im Vergleich zu konventionellen Bauelementen funktionserweitert sind, wodurch ein zur Skalierung alternativer Ansatz vorgestellt wird. Ausgehend von gewachsenen und nominell undotierten Silizium-Nanodrähten wird die Herstellung von Schottky-Barrieren-Feldeffekttransistoren (SBFETs) mit Hilfe etablierter und selbst entwickelter Methoden beschrieben und die Ladungsträgerinjektion unter dem Einfluss elektrischer Felder an den dabei erzeugten abrupten Metall–Halbleiter-Grenzflächen analysiert. Zur Optimierung der Injektionsvorgänge dienen strukturelle Modifikationen, welche zu erhöhten ambipolaren Strömen und einer vernachlässigbaren Hysterese der SBFETs führen. Mit dem rekonfigurierbaren Feldeffekttransistor (RFET) konnte ein Bauelement erzeugt werden, bei dem sich Elektronen- und Löcherinjektion unabhängig und bis zu neun Größenordnungen modulieren lassen. Getrennte Topgate-Elektroden über den Schottkybarrieren ermöglichen dabei die reversible Konfiguration von unipolarer Elektronenleitung (n-Typ) zu Löcherleitung (p-Typ) durch eine Programmierspannung, wodurch die Funktionen konventioneller FETs in einem universellen Bauelement vereint werden. Messungen und 3D-FEM-Simulationen geben einen detaillierten Einblick in den elektrischen Transport und dienen der anschaulichen Beschreibung der Funktionsweise. Systematische Untersuchungen zu Änderungen im Transistoraufbau, den Abmessungen und der Materialzusammensetzung verdeutlichen, dass zusätzliche Strukturverkleinerungen sowie die Verwendung von Halbleitern mit niedrigem Bandabstand die elektrische Charakteristik dieser Transistoren weiter verbessern. Im Hinblick auf die Realisierung neuartiger Schaltungen wird ein Konzept beschrieben, die funktionserweiterten Transistoren in einer energieeffizienten Komplementärtechnologie (CMOS) nutzbar zu machen. Die dafür notwendigen gleichen Elektronen- und Löcherstromdichten konnten durch einen modifizierten Ladungsträgertunnelprozess infolge mechanischer Verspannungen an den Schottkyübergängen erzielt und weltweit erstmalig an einem Transistor gezeigt werden. Der aus einem <110>-Nanodraht mit 12 nm Si-Kerndurchmesser erzeugte elektrisch symmetrische RFET weist dabei eine bisher einzigartige Kennliniensymmetrie auf.Die technische Umsetzung des Schaltungskonzepts erfolgt durch die Integration zweier RFETs innerhalb eines Nanodrahts zum dotierstofffreien CMOS-Inverter, der flexibel programmiert werden kann. Die rekonfigurierbare NAND/NOR- Schaltung verdeutlicht, dass durch die RFET-Technologie die Bauelementanzahl reduziert und die Funktionalität des Systems im Vergleich zu herkömmlichen Schaltungen erhöht werden kann. Ferner werden weitere Schaltungsbeispiele sowie die technologischen Herausforderungen einer industriellen Umsetzung des Konzeptes diskutiert. Mit der funktionserweiterten, dotierstofffreien RFET-Technologie wird ein neuartiger Ansatz beschrieben, den technischen Fortschritt der Elektronik nach dem erwarteten Ende der klassischen Skalierung zu ermöglichen
The enormous increase in performance of integrated circuits has been driven for more than 50 years, mainly by reducing the device dimensions. This trend cannot continue in the long term due to physical limits being reached. The scope of this thesis is the development and fabrication of novel kinds of transistors and circuits that provide higher functionality compared to the classical devices, thus introducing an alternative approach to scaling. The fabrication of Schottky barrier field effect transistors (SBFETs) based on nominally undoped grown silicon nanowires using established and developed techniques is described. Further the charge carrier injection in the fabricated metal to semiconductor interfaces is analyzed under the influence of electrical fields. Structural modifications are used to optimize the charge injection resulting in increased ambipolar currents and negligible hysteresis of the SBFETs. Moreover, a device has been developed called the reconfigurable field-effect transistor (RFET), in which the electron and hole injection can be independently controlled by up to nine orders of magnitude. This device can be reversibly configured from unipolar electron conducting (ntype) to hole conducting (p-type) by the application of a program voltage to the two individual top gate electrodes at the Schottky junctions. So the RFET merges the functionality of classical FETs into one universal device. Measurements and 3D finite element method simulations are used to analyze the electrical transport and to describe the operation principle. Systematic investigations of changes in the device structure, dimensions and material composition show enhanced characteristics in scaled and low bandgap semiconductor RFET devices. For the realization of novel circuits, a concept is described to use the enhanced functionality of the transistors in order to realize energy efficient complementary circuits (CMOS). The required equal electron and hole current densities are achieved by the modification of charge carrier tunneling due to mechanical stress and are shown for the first time ever on a transistor. An electrically symmetric RFET based on a compressive strained nanowire in <110> crystal direction and 12 nm silicon core diameter exhibits unique electrical symmetry. The circuit concept is demonstrated by the integration of two RFETs on a single nanowire, thus realizing a dopant free CMOS inverter which can be programmed flexibly. The reconfigurable NAND/NOR shows that the RFET technology can lead to a reduction of the transistor count and can increase the system functionality. Additionally, further circuit examples and the challenges of an industrial implementation of the concept are discussed.The enhanced functionality and dopant free RFET technology describes a novel approach to maintain the technological progress in electronics after the expected end of classical device scaling

Die vorliegende Arbeit befasst sich mit einem detaillierten Vergleich von Mehrpunkt-Schaltungstopologien mit zentralem Gleichspannungszwischenkreis für den Einsatz in Mittelspannungsanwendungen. Im Rahmen dieser Untersuchungen wird die 3-Level Neutral Point Clamped Spannungswechselrichter Schaltungstopologie (3L-NPC VSC) sowohl mit Multilevel Flying Capacitor (FLC) als auch mit Multilevel Stacked Multicell (SMC) Schaltungstopologien verglichen, wobei unter Verwendung von aktuell verfügbaren IGBT-Modulen Stromrichterausgangsspannungen von 2.3 kV, 4.16 kV und 6.6 kV betrachtet werden. Neben der grundlegenden Funktionsweise wird die Auslegung der aktiven Leistungshalbleiter und der passiven Energiespeicher (Zwischenkreiskondensatoren, Flying Capacitors) für die untersuchten Stromrichtertopologien dargestellt. Unter Berücksichtigung verschiedener Modulationsverfahren und Schaltfrequenzen werden Kennwerte für den Oberschwingungsgehalt in der Ausgangsspannung und dem Ausgangsstrom vergleichend evaluiert. Die installierte Schalterleistungen, die Halbleiterausnutzungsfaktoren, die Stromrichterverlustleistungen sowie die Verlustleistungsverteilungen werden für die betrachteten Stromrichtertopologien detailliert gegenübergestellt und bewertet
The thesis deals with a detailed comparison of voltage source converter topologies with a central dc-link energy storage device for medium voltage applications. The Three-Level Neutral Point Clamped Voltage Source Converter (3L-NPC VSC) is compared with multilevel Flying Capacitor (FLC) and Stacked Multicell (SMC) Voltage Source Converters (VSC) for output voltages of 2.3 kV, 4.16 kV and 6.6 kV by using state-of-the-art 6.5 kV, 3.3 kV, 4.5 kV and 1.7kV IGBTs. The fundamental functionality of the investigated converter topologies as well as the design of the power semiconductors and of the energy storage devices (Flying Capacitors and Dc-Link capacitors) is described. The installed switch power, converter losses, the semiconductor loss distribution, modulation strategies and the harmonic spectra are compared in detail

碩士
國立臺灣大學
電子工程學研究所
98
Organic photovoltaic devices are very attractive for their advantages of flexibility, light-weight, and large-area production at a dramatically low cost. In this study, the PV2000 material is used as a photoactive layer, which has a larger relative energy difference between the HOMO level of the electron-donating polymer and the LUMO level of the electron acceptor (energy difference ~1.7 eV) as compared to the standard P3HT:PCBM system, thereby leading to a larger VOC. The better contact in the interface is achieved by the post-annealing process, which corrects the defects between electrode and polymer layer interface. Moreover, the thermally induced morphology modification, crystallization and improved interfacial transportation, thereby leading to better charge collection and reduced series resistance. These results show that the process of post-annealing is very important for our PV2000 inverted device. We used solution process to replace deposition to spin NiO layer on active layer. NiO layer acts as an interfacial electron-blocking layer/hole-transporting layer (EBL/HTL). Utilizing its higher LUMO (lowest unoccupied molecular orbital) could block electron leakage to anode to recombine with hole. The leakage current is reduced to improve the power conversion efficiency of inverted structure devices. When the TiO2 nanorods are introduced, an improvement of light harvest and photocurrent is achieved due to several factors. First, the photoactive layer is thickened and the light path is increased to have more light absorption. Second, the morphology is modified to provide the photoactive layer and inorganic layer a larger contact area for efficient charge collection. Third, the TiO2 nanorods enhance the photoluminescence quenching, indicating improved electron-hole dissociation. In this way, the high PCE of 5.61% from inverted PSCs is achieved. In the second part of this work, our investigation apply the low band gap material (ITRI P47:PC70BM) as the photoactive layer. The light harvest is improved by adjusting the thickness of photoactive layer. In addition, we introduce the solution-process NiO layer between photoactive layer and silver as an electron blocking layer, therefore, the electron is forced to move toward the ITO electrodes, increasing the selectivity of the charge carriers and the shunt resistance of the photovoltaic cell.

Amorphous oxide semiconductor (AOS) thin-film transistors (TFTs) constitute the central theme of this thesis. Within this theme, three primary areas of focus are pursued. The first focus is the realization of a transparent three-stage ring oscillator with buffered output and an output frequency in the megahertz range. This leads to the possibility of transparent radio frequency applications, such as transparent RFID tags. At the time of its fabrication, this ring oscillator was the fastest oxide electronics ring oscillator reported, with an output frequency of 2.16 MHz, and a time delay per stage of 77 ns. The second focus is to ascertain whether a three-terminal device (i.e., a TFT) is an appropriate structure for conducting space-charge-limited-current (SCLC) measurements. It is found that it is not appropriate to use a diode-tied or gate-biased TFT configuration for conducting a SCLC assessment since square-law theory shows that transistor action alone gives rise to I proportional to V² characteristics, which can easily be mistakenly attributed to a SCLC mechanism. Instead, a floating gate TFT configuration is recommended for accomplishing SCLC assessment of AOS channel layers. The final focus of this work is to describe an assessment procedure appropriate for determining if a dielectric is suitable for use as a TFT gate insulator. This is accomplished by examining the shape of a MIM capacitor's log(J)-ξ curve, where J is the measured current density and ξ is the applied electric field. An appropriate dielectric for use as a TFT gate insulator will have a log(J)-ξ curve that expresses a clear breakover knee, indicating a high-field conduction mechanism dominated by Fowler-Nordheim tunneling. Such a dielectric produces a TFT with a minimal gate leakage which does not track with the drain current in a log(I[subscript D])-V[subscript GS] transfer curve. An inappropriate dielectric for use as a TFT gate insulator will have a log(J)-ξ curve that does not express a clear breakover knee, indicating that the dominate conduction mechanism is defect driven (i.e., pin-hole like shunt paths) and, therefore, the dielectric is leaky. It is shown that experimental log(J)-ξ leakage curves can be accurately simulated using Ohmic, space-charge-limited current (SCLC), and Fowler-Nordheim tunneling conduction mechanisms.
Graduation date: 2010

Increasing global energy demands and diminishing supplies of conventional fuels are forcing the world to focus more on alternative power sources that are both renewable and ecologically benign. Solar energy is clean, regularly available and can be harvested without sacrificing valuable land space. Due to the associated cost of solar cells, however a very small portion of the world’s energy needs are supplied by the sun. Solution-processable organic photovoltaics (OPVs) offer the promise of lower production costs relative to conventional (silicon) solar cell technology. Solution-processing can be performed using reel-to-reel manufacturing, with printing and coating techniques that are significantly cheaper than current processing methods for inorganic semiconductors. Although OPV efficiency values currently remain inferior to those of conventional solar cells, the rate of improvement is much higher in OPVs than in other solar cell technologies. Recently an efficiency exceeding 10% was reported for organic solar cells. An important difference between organic and conventional solar cells is the charge carrier mobility of the semiconductors, which tends to be relatively low in organic semiconductors. Recent advances in molecular design have led to polymer semiconductor materials that possess hole mobility values similar to that of amorphous silicon. The present study investigates potential improvements in OPV devices that can be achieved through the application of high hole mobility polymer semiconductor donors. Two diketopyrrolopyrrole-based polymers, PDQT and PDBFBT, were selected for the role of electron donor in OPV devices due to their high mobilities and their optimum optical and electrical properties. Optimization of the process parameters was performed using PC61BM as the acceptor. A relatively high quantity of PC61BM (3 - 4 × the weight of the donor) is required in the donor-acceptor blends of both polymers in order to balance the high hole mobility. For these donor-acceptor blends, a solvent system consisting of chloroform/ortho-dichlorobenzene (4:1 v/v) is necessary for proper solubility, and an additive, 1,8-diiodooctane, is required to achieve an acceptable morphology. The main benefit expected from the use of high mobility semiconductors is reduced charge recombination. This was studied in relation to the active layer thickness in standard and inverted OPV devices prepared using PC61BM as the acceptor. Normally the thickness of the active layer is required to be low (~100 nm) due to the poor charge transport mobility of the carriers. In this study, rather consistent power conversion efficiencies were achieved throughout a wide range of active layer thicknesses (~100 nm to ~800 nm). A comparison between standard and inverted device configurations demonstrates that the inverted configuration is more suitable for achieving thicker active layers when a high hole mobility donor is used. This is attributed to the longer hole collection path in the inverted structure, which can benefit from using a high hole mobility material. Increasing the absorption spectra of the donor-acceptor blend was studied by substituting PC71BM for PC61BM. The improved absorption leads to greater charge generation. In PDQT devices, the increase in absorption that is contributed by PC71BM appears to be of greatest benefit when active layers are not very thick. Therefore, when thick active layers (>500 nm) are required, the use of PC61BM is sufficient, in conjunction with a high mobility donor. Finally, an increase in a polymer’s crystallinity can often lead to greater mobility. This can be accomplished through various annealing techniques. The improved crystallinity of PDBFBT that occurs as a result of thermal annealing was studied in OPV applications. Although hole mobility of PDBFBT in the lateral direction improves with thermal annealing, mobility in the vertical direction decreases with increasing temperature. This suggests that the crystallinity of PDBFBT is oriented in the lateral direction as opposed to the vertical direction, thereby directing charge flow horizontal to the surface. With thermal annealing, an optimal amount of PC61BM added to PDBFBT can increase the vertical mobility to fairly high values. Nevertheless, the efficiency of standard and inverted OPV devices decreases with increased annealing temperature. This is attributed to agglomeration of PC61BM that occurs from an increase in annealing temperature. The results of this study demonstrate that thermal annealing is not beneficial for PDBFBT:PC61BM films in OPV applications due to the vertical orientation of devices. All of the studies presented in this work involve the use of high hole mobility polymer semiconductors as donor materials for OPV applications. This work will provide a deeper understanding of the properties required for the development of new semiconductor materials in OPV applications. Furthermore, this work will be very useful for the design of device structures for more feasible manufacturing of large area OPV devices via high speed roll-to-roll printing processes.

博士
國立交通大學
電子物理系所
95
This research is divided into two parts: [1]Electronic structure of organic semiconductor materials – Study of electronic structure of organic semiconductor materials is based on the density functional theory calculations, which includes organic molecular structure, electronic structure of molecular orbital and energy levels and energy gap. The calculated of IR spectra, singlet and triplet gaps and stokes shift of selected materials are found to be in good agreement with the experimental data. This study contributed to the understanding the characteristics of organic semiconductor and the designing of new materials. [2]Inverted bottom-emission OLED (IBOLED) development - Inverted OLED is best suited for the large n-channel TFT active matrix OLED display technology. We have developed one of the most efficient (22 cd/A) green fluorescent IBOLED which is more efficient than that of the conventional OLED. The efficiency levels of the white OLED achieved 13.0 cd/A and 10.6 lm/W. The projected half-lifetime under an initial luminance of 400 cd/m2 is projected to be over 34,000 hours and the Commission International de l’Eclairage (CIE) coordinates are not affected by aging. The development of IBOLED is useful in fabricating AMOLED with high power efficiency and long device stability and is also expected to impact on the future development of low power solid-state lighting.

This study focuses on the investigation of the key parameters that determine the optical and electrical characteristics of inverted top-emitting organic light emitting diodes (OLED). A co-deposition of small molecules in vacuum is used to establish electrically doped films that are applied in n-i-p layered devices. The knowledge about the functionality of each layer and parameter is important to develop efficient strategies to reach outstanding device performances. In the first part, the thin film optics of top-emitting OLEDs are investigated, focusing on light extraction via cavity tuning, external outcoupling layers (capping layer), and the application of microlens films. Optical simulations are performed to determine the layer configuration with the maximum light extraction efficiency for monochrome phosphorescent devices. The peak efficiency is found at 35%, while varying the thickness of the charge transport layers, the semitransparent anode, and the capping layer simultaneously. Measurements of the spatial light distribution validate, that the capping layer influences the spectral width and the resonance wavelength of the extracted cavity mode, especially for TM polarization. Further, laminated microlens films are applied to benefit from strong microcavity effects in stacked OLEDs by spatial mixing of external and to some extend internal light modes. These findings are used to demonstrate white top-emitting OLEDs on opaque substrates showing power conversion efficiencies up to 30 lm/W and a color rendering index of 93, respectively. In the second part, the charge carrier management of n-i-p layered diodes is investigated as it strongly deviates from that of the p-i-n layered counterparts. The influence of the bottom cathode material and the electron transport layer is found to be negligible in terms of driving voltage, which means that the assumption of an ohmic bottom contact is valid. The hole transport and the charge carrier injection at the anode is much more sensitive to the evaporation sequence, especially when using hole transport materials with a glass transition temperature below 100°C. As a consequence, thermal annealing of fabricated inverted OLEDs is found to drastically improve the device electronics, resulting in lower driving voltages and an increased internal efficiency. The annealing effect on charge transport comes from a reduced charge accumulation due to an altered film morphology of the transport layers, which is proven for electrons and for holes independently. The thermal treatment can further lead to a device degradation. Finally, the thickness and the material of the blocking layers which usually control the charge confinement inside the OLED are found to influence the recombination much more effectively in inverted OLEDs compared to non-inverted ones.

碩士
國立成功大學
光電科學與工程學系
100
Native InAlAs oxide prepared by liquid phase oxidation (LPO) method as the gate insulator in the fabrication of InAlAs/InGaAs inverted-type metal-oxide-semiconductor high electron mobility transistors (MOSHEMTs) ispresented. The liquid phase oxidation system is simple, low-cost, and near temperature (30-70℃) without using extra energy to form a native oxide layer. In this work, we invested an InAlAs/InGaAs HEMT with a thin InAs layer inserted into the InGaAs channel layer to get improved DC and transconductance performance. To further improve HEMT performance, the InAlAs native oxide is used as the gate insulator for MOS-HEMT applications. In the DC measurements, the maximum drain current density is found to be 609 mA/mm at the gate-to-source voltage of 2.5 V, representing an improvement of about 32%. Meanwhile, the extrinsic transconductance is 327 mS/mm, representing an improvement of about 35%. The maximum turn-on voltage is 3.98 V, and the breakdown voltage is -4.62 V. The cut-off frequencies of conventional HEMTs and MOS-HEMTs are 5.7 GHz and 5.62 GHz; the maximum oscillation frequencies are 4.2 GHz and 3.9 GHz, respectively.And the noise figure is improved in MOS-HEMT owing to the reduced surface states.

The primary objective of this thesis is to develop a process for fabricating integrated circuits based on thin-film transistors (TFTs) using zinc tin oxide (ZTO) as the channel layer. ZTO, in contrast to indium- or gallium-based amorphous oxide semiconductors (AOS), is perceived to be a more commercially viable AOS choice due to its low cost and ability to be deposited via DC reactive sputtering. In the absence of an acceptable ZTO wet etch process, a plasma-etching process using Ar/CH₄ is developed for both 1:1 and 2:1 ZTO compositions. An Ar/CH₄ plasma etch process is also designed for indium gallium oxide (IGO), indium gallium zinc oxide (IGZO), and indium tin oxide (ITO). Ar/CH₄ dry etches have excellent selectivity with respect to SiO₂, providing a route for obtaining patterned ZTO channels. A critical asset of ZTO process integration involves removing polymer deposits after ZTO etching without active layer damage. A ZTO process is developed for the fabrication of integrated circuits which use ZTO channel enhancement-mode TFTs. Such ZTO TFTs exhibit incremental and average mobilities of 23 and 18 cm²V⁻¹s⁻¹, respectively, turn-on voltages approximately 0 to 1.5 V and subthreshold swings below 0.5 V/dec when annealed in air at 400 °C for 1 hour. Several types of ZTO TFT circuits are realized for the first time. Despite large parasitic capacitances due to large gate-source and gate-drain overlaps, AC/DC rectifiers are fabricated and found to operate in the MHz range. Thus, they are usable for RFID and other equivalent-speed applications. Finally, a ZTO process for simultaneously fabricating both enhancement-mode and depletion-mode TFTs on a single substrate using a single target and anneal step is developed. This dual-channel process is used to build a high-gain two-transistor enhancement/depletion inverter. At a rail voltage of 10 V, this inverter has a gain of 10.6 V/V, the highest yet reported for an AOS-based inverter. This E/D inverter is an important new functional block which will enable the realization of more complex digital logic circuits.
Graduation date: 2009

Recent developments in semiconductor device technology have seen the advent of wide-bandgap (WBG) based devices that enable operation at high switching frequencies. These devices, such as silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs), are becoming a favored choice in inverters for electric drive systems because of their lower switching losses and higher allowable operating temperature. However, the fast switching of such devices implies increased voltage edge rates (high dv/dt) that give rise to various undesirable effects including large common-mode currents, electromagnetic interference, transient overvoltages, insulation failure due to the overvoltages, and bearing failures due to

microarcs. With increased use of these devices in transportation and industrial applications, it is imperative that accurate models and efficient simulation tools, which can predict these high-frequency effects and accompanying system losses, be established. This research initially focuses on establishing an accurate wideband model of a surface-mount permanent-magnet

ac machine supplied by a WBG-based inverter. A new multirate simulation framework for predicting the transient behavior and estimating the power losses is then set forth. In this approach,

the wideband model is separated into high- and low-frequency models implemented using two different computer programs that are best suited for the respective time scales. Repetitive execution of the high-frequency model yields look-up tables for the switching losses in the semiconductors, electric machine, and interconnecting cable. These look-up tables are then incorporated into the low-frequency model that establishes the conduction

losses. This method is applied to a WBG-based electric drive comprised of a SiC inverter and permanent-magnet ac machine. Comparisons of measured and simulated transients are provided.

Indiana University-Purdue University Indianapolis (IUPUI)
The substantial increase demand for electrical energy requires high efficient apparatus dealing with energy conversion. Several technologies have been suggested to implement power supplies with higher efficiency, such as multilevel and interleaved converters. This thesis proposes an energy conversion unit with an optimized number of output voltage levels per number of switches nL=nS. The proposed five-level four-switch per phase converter has nL=nS=5/4 which is by far the best relationship among the converters presented in technical literature. A comprehensive literature review on existing five-level converter topologies is done to compare the proposed topology with conventional multilevel converters. The most important characteristics of the proposed configuration are: (i) reduced number of semiconductor devices, while keeping a high number of levels at the output converter side, (ii) only one DC source without any need to balance capacitor voltages, (iii) high efficiency, (iv) there is no dead-time requirement for the converters operation, (v) leg isolation procedure with lower stress for the DC-link capacitor. Single-phase and three-phase version of the proposed converter is presented in this thesis. Details regarding the operation of the configuration and modulation strategy are presented, as well as the comparison between the proposed converter and the conventional ones. Simulated results are presented to validate the theoretical expectations. In addition a fault tolerant converter based on proposed topology for micro-grid systems is presented. A hybrid pulse-width-modulation for the pre-fault operation and transition from the pre-fault to post-fault operation will be discussed. Selected steady-state and transient results are demonstrated to validate the theoretical modeling.

Die enorme Steigerung der Leistungsfähigkeit integrierter Schaltkreise wird seit über 50 Jahren im Wesentlichen durch eine Verkleinerung der Bauelementdimensionen erzielt. Aufgrund des Erreichens physikalischer Grenzen kann dieser Trend, unabhängig von der Lösung technologischer Probleme, langfristig nicht fortgesetzt werden. Diese Arbeit beschäftigt sich mit der Entwicklung und Herstellung neuartiger Transistoren und Schaltungen, welche im Vergleich zu konventionellen Bauelementen funktionserweitert sind, wodurch ein zur Skalierung alternativer Ansatz vorgestellt wird. Ausgehend von gewachsenen und nominell undotierten Silizium-Nanodrähten wird die Herstellung von Schottky-Barrieren-Feldeffekttransistoren (SBFETs) mit Hilfe etablierter und selbst entwickelter Methoden beschrieben und die Ladungsträgerinjektion unter dem Einfluss elektrischer Felder an den dabei erzeugten abrupten Metall–Halbleiter-Grenzflächen analysiert. Zur Optimierung der Injektionsvorgänge dienen strukturelle Modifikationen, welche zu erhöhten ambipolaren Strömen und einer vernachlässigbaren Hysterese der SBFETs führen. Mit dem rekonfigurierbaren Feldeffekttransistor (RFET) konnte ein Bauelement erzeugt werden, bei dem sich Elektronen- und Löcherinjektion unabhängig und bis zu neun Größenordnungen modulieren lassen. Getrennte Topgate-Elektroden über den Schottkybarrieren ermöglichen dabei die reversible Konfiguration von unipolarer Elektronenleitung (n-Typ) zu Löcherleitung (p-Typ) durch eine Programmierspannung, wodurch die Funktionen konventioneller FETs in einem universellen Bauelement vereint werden. Messungen und 3D-FEM-Simulationen geben einen detaillierten Einblick in den elektrischen Transport und dienen der anschaulichen Beschreibung der Funktionsweise. Systematische Untersuchungen zu Änderungen im Transistoraufbau, den Abmessungen und der Materialzusammensetzung verdeutlichen, dass zusätzliche Strukturverkleinerungen sowie die Verwendung von Halbleitern mit niedrigem Bandabstand die elektrische Charakteristik dieser Transistoren weiter verbessern. Im Hinblick auf die Realisierung neuartiger Schaltungen wird ein Konzept beschrieben, die funktionserweiterten Transistoren in einer energieeffizienten Komplementärtechnologie (CMOS) nutzbar zu machen. Die dafür notwendigen gleichen Elektronen- und Löcherstromdichten konnten durch einen modifizierten Ladungsträgertunnelprozess infolge mechanischer Verspannungen an den Schottkyübergängen erzielt und weltweit erstmalig an einem Transistor gezeigt werden. Der aus einem <110>-Nanodraht mit 12 nm Si-Kerndurchmesser erzeugte elektrisch symmetrische RFET weist dabei eine bisher einzigartige Kennliniensymmetrie auf.Die technische Umsetzung des Schaltungskonzepts erfolgt durch die Integration zweier RFETs innerhalb eines Nanodrahts zum dotierstofffreien CMOS-Inverter, der flexibel programmiert werden kann. Die rekonfigurierbare NAND/NOR- Schaltung verdeutlicht, dass durch die RFET-Technologie die Bauelementanzahl reduziert und die Funktionalität des Systems im Vergleich zu herkömmlichen Schaltungen erhöht werden kann. Ferner werden weitere Schaltungsbeispiele sowie die technologischen Herausforderungen einer industriellen Umsetzung des Konzeptes diskutiert. Mit der funktionserweiterten, dotierstofffreien RFET-Technologie wird ein neuartiger Ansatz beschrieben, den technischen Fortschritt der Elektronik nach dem erwarteten Ende der klassischen Skalierung zu ermöglichen.:Kurzzusammenfassung Abstract 1 Einleitung 2 Nanodrähte als aktivesGebiet fürFeldeffekttransistoren 2.1 Elektrisches Potential und Ladungsträgertransport in Transistoren 2.1.1 Potentialverlauf 2.1.2 Ladungsträgerfluss und Steuerung 2.2 Der Metall-Halbleiter-Kontakt 2.2.1 Ladungsträgertransport über den Schottky-Kontakt 2.2.2 Thermionische Emission 2.2.3 Ladungsträgertunneln 2.2.4 Methoden zur Beschreibung der Gesamtinjektion 2.3 Der Schottkybarrieren-Feldeffekttransistor 2.4 Stand der Technik 2.4.1 Elektronische Bauelemente auf Basis von Nanoröhren und Nanodrähten 2.4.2 Rekonfigurierbare Transistoren und Schaltungen 2.5 Zusammenfassung 3 TechnologienzurHerstellung vonNanodraht-Transistoren 3.1 Herstellung von SB-Nanodraht-Transistoren mit Rückseitengatelektrode 3.1.1 Nanodraht-Strukturbildung durch VLS-Wachstum 3.1.2 Drahttransfer 3.1.3 Herstellung von Kontaktelektroden 3.1.4 Herstellung von Schottky-Kontakten innerhalb eines Nanodrahtes 3.2 Strukturerzeugung mittels Elektronenstrahllithographie 3.2.1 Schichtstrukturierung mittels Elektronenstrahllithographie 3.2.2 Strukturierung mittels ungerichteter Elektronenstrahllithographie 3.2.3 Justierte Strukturierung mittels Elektronenstrahllithographie 3.2.4 Justierte Strukturierung mittels feinangepasster Elektronenstrahllithographie 3.2.5 Justierte Strukturierung mittels kombinierter optischer und Elektronenstrahllithographie 3.3 Zusammenfassung 4 Realisierung und Optimierung siliziumbasierter Schottkybarrieren- Nanodraht-Transistoren 4.1 Nanodraht-Transistor mit einlegierten Silizidkontakten 4.1.1 Transistoren auf Basis von Nanodrähten in <112>-Richtung 4.1.2 Transistoren mit veränderten Abmessungen 4.2 Analyse und Optimierung der Gatepotentialverteilung im Drahtquerschnitt in Kontaktnähe 4.3 Si/SiO2 - Core/Shell Nanodrähte als Basis für elektrisch optimierte Transistoren 4.3.1 Si-Oxidation im Volumenmaterial 4.3.2 Si-Oxidation am Draht 4.3.3 Silizidierung innerhalb der Oxidhülle 4.3.4 Core/Shell-Nanodraht-Transistoren mit Rückseitengate 4.4 Analyse der Gatepotentialwirkung in Abhängigkeit des Abstands zur Barriere 4.5 Zusammenfassung 5 RFET - Der Rekonfigurierbare Feldeffekttransistor 5.1 Realisierung des RFET 5.2 Elektrische Charakteristik 5.2.1 Elektrische Beschaltung und Funktionsprinzip 5.2.2 Elektrische Messungen 5.2.3 Auswertung 5.3 Transporteigenschaften des rekonfigurierbaren Transistors 5.3.1 Tunnel- und thermionische Ströme im RFET 5.3.2 Analyse der Transportvorgänge mit Hilfe der numerischen Simulation 5.3.3 Schaltzustände des RFET 5.3.4 On-zu-Off Verhältnisse des RFET 5.3.5 Einfluss der Bandlücke auf das On- zu Off-Verhältnis 5.3.6 Abhängigkeiten von geometrischen, materialspezifischen und physikalischen Parametern 5.3.7 Skalierung des RFET 5.3.8 Längenskalierung des aktiven Gebietes 5.4 Vergleich verschiedener Konzepte zur Rekonfigurierbarkeit 5.5 Zusammenfassung 6 Schaltungen aus rekonfigurierbaren Bauelementen 6.1 Komplementäre Schaltkreise 6.1.1 Inverter 6.1.2 Universelle Gatter 6.1.3 Anforderungen an komplementäre Bauelemente 6.1.4 Individuelle Symmetrieanpassung statischer Transistoren 6.2 Rekonfigurierbare Transistoren als Bauelemente für komplementäre Elektronik 6.2.1 Analyse des RFET als komplementäres Bauelement 6.2.2 Bauelementbedingungen für eine rekonfigurierbare komplementäre Elektronik 6.3 Erzeugung eines RFETs für rekonfigurierbare komplementäre Schaltkreise 6.3.1 Möglichkeiten der Symmetrieanpassung 6.3.2 Erzeugung eines RFET mit elektrischer Symmetrie 6.3.3 Erzeugung und Aufbau des symmetrischen RFET 6.3.4 Elektrische Eigenschaften des symmetrischen RFET 6.4 Realisierung von komplementären rekonfigurierbaren Schaltungen 6.4.1 Integration identischer RFETs 6.4.2 RFET-basierter komplementärer Inverter 6.4.3 Rekonfigurierbarer CMOS-Inverter 6.4.4 PMOS/NMOS-Inverter 6.4.5 Zusammenfassung zur RFET-Inverterschaltung 6.4.6 Rekonfigurierbarer NAND/NOR-Schaltkreis 6.5 Zusammenfassung und Diskussion 7 Zusammenfassung und Ausblick 7.1 Zusammenfassung 7.2 Ausblick Anhang Symbol- und Abkürzungsverzeichnis Literaturverzeichnis Publikations- und Vortragsliste Danksagung Eidesstattliche Erklärung
The enormous increase in performance of integrated circuits has been driven for more than 50 years, mainly by reducing the device dimensions. This trend cannot continue in the long term due to physical limits being reached. The scope of this thesis is the development and fabrication of novel kinds of transistors and circuits that provide higher functionality compared to the classical devices, thus introducing an alternative approach to scaling. The fabrication of Schottky barrier field effect transistors (SBFETs) based on nominally undoped grown silicon nanowires using established and developed techniques is described. Further the charge carrier injection in the fabricated metal to semiconductor interfaces is analyzed under the influence of electrical fields. Structural modifications are used to optimize the charge injection resulting in increased ambipolar currents and negligible hysteresis of the SBFETs. Moreover, a device has been developed called the reconfigurable field-effect transistor (RFET), in which the electron and hole injection can be independently controlled by up to nine orders of magnitude. This device can be reversibly configured from unipolar electron conducting (ntype) to hole conducting (p-type) by the application of a program voltage to the two individual top gate electrodes at the Schottky junctions. So the RFET merges the functionality of classical FETs into one universal device. Measurements and 3D finite element method simulations are used to analyze the electrical transport and to describe the operation principle. Systematic investigations of changes in the device structure, dimensions and material composition show enhanced characteristics in scaled and low bandgap semiconductor RFET devices. For the realization of novel circuits, a concept is described to use the enhanced functionality of the transistors in order to realize energy efficient complementary circuits (CMOS). The required equal electron and hole current densities are achieved by the modification of charge carrier tunneling due to mechanical stress and are shown for the first time ever on a transistor. An electrically symmetric RFET based on a compressive strained nanowire in <110> crystal direction and 12 nm silicon core diameter exhibits unique electrical symmetry. The circuit concept is demonstrated by the integration of two RFETs on a single nanowire, thus realizing a dopant free CMOS inverter which can be programmed flexibly. The reconfigurable NAND/NOR shows that the RFET technology can lead to a reduction of the transistor count and can increase the system functionality. Additionally, further circuit examples and the challenges of an industrial implementation of the concept are discussed.The enhanced functionality and dopant free RFET technology describes a novel approach to maintain the technological progress in electronics after the expected end of classical device scaling.:Kurzzusammenfassung Abstract 1 Einleitung 2 Nanodrähte als aktivesGebiet fürFeldeffekttransistoren 2.1 Elektrisches Potential und Ladungsträgertransport in Transistoren 2.1.1 Potentialverlauf 2.1.2 Ladungsträgerfluss und Steuerung 2.2 Der Metall-Halbleiter-Kontakt 2.2.1 Ladungsträgertransport über den Schottky-Kontakt 2.2.2 Thermionische Emission 2.2.3 Ladungsträgertunneln 2.2.4 Methoden zur Beschreibung der Gesamtinjektion 2.3 Der Schottkybarrieren-Feldeffekttransistor 2.4 Stand der Technik 2.4.1 Elektronische Bauelemente auf Basis von Nanoröhren und Nanodrähten 2.4.2 Rekonfigurierbare Transistoren und Schaltungen 2.5 Zusammenfassung 3 TechnologienzurHerstellung vonNanodraht-Transistoren 3.1 Herstellung von SB-Nanodraht-Transistoren mit Rückseitengatelektrode 3.1.1 Nanodraht-Strukturbildung durch VLS-Wachstum 3.1.2 Drahttransfer 3.1.3 Herstellung von Kontaktelektroden 3.1.4 Herstellung von Schottky-Kontakten innerhalb eines Nanodrahtes 3.2 Strukturerzeugung mittels Elektronenstrahllithographie 3.2.1 Schichtstrukturierung mittels Elektronenstrahllithographie 3.2.2 Strukturierung mittels ungerichteter Elektronenstrahllithographie 3.2.3 Justierte Strukturierung mittels Elektronenstrahllithographie 3.2.4 Justierte Strukturierung mittels feinangepasster Elektronenstrahllithographie 3.2.5 Justierte Strukturierung mittels kombinierter optischer und Elektronenstrahllithographie 3.3 Zusammenfassung 4 Realisierung und Optimierung siliziumbasierter Schottkybarrieren- Nanodraht-Transistoren 4.1 Nanodraht-Transistor mit einlegierten Silizidkontakten 4.1.1 Transistoren auf Basis von Nanodrähten in <112>-Richtung 4.1.2 Transistoren mit veränderten Abmessungen 4.2 Analyse und Optimierung der Gatepotentialverteilung im Drahtquerschnitt in Kontaktnähe 4.3 Si/SiO2 - Core/Shell Nanodrähte als Basis für elektrisch optimierte Transistoren 4.3.1 Si-Oxidation im Volumenmaterial 4.3.2 Si-Oxidation am Draht 4.3.3 Silizidierung innerhalb der Oxidhülle 4.3.4 Core/Shell-Nanodraht-Transistoren mit Rückseitengate 4.4 Analyse der Gatepotentialwirkung in Abhängigkeit des Abstands zur Barriere 4.5 Zusammenfassung 5 RFET - Der Rekonfigurierbare Feldeffekttransistor 5.1 Realisierung des RFET 5.2 Elektrische Charakteristik 5.2.1 Elektrische Beschaltung und Funktionsprinzip 5.2.2 Elektrische Messungen 5.2.3 Auswertung 5.3 Transporteigenschaften des rekonfigurierbaren Transistors 5.3.1 Tunnel- und thermionische Ströme im RFET 5.3.2 Analyse der Transportvorgänge mit Hilfe der numerischen Simulation 5.3.3 Schaltzustände des RFET 5.3.4 On-zu-Off Verhältnisse des RFET 5.3.5 Einfluss der Bandlücke auf das On- zu Off-Verhältnis 5.3.6 Abhängigkeiten von geometrischen, materialspezifischen und physikalischen Parametern 5.3.7 Skalierung des RFET 5.3.8 Längenskalierung des aktiven Gebietes 5.4 Vergleich verschiedener Konzepte zur Rekonfigurierbarkeit 5.5 Zusammenfassung 6 Schaltungen aus rekonfigurierbaren Bauelementen 6.1 Komplementäre Schaltkreise 6.1.1 Inverter 6.1.2 Universelle Gatter 6.1.3 Anforderungen an komplementäre Bauelemente 6.1.4 Individuelle Symmetrieanpassung statischer Transistoren 6.2 Rekonfigurierbare Transistoren als Bauelemente für komplementäre Elektronik 6.2.1 Analyse des RFET als komplementäres Bauelement 6.2.2 Bauelementbedingungen für eine rekonfigurierbare komplementäre Elektronik 6.3 Erzeugung eines RFETs für rekonfigurierbare komplementäre Schaltkreise 6.3.1 Möglichkeiten der Symmetrieanpassung 6.3.2 Erzeugung eines RFET mit elektrischer Symmetrie 6.3.3 Erzeugung und Aufbau des symmetrischen RFET 6.3.4 Elektrische Eigenschaften des symmetrischen RFET 6.4 Realisierung von komplementären rekonfigurierbaren Schaltungen 6.4.1 Integration identischer RFETs 6.4.2 RFET-basierter komplementärer Inverter 6.4.3 Rekonfigurierbarer CMOS-Inverter 6.4.4 PMOS/NMOS-Inverter 6.4.5 Zusammenfassung zur RFET-Inverterschaltung 6.4.6 Rekonfigurierbarer NAND/NOR-Schaltkreis 6.5 Zusammenfassung und Diskussion 7 Zusammenfassung und Ausblick 7.1 Zusammenfassung 7.2 Ausblick Anhang Symbol- und Abkürzungsverzeichnis Literaturverzeichnis Publikations- und Vortragsliste Danksagung Eidesstattliche Erklärung

Die vorliegende Arbeit befasst sich mit einem detaillierten Vergleich von Mehrpunkt-Schaltungstopologien mit zentralem Gleichspannungszwischenkreis für den Einsatz in Mittelspannungsanwendungen. Im Rahmen dieser Untersuchungen wird die 3-Level Neutral Point Clamped Spannungswechselrichter Schaltungstopologie (3L-NPC VSC) sowohl mit Multilevel Flying Capacitor (FLC) als auch mit Multilevel Stacked Multicell (SMC) Schaltungstopologien verglichen, wobei unter Verwendung von aktuell verfügbaren IGBT-Modulen Stromrichterausgangsspannungen von 2.3 kV, 4.16 kV und 6.6 kV betrachtet werden. Neben der grundlegenden Funktionsweise wird die Auslegung der aktiven Leistungshalbleiter und der passiven Energiespeicher (Zwischenkreiskondensatoren, Flying Capacitors) für die untersuchten Stromrichtertopologien dargestellt. Unter Berücksichtigung verschiedener Modulationsverfahren und Schaltfrequenzen werden Kennwerte für den Oberschwingungsgehalt in der Ausgangsspannung und dem Ausgangsstrom vergleichend evaluiert. Die installierte Schalterleistungen, die Halbleiterausnutzungsfaktoren, die Stromrichterverlustleistungen sowie die Verlustleistungsverteilungen werden für die betrachteten Stromrichtertopologien detailliert gegenübergestellt und bewertet.:Inhaltsverzeichnis Liste der Variablen i Liste der Abkürzungen v 1 Einleitung 1 2 Überblick von Mittelspannungsstromrichtertopologien und Leistungshalbleitern 3 2.1 Mittelspannungsumrichtertopologien 3 2.2 Leistungshalbleiter 8 3 Aufbau und Funktion von Mittelspannungsstromrichtertopologien 10 3.1 Neutral Point Clamped Stromrichter (NPC) 10 3.1.1 3-Level Neutral Point Clamped Stromrichter (3L-NPC) 10 3.1.2 Mehrstufige NPC-Umrichter 21 3.2 Flying Capacitor Stromrichter (FLC) 23 3.2.1 3-Level Flying Capacitor Stromrichter (3L-FLC) 23 3.2.2 4-Level Flying Capacitor-Stromrichter (4L-FLC) 33 3.2.3 Mehrstufige Flying Capacitor-Stromrichter (NL-FLC) 39 3.3 Stacked Multicell Stromrichter (SMC) 43 3.3.1 5L-Stacked Multicell Stromrichter (5L-SMC) 43 3.3.2 N-Level Stacked Multicell Umrichter (NL-SMC) 51 4 Modellierung und Auslegung der Stromrichter 59 4.1 Verlustmodell 59 4.1.1 Sperrschichttemperaturen 64 4.2 Auslegung der Leistungshalbleiter 65 4.2.1 Stromauslegung 67 4.2.2 Worst-Case Arbeitspunkte 69 4.3 Auslegung der Zwischenkreiskondensatoren 75 4.3.1 Spannungszwischenkreis 76 4.3.2 Lastseitige Strombelastung und resultierende Spannungswelligkeit im Spannungszwischenkreis 77 4.3.3 Abhängigkeit der Strombelastung und der Spannungswelligkeit im Spannungszwischenkreis vom Frequenzverhältnis mf 95 4.3.4 Netzseitige Zwischenkreiseinspeisung 97 4.3.4.1 Zwischenkreiseinspeisung mit idealisiertem Transformatormodell 98 4.3.4.2 Zwischenkreiseinspeisung mit erweitertem Transformatormodell 101 4.3.5 Simulation des Gesamtsystems 104 4.4 Auslegung der Flying Capacitors 107 4.4.1 Strombelastung der Flying Capacitors 109 4.4.2 Spannungswelligkeit über den Flying Capacitors 113 4.4.3 Abhängigkeit der Spannungswelligkeit der Flying Capacitors vom Frequenzverhältnis mf 124 4.4.4 Auswirkung der Spannungswelligkeit der Flying Capacitors auf die Ausgangsspannungen 126 5 Vergleich der Stromrichtertopologien 129 5.1 Daten für den Stromrichtervergleich 129 5.2 Basis des Vergleiches 132 5.3 Vergleich für einen 2,3 kV Mittelspannungsstromrichter 134 5.3.1 Vergleich bei verschiedenen Schaltfrequenzen 134 5.3.2 Vergleich bei maximaler Trägerfrequenz 142 5.4 Vergleich für einen 4,16 kV Mittelspannungsstromrichter 146 5.4.1 Vergleich bei verschiedenen Schaltfrequenzen 146 5.4.2 Vergleich bei maximaler Trägerfrequenz 153 5.5 Vergleich für einen 6,6 kV Mittelspannungsstromrichter 156 5.5.1 Vergleich bei verschiedenen Schaltfrequenzen 156 5.5.2 Vergleich bei maximaler Trägerfrequenz 162 5.6 Vergleich von 2,3 kV, 4,16 kV und 6,6 kV Mittelspannungsstromrichtern 165 5.6.1 Vergleich bei identischer installierter Schalterleistung SS 165 5.6.2 Vergleich bei einer identischen Ausgangsleistung 167 6 Zusammenfassung und Bewertung 171 Anhang 175 A. Halbleiterverlustmodell 175 Referenzen 177
The thesis deals with a detailed comparison of voltage source converter topologies with a central dc-link energy storage device for medium voltage applications. The Three-Level Neutral Point Clamped Voltage Source Converter (3L-NPC VSC) is compared with multilevel Flying Capacitor (FLC) and Stacked Multicell (SMC) Voltage Source Converters (VSC) for output voltages of 2.3 kV, 4.16 kV and 6.6 kV by using state-of-the-art 6.5 kV, 3.3 kV, 4.5 kV and 1.7kV IGBTs. The fundamental functionality of the investigated converter topologies as well as the design of the power semiconductors and of the energy storage devices (Flying Capacitors and Dc-Link capacitors) is described. The installed switch power, converter losses, the semiconductor loss distribution, modulation strategies and the harmonic spectra are compared in detail.:Inhaltsverzeichnis Liste der Variablen i Liste der Abkürzungen v 1 Einleitung 1 2 Überblick von Mittelspannungsstromrichtertopologien und Leistungshalbleitern 3 2.1 Mittelspannungsumrichtertopologien 3 2.2 Leistungshalbleiter 8 3 Aufbau und Funktion von Mittelspannungsstromrichtertopologien 10 3.1 Neutral Point Clamped Stromrichter (NPC) 10 3.1.1 3-Level Neutral Point Clamped Stromrichter (3L-NPC) 10 3.1.2 Mehrstufige NPC-Umrichter 21 3.2 Flying Capacitor Stromrichter (FLC) 23 3.2.1 3-Level Flying Capacitor Stromrichter (3L-FLC) 23 3.2.2 4-Level Flying Capacitor-Stromrichter (4L-FLC) 33 3.2.3 Mehrstufige Flying Capacitor-Stromrichter (NL-FLC) 39 3.3 Stacked Multicell Stromrichter (SMC) 43 3.3.1 5L-Stacked Multicell Stromrichter (5L-SMC) 43 3.3.2 N-Level Stacked Multicell Umrichter (NL-SMC) 51 4 Modellierung und Auslegung der Stromrichter 59 4.1 Verlustmodell 59 4.1.1 Sperrschichttemperaturen 64 4.2 Auslegung der Leistungshalbleiter 65 4.2.1 Stromauslegung 67 4.2.2 Worst-Case Arbeitspunkte 69 4.3 Auslegung der Zwischenkreiskondensatoren 75 4.3.1 Spannungszwischenkreis 76 4.3.2 Lastseitige Strombelastung und resultierende Spannungswelligkeit im Spannungszwischenkreis 77 4.3.3 Abhängigkeit der Strombelastung und der Spannungswelligkeit im Spannungszwischenkreis vom Frequenzverhältnis mf 95 4.3.4 Netzseitige Zwischenkreiseinspeisung 97 4.3.4.1 Zwischenkreiseinspeisung mit idealisiertem Transformatormodell 98 4.3.4.2 Zwischenkreiseinspeisung mit erweitertem Transformatormodell 101 4.3.5 Simulation des Gesamtsystems 104 4.4 Auslegung der Flying Capacitors 107 4.4.1 Strombelastung der Flying Capacitors 109 4.4.2 Spannungswelligkeit über den Flying Capacitors 113 4.4.3 Abhängigkeit der Spannungswelligkeit der Flying Capacitors vom Frequenzverhältnis mf 124 4.4.4 Auswirkung der Spannungswelligkeit der Flying Capacitors auf die Ausgangsspannungen 126 5 Vergleich der Stromrichtertopologien 129 5.1 Daten für den Stromrichtervergleich 129 5.2 Basis des Vergleiches 132 5.3 Vergleich für einen 2,3 kV Mittelspannungsstromrichter 134 5.3.1 Vergleich bei verschiedenen Schaltfrequenzen 134 5.3.2 Vergleich bei maximaler Trägerfrequenz 142 5.4 Vergleich für einen 4,16 kV Mittelspannungsstromrichter 146 5.4.1 Vergleich bei verschiedenen Schaltfrequenzen 146 5.4.2 Vergleich bei maximaler Trägerfrequenz 153 5.5 Vergleich für einen 6,6 kV Mittelspannungsstromrichter 156 5.5.1 Vergleich bei verschiedenen Schaltfrequenzen 156 5.5.2 Vergleich bei maximaler Trägerfrequenz 162 5.6 Vergleich von 2,3 kV, 4,16 kV und 6,6 kV Mittelspannungsstromrichtern 165 5.6.1 Vergleich bei identischer installierter Schalterleistung SS 165 5.6.2 Vergleich bei einer identischen Ausgangsleistung 167 6 Zusammenfassung und Bewertung 171 Anhang 175 A. Halbleiterverlustmodell 175 Referenzen 177