Статті в журналах з теми "RISC V processor"
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Pitcher, Graham. "RISC-V Powers IoT Apps Processor." New Electronics 51, no. 4 (February 27, 2018): 7. http://dx.doi.org/10.12968/s0047-9624(23)60141-5.
Повний текст джерелаGamino del Río, Iván, Agustín Martínez Hellín, Óscar R. Polo, Miguel Jiménez Arribas, Pablo Parra, Antonio da Silva, Jonatan Sánchez, and Sebastián Sánchez. "A RISC-V Processor Design for Transparent Tracing." Electronics 9, no. 11 (November 7, 2020): 1873. http://dx.doi.org/10.3390/electronics9111873.
Повний текст джерелаHongsheng, Zhang, Zekun Jiang, and Yong Li. "Design of a dual-issue RISC-V processor." Journal of Physics: Conference Series 1693 (December 2020): 012192. http://dx.doi.org/10.1088/1742-6596/1693/1/012192.
Повний текст джерелаAn, Hyogeun, Sudong Kang, Guard Kanda, and Kwangki Ryoo. "RISC-V Hardware Synthesizable Processor Design Test and Verification Using User-Friendly Desktop Application." Webology 19, no. 1 (January 20, 2022): 4597–620. http://dx.doi.org/10.14704/web/v19i1/web19305.
Повний текст джерелаNúñez-Prieto, Ricardo, David Castells-Rufas, and Lluís Terés-Terés. "RisCO2: Implementation and Performance Evaluation of RISC-V Processors for Low-Power CO2 Concentration Sensing." Micromachines 14, no. 7 (July 4, 2023): 1371. http://dx.doi.org/10.3390/mi14071371.
Повний текст джерелаMichel Deves de Souza, Eduardo, Nathalia Nathalia Adriana de Oliveira, Douglas Almeida dos Santos Almeida dos Santos, and Douglas Rossi de Melo. "RVSH - Um processador RISC-V para fins didáticos." Anais do Computer on the Beach 14 (May 3, 2023): 450–52. http://dx.doi.org/10.14210/cotb.v14.p450-452.
Повний текст джерелаZhou, Weixin, Dehua Wu, Wan’ang Xiao, Shan Gao, and Wanlin Gao. "A Novel Sleep Scheduling Strategy on RISC-V Processor." Journal of Physics: Conference Series 1631 (September 2020): 012028. http://dx.doi.org/10.1088/1742-6596/1631/1/012028.
Повний текст джерелаXue, Wang, Liu, Lv, Wang, and Zeng. "An RISC-V Processor with Area-Efficient Memristor-Based In-Memory Computing for Hash Algorithm in Blockchain Applications." Micromachines 10, no. 8 (August 16, 2019): 541. http://dx.doi.org/10.3390/mi10080541.
Повний текст джерелаSantos, Douglas A., André M. P. Mattos, Douglas R. Melo, and Luigi Dilillo. "Enhancing Fault Awareness and Reliability of a Fault-Tolerant RISC-V System-on-Chip." Electronics 12, no. 12 (June 6, 2023): 2557. http://dx.doi.org/10.3390/electronics12122557.
Повний текст джерелаGomes, Tiago, Pedro Sousa, Miguel Silva, Mongkol Ekpanyapong, and Sandro Pinto. "FAC-V: An FPGA-Based AES Coprocessor for RISC-V." Journal of Low Power Electronics and Applications 12, no. 4 (September 27, 2022): 50. http://dx.doi.org/10.3390/jlpea12040050.
Повний текст джерелаPietzsch, Marcus. "RISC-V Processor for Network Platforms According to ISO 26262." ATZelectronics worldwide 16, no. 11 (November 2021): 8–13. http://dx.doi.org/10.1007/s38314-021-0691-y.
Повний текст джерелаGao, Shan, Wan’ang Xiao, Zhenghong Yang, Dehua Wu, and Wanlin Gao. "A fast on-chip debugging design for RISC-V processor." Journal of Physics: Conference Series 1976, no. 1 (July 1, 2021): 012056. http://dx.doi.org/10.1088/1742-6596/1976/1/012056.
Повний текст джерелаCheng, Yuan-Hu, Li-Bo Huang, Yi-Jun Cui, Sheng Ma, Yong-Wen Wang, and Bing-Cai Sui. "RV16: An Ultra-Low-Cost Embedded RISC-V Processor Core." Journal of Computer Science and Technology 37, no. 6 (November 30, 2022): 1307–19. http://dx.doi.org/10.1007/s11390-022-0910-x.
Повний текст джерелаJamieson, Peter, Huan Le, Nathan Martin, Tyler McGrew, Yicheng Qian, Eric Schonauer, Alan Ehret, and Michel A. Kinsy. "Computer Engineering Education Experiences with RISC-V Architectures—From Computer Architecture to Microcontrollers." Journal of Low Power Electronics and Applications 12, no. 3 (August 9, 2022): 45. http://dx.doi.org/10.3390/jlpea12030045.
Повний текст джерелаB, Rajeshwari, Rithvik Kumar, Shweta P. Hegde, Manav Eswar Prasad, Vandhya D M, and Bajrangabali B. "Dual Quaternion Hardware Accelerator for RISC-V based System." International Journal of Research and Scientific Innovation 09, no. 05 (2022): 77–81. http://dx.doi.org/10.51244/ijrsi.2022.9506.
Повний текст джерелаLim, Seung-Ho, WoonSik William Suh, Jin-Young Kim, and Sang-Young Cho. "RISC-V Virtual Platform-Based Convolutional Neural Network Accelerator Implemented in SystemC." Electronics 10, no. 13 (June 23, 2021): 1514. http://dx.doi.org/10.3390/electronics10131514.
Повний текст джерелаGao, Shan, Dehua Wu, Wan’ang Xiao, Zetao Wang, Zhenghong Yang, and Wanlin Gao. "A novel method for on-chip debugging based on RISC-V processor." MATEC Web of Conferences 355 (2022): 03055. http://dx.doi.org/10.1051/matecconf/202235503055.
Повний текст джерелаMIYAZAKI, Hiromu, Takuto KANAMORI, Md Ashraful ISLAM, and Kenji KISE. "RVCoreP: An Optimized RISC-V Soft Processor of Five-Stage Pipelining." IEICE Transactions on Information and Systems E103.D, no. 12 (December 1, 2020): 2494–503. http://dx.doi.org/10.1587/transinf.2020pap0015.
Повний текст джерелаLi, Jiemin, Shancong Zhang, and Chong Bao. "DuckCore: A Fault-Tolerant Processor Core Architecture Based on the RISC-V ISA." Electronics 11, no. 1 (December 30, 2021): 122. http://dx.doi.org/10.3390/electronics11010122.
Повний текст джерелаPatrick, Mark. "What's all the Hype About?" New Electronics 53, no. 14 (August 11, 2020): 22–23. http://dx.doi.org/10.12968/s0047-9624(22)61362-2.
Повний текст джерелаKwon, Donghyun, Dongil Hwang, and Yunheung Paek. "A Hardware Platform for Ensuring OS Kernel Integrity on RISC-V." Electronics 10, no. 17 (August 26, 2021): 2068. http://dx.doi.org/10.3390/electronics10172068.
Повний текст джерелаCococcioni, Marco, Federico Rossi, Emanuele Ruffaldi, and Sergio Saponara. "Vectorizing posit operations on RISC-V for faster deep neural networks: experiments and comparison with ARM SVE." Neural Computing and Applications 33, no. 16 (February 28, 2021): 10575–85. http://dx.doi.org/10.1007/s00521-021-05814-0.
Повний текст джерелаLi, Zhiyu, Yuhao Huang, Longfeng Tian, Ruimin Zhu, Shanlin Xiao, and Zhiyi Yu. "A Low-Power Asynchronous RISC-V Processor With Propagated Timing Constraints Method." IEEE Transactions on Circuits and Systems II: Express Briefs 68, no. 9 (September 2021): 3153–57. http://dx.doi.org/10.1109/tcsii.2021.3100524.
Повний текст джерелаMurabayashi, F., T. Yamauchi, H. Yamada, T. Nishiyama, K. Shimamura, S. Tanaka, T. Hotta, T. Shimizu, and H. Sawamoto. "2.5 V CMOS circuit techniques for a 200 MHz superscalar RISC processor." IEEE Journal of Solid-State Circuits 31, no. 7 (July 1996): 972–80. http://dx.doi.org/10.1109/4.508211.
Повний текст джерелаZhang, Haifeng, Xiaoti Wu, Yuyu Du, Hongqing Guo, Chuxi Li, Yidong Yuan, Meng Zhang, and Shengbing Zhang. "A Heterogeneous RISC-V Processor for Efficient DNN Application in Smart Sensing System." Sensors 21, no. 19 (September 28, 2021): 6491. http://dx.doi.org/10.3390/s21196491.
Повний текст джерелаSchmidt, Colin, John Wright, Zhongkai Wang, Eric Chang, Albert Ou, Woorham Bae, Sean Huang, et al. "An Eight-Core 1.44-GHz RISC-V Vector Processor in 16-nm FinFET." IEEE Journal of Solid-State Circuits 57, no. 1 (January 2022): 140–52. http://dx.doi.org/10.1109/jssc.2021.3118046.
Повний текст джерелаTada, Jubee, and Keiichi Sato. "An Implementation of a Grid Square Codes Generator on a RISC-V Processor." International Journal of Networking and Computing 12, no. 1 (2022): 204–17. http://dx.doi.org/10.15803/ijnc.12.1_204.
Повний текст джерелаde Oliveira, Adria B., Lucas A. Tambara, Fabio Benevenuti, Luis A. C. Benites, Nemitala Added, Vitor A. P. Aguiar, Nilberto H. Medina, Marcilei A. G. Silveira, and Fernanda L. Kastensmidt. "Evaluating Soft Core RISC-V Processor in SRAM-Based FPGA Under Radiation Effects." IEEE Transactions on Nuclear Science 67, no. 7 (July 2020): 1503–10. http://dx.doi.org/10.1109/tns.2020.2995729.
Повний текст джерелаCho, Hyungmin. "Impact of Microarchitectural Differences of RISC-V Processor Cores on Soft Error Effects." IEEE Access 6 (2018): 41302–13. http://dx.doi.org/10.1109/access.2018.2858773.
Повний текст джерелаKaneko, Hiroaki, and Akinori Kanasugi. "An integrated machine code monitor for a RISC-V processor on an FPGA." Artificial Life and Robotics 25, no. 3 (March 9, 2020): 427–33. http://dx.doi.org/10.1007/s10015-020-00593-8.
Повний текст джерелаGarofalo, Angelo, Manuele Rusci, Francesco Conti, Davide Rossi, and Luca Benini. "PULP-NN: accelerating quantized neural networks on parallel ultra-low-power RISC-V processors." Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences 378, no. 2164 (December 23, 2019): 20190155. http://dx.doi.org/10.1098/rsta.2019.0155.
Повний текст джерелаC, Rohan. "Design of a 32-Bit, Dual Pipeline Superscalar RISC-V Processor on FPGA: A Review." International Journal for Research in Applied Science and Engineering Technology 10, no. 6 (June 30, 2022): 4044–46. http://dx.doi.org/10.22214/ijraset.2022.44654.
Повний текст джерелаYu, Hongjiang, Guoshun Yuan, Dewei Kong, and Chuhuai Chen. "An Optimized Implementation of Activation Instruction Based on RISC-V." Electronics 12, no. 9 (April 24, 2023): 1986. http://dx.doi.org/10.3390/electronics12091986.
Повний текст джерелаKalapothas, Stavros, Manolis Galetakis, Georgios Flamis, Fotis Plessas, and Paris Kitsos. "A Survey on RISC-V-Based Machine Learning Ecosystem." Information 14, no. 2 (January 21, 2023): 64. http://dx.doi.org/10.3390/info14020064.
Повний текст джерелаJaiswal, Nidhi. "Design of High Performance Core Micro-Architecture Based on RISC-V ISA for Low Power Applications." International Journal for Research in Applied Science and Engineering Technology 11, no. 7 (July 31, 2023): 734–42. http://dx.doi.org/10.22214/ijraset.2023.54647.
Повний текст джерелаGuangTang, Jiancheng, and Li. "Research and design of low-power, high-performance processor based on RISC-V instruction set architecture." Journal of Physics: Conference Series 2221, no. 1 (May 1, 2022): 012008. http://dx.doi.org/10.1088/1742-6596/2221/1/012008.
Повний текст джерелаRagini, Dr K., and Nidhi Jaiswal. "Design of High-Performance Core Micro-Architecture Based on 32- Bit RISC-V Instruction Set Architecture [ISA]." International Journal for Research in Applied Science and Engineering Technology 11, no. 7 (July 31, 2023): 1025–33. http://dx.doi.org/10.22214/ijraset.2023.54791.
Повний текст джерелаNişancı, Görkem, Paul G. Flikkema, and Tolga Yalçın. "Symmetric Cryptography on RISC-V: Performance Evaluation of Standardized Algorithms." Cryptography 6, no. 3 (August 10, 2022): 41. http://dx.doi.org/10.3390/cryptography6030041.
Повний текст джерелаAndorno, M., M. Andersen, G. Borghello, A. Caratelli, D. Ceresa, J. Dhaliwal, K. Kloukinas, and R. Pejasinovic. "Rad-hard RISC-V SoC and ASIP ecosystems studies for high-energy physics applications." Journal of Instrumentation 18, no. 01 (January 1, 2023): C01018. http://dx.doi.org/10.1088/1748-0221/18/01/c01018.
Повний текст джерелаRathi, C. Arul, G. Rajakumar, T. Ananth Kumar, and T. S. Arun Samuel. "Design and Development of an Efficient Branch Predictor for an In-order RISC-V Processor." Journal of Nano- and Electronic Physics 12, no. 5 (2020): 05021–1. http://dx.doi.org/10.21272/jnep.12(5).05021.
Повний текст джерелаRAO, Jinli, Tianyong AO, Shu XU, Kui DAI, and Xuecheng ZOU. "Design Exploration of SHA-3 ASIP for IoT on a 32-bit RISC-V Processor." IEICE Transactions on Information and Systems E101.D, no. 11 (November 1, 2018): 2698–705. http://dx.doi.org/10.1587/transinf.2017icp0019.
Повний текст джерелаXin, Guozhu, Jun Han, Tianyu Yin, Yuchao Zhou, Jianwei Yang, Xu Cheng, and Xiaoyang Zeng. "VPQC: A Domain-Specific Vector Processor for Post-Quantum Cryptography Based on RISC-V Architecture." IEEE Transactions on Circuits and Systems I: Regular Papers 67, no. 8 (August 2020): 2672–84. http://dx.doi.org/10.1109/tcsi.2020.2983185.
Повний текст джерелаCho, Hyungmin. "Correction to “Impact of Microarchitectural Differences of RISC-V Processor Cores on Soft Error Effects”." IEEE Access 7 (2019): 35034. http://dx.doi.org/10.1109/access.2019.2904033.
Повний текст джерелаZhou, Yuzhi, Xi Jin, Tian Xiang, and Daolu Zha. "Enhancing energy efficiency of RISC-V processor-based embedded graphics systems through frame buffer compression." Microprocessors and Microsystems 77 (September 2020): 103140. http://dx.doi.org/10.1016/j.micpro.2020.103140.
Повний текст джерелаLe, Anh-Tien, Trong-Thuc Hoang, Ba-Anh Dao, Akira Tsukamoto, Kuniyasu Suzaki, and Cong-Kha Pham. "A cross-process Spectre attack via cache on RISC-V processor with trusted execution environment." Computers and Electrical Engineering 105 (January 2023): 108546. http://dx.doi.org/10.1016/j.compeleceng.2022.108546.
Повний текст джерелаZhou, Ziqiao, and Michael K. Reiter. "Interpretable noninterference measurement and its application to processor designs." Proceedings of the ACM on Programming Languages 5, OOPSLA (October 20, 2021): 1–30. http://dx.doi.org/10.1145/3485518.
Повний текст джерелаChen, Yuehai, Huarun Chen, Shaozhen Chen, Chao Han, Wujian Ye, Yijun Liu, and Huihui Zhou. "DITES: A Lightweight and Flexible Dual-Core Isolated Trusted Execution SoC Based on RISC-V." Sensors 22, no. 16 (August 10, 2022): 5981. http://dx.doi.org/10.3390/s22165981.
Повний текст джерелаTaştan, İbrahim, Mahmut Karaca, and Arda Yurdakul. "Approximate CPU Design for IoT End-Devices with Learning Capabilities." Electronics 9, no. 1 (January 9, 2020): 125. http://dx.doi.org/10.3390/electronics9010125.
Повний текст джерелаHan, Xiaojing, Liang Liu, Zhe Zhang, Yufeng Sun, Jiahui Zhou, and Hao Cai. "Design of a High Performance Vector Processor Based on RISIC-V Architecture." Journal of Physics: Conference Series 2560, no. 1 (August 1, 2023): 012027. http://dx.doi.org/10.1088/1742-6596/2560/1/012027.
Повний текст джерелаMach, Ján, Lukáš Kohútka, and Pavel Čičák. "In-Pipeline Processor Protection against Soft Errors." Journal of Low Power Electronics and Applications 13, no. 2 (May 10, 2023): 33. http://dx.doi.org/10.3390/jlpea13020033.
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