Статті в журналах: "RISC V processor"

1

Pitcher, Graham. "RISC-V Powers IoT Apps Processor." New Electronics 51, no. 4 (February 27, 2018): 7. http://dx.doi.org/10.12968/s0047-9624(23)60141-5.

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2

Gamino del Río, Iván, Agustín Martínez Hellín, Óscar R. Polo, Miguel Jiménez Arribas, Pablo Parra, Antonio da Silva, Jonatan Sánchez, and Sebastián Sánchez. "A RISC-V Processor Design for Transparent Tracing." Electronics 9, no. 11 (November 7, 2020): 1873. http://dx.doi.org/10.3390/electronics9111873.

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Code instrumentation enables the observability of an embedded software system during its execution. A usage example of code instrumentation is the estimation of “worst-case execution time” using hybrid analysis. This analysis combines static code analysis with measurements of the execution time on the deployment platform. Static analysis of source code determines where to insert the tracing instructions, so that later, the execution time can be captured using a logic analyser. The main drawback of this technique is the overhead introduced by the execution of trace instructions. This paper proposes a modification of the architecture of a RISC pipelined processor that eliminates the execution time overhead introduced by the code instrumentation. In this way, it allows the tracing to be non-intrusive, since the sequence and execution times of the program under analysis are not modified by the introduction of traces. As a use case of the proposed solution, a processor, based on RISC-V architecture, was implemented using VHDL language. The processor, synthesized on a FPGA, was used to execute and evaluate a set of examples of instrumented code generated by a “worst-case execution time” estimation tool. The results validate that the proposed architecture executes the instrumented code without overhead.

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3

Hongsheng, Zhang, Zekun Jiang, and Yong Li. "Design of a dual-issue RISC-V processor." Journal of Physics: Conference Series 1693 (December 2020): 012192. http://dx.doi.org/10.1088/1742-6596/1693/1/012192.

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4

An, Hyogeun, Sudong Kang, Guard Kanda, and Kwangki Ryoo. "RISC-V Hardware Synthesizable Processor Design Test and Verification Using User-Friendly Desktop Application." Webology 19, no. 1 (January 20, 2022): 4597–620. http://dx.doi.org/10.14704/web/v19i1/web19305.

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Although the RISC-V ISA has not been around for long, it is a processor architecture that has been highlighted by many businesses and individuals for its low-cost and rapid pace of development. They are open-source-synthesizable hardware processors with minimal functionality that is ideal for current IoT applications involving simple sensors and actuator controls. Due to some qualities of hardware, they can operate in areas where software programs and applications cannot be used whereas, these software programs that run on such hardware equally help in understanding how hardware operates. This paper, therefore, proposes and discusses the design, implementation, and internal verification and test platform for a Reduced Instruction Set Code-V’s (RISC-V) Instruction Set Architecture (ISA), using an interactive desktop program for a 32-bit single-cycle processor. This paper developed a system that functions as interactive assistance to RISC-V's ISA design and debugger using a more user-friendly desktop UI application. The uniqueness of this design is the flexibility of testing and debugging that is possible through either the software interface or through hardware peripherals such as Universal Asynchronous Receiver/Transmitter (UART) protocols in FPGA or even both. These peripherals allow users to view the contents of the register files and RAM being utilized by the implemented processor on the FPGA. The proposed desktop User Interface program monitors and controls the sequential processing and states of a 32-bit single-cycle RISC-V processor’s operation on an FPGA. Contents of the proposed processor’s registers and memory are displayed alongside other temporal or internal data. Internal components such as Program Counters (PC), Random Access Memory (RAM), are displayed all through the proposed User Interface (UI) program and also through various peripherals on the FPGA board. The software program is implemented using C# programing language through Microsoft Visual Studio 2019 Integrated Development Environment (IDE). The proposed hardware synthesizable processor core is implemented using Verilog Hardware Description Language (HDL) and synthesized with Xilinx Integrated Synthesis Environment (ISE) version 14.7. The proposed processor and its corresponding hardware test modules occupy 6476 Look-Up-Tables (LUT) and operate at a maximum frequency of 49MHz and its operation is verified on a Field Programmable Gate Array (FPGA). The proposed processor and its test platform can serve as a good educational tool as well as a help for processor design engineers both experienced and beginners.

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5

Núñez-Prieto, Ricardo, David Castells-Rufas, and Lluís Terés-Terés. "RisCO2: Implementation and Performance Evaluation of RISC-V Processors for Low-Power CO2 Concentration Sensing." Micromachines 14, no. 7 (July 4, 2023): 1371. http://dx.doi.org/10.3390/mi14071371.

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In the field of embedded systems, energy efficiency is a critical requirement, particularly for battery-powered devices. RISC-V processors have gained popularity due to their flexibility and open-source nature, making them an attractive choice for embedded applications. However, not all RISC-V processors are equally energy-efficient, and evaluating their performance in specific use cases is essential. This paper presents RisCO2, an RISC-V implementation optimized for energy efficiency. It evaluates its performance compared to other RISC-V processors in terms of resource utilization and energy consumption in a signal processing application for nondispersive infrared (NDIR) CO2 sensors.The processors were implemented in the PULPino SoC and synthesized using Vivado IDE. RisCO2 is based on the RV32E_Zfinx instruction set and was designed from scratch by the authors specifically for low-power signal demodulation in CO2 NDIR sensors. The other processors are Ri5cy, Micro-riscy, and Zero-riscy, developed by the PULP team, and CV32E40P (derived from Ri5cy) from the OpenHW Group, all of them widely used in the RISC-V community. Our experiments showed that RisCO2 had the lowest energy consumption among the five processors, with a 53.5% reduction in energy consumption compared to CV32E40P and a 94.8% reduction compared to Micro-riscy. Additionally, RisCO2 had the lowest FPGA resource utilization compared to the best-performing processors, CV32E40P and Ri5cy, with a 46.1% and a 59% reduction in LUTs, respectively. Our findings suggest that RisCO2 is a highly energy-efficient RISC-V processor for NDIR CO2 sensors that require signal demodulation to enhance the accuracy of the measurements. The results also highlight the importance of evaluating processors in specific use cases to identify the most energy-efficient option. This paper provides valuable insights for designers of energy-efficient embedded systems using RISC-V processors.

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6

Michel Deves de Souza, Eduardo, Nathalia Nathalia Adriana de Oliveira, Douglas Almeida dos Santos Almeida dos Santos, and Douglas Rossi de Melo. "RVSH - Um processador RISC-V para fins didáticos." Anais do Computer on the Beach 14 (May 3, 2023): 450–52. http://dx.doi.org/10.14210/cotb.v14.p450-452.

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ABSTRACTEmbedded systems constitute the class of computers that presentthe most significant volume and are increasingly present ineveryday life. The main element of these systems is the processor,which can be found in discrete form, represented by a physicalcomponent, or cores, as used in programmable logic devices.Processors of the same architecture share the same instructionset but may differ in the organization’s implementation. RISC(Reduced Instruction Set Computer) is the class of architecturesthat favors a simple, reduced instruction set. RISC-V is an exampleof such architecture, which consists of an initiative by academiaand industry to be open and free, aiming for easy and optimizedimplementations. However, due to the recent disclosure of itsfeatures and specifications, RISC-V needs more reference materialfor digital and embedded system designs. This work proposesthe RVSH, a simple RISC-V processor for teaching and researchactivities. The implementation aims to allow the adoption of thisarchitecture in topics such as digital systems, computer architecture,microcontrollers, and embedded systems design.

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7

Zhou, Weixin, Dehua Wu, Wan’ang Xiao, Shan Gao, and Wanlin Gao. "A Novel Sleep Scheduling Strategy on RISC-V Processor." Journal of Physics: Conference Series 1631 (September 2020): 012028. http://dx.doi.org/10.1088/1742-6596/1631/1/012028.

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8

Xue, Wang, Liu, Lv, Wang, and Zeng. "An RISC-V Processor with Area-Efficient Memristor-Based In-Memory Computing for Hash Algorithm in Blockchain Applications." Micromachines 10, no. 8 (August 16, 2019): 541. http://dx.doi.org/10.3390/mi10080541.

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Blockchain technology is increasingly being used in Internet of things (IoT) devices for information security and data integrity. However, it is challenging to implement complex hash algorithms with limited resources in IoT devices owing to large energy consumption and a long processing time. This paper proposes an RISC-V processor with memristor-based in-memory computing (IMC) for blockchain technology in IoT applications. The IMC-adapted instructions were designed for the Keccak hash algorithm by virtue of the extendibility of the RISC-V instruction set architecture (ISA). Then, an RISC-V processor with area-efficient memristor-based IMC was developed based on an open-source core for IoT applications, Hummingbird E200. The general compiling policy with the data allocation method is also disclosed for the IMC implementation of the Keccak hash algorithm. An evaluation shows that >70% improvements in both performance and energy saving were achieved with limited area overhead after introducing IMC in the RISC-V processor.

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9

Santos, Douglas A., André M. P. Mattos, Douglas R. Melo, and Luigi Dilillo. "Enhancing Fault Awareness and Reliability of a Fault-Tolerant RISC-V System-on-Chip." Electronics 12, no. 12 (June 6, 2023): 2557. http://dx.doi.org/10.3390/electronics12122557.

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Recent research has shown interest in adopting the RISC-V processors for high-reliability electronics, such as aerospace applications. The openness of this architecture enables the implementation and customization of the processor features to increase their reliability. Studies on hardened RISC-V processors facing harsh radiation environments apply fault tolerance techniques in the processor core and peripherals, exploiting system redundancies. In prior work, we present a hardened RISC-V System-on-Chip (SoC), which could detect and correct radiation-induced faults with limited fault awareness. Therefore, in this work, we propose solutions to extend the fault observability of the SoC implementation by providing error detection and monitoring. For this purpose, we introduce observation features in the redundant structures of the system, enabling the report of valuable information that supports enhanced radiation testing and support the application to perform actions to recover from critical failures. Thus, the main contribution of this work is a solution to improve fault awareness and the analysis of the fault models in the system. In order to validate this solution, we performed complementary experiments in two irradiation facilities, comprehending atmospheric neutrons and a mixed-field environment, in which the system proved to be valuable for analyzing the radiation effects on the processor core and its peripherals. In these experiments, we were able to obtain a range of error reports that allowed us to gain a deeper understanding of the faults mechanisms, as well as improve the characterization of the SoC.

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10

Gomes, Tiago, Pedro Sousa, Miguel Silva, Mongkol Ekpanyapong, and Sandro Pinto. "FAC-V: An FPGA-Based AES Coprocessor for RISC-V." Journal of Low Power Electronics and Applications 12, no. 4 (September 27, 2022): 50. http://dx.doi.org/10.3390/jlpea12040050.

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In the new Internet of Things (IoT) era, embedded Field-Programmable Gate Array (FPGA) technology is enabling the deployment of custom-tailored embedded IoT solutions for handling different application requirements and workloads. Combined with the open RISC-V Instruction Set Architecture (ISA), the FPGA technology provides endless opportunities to create reconfigurable IoT devices with different accelerators and coprocessors tightly and loosely coupled with the processor. When connecting IoT devices to the Internet, secure communications and data exchange are major concerns. However, adding security features requires extra capabilities from the already resource-constrained IoT devices. This article presents the FAC-V coprocessor, which is an FPGA-based solution for an RISC-V processor that can be deployed following two different coupling styles. FAC-V implements in hardware the Advanced Encryption Standard (AES), one of the most widely used cryptographic algorithms in IoT low-end devices, at the cost of few FPGA resources. The conducted experiments demonstrate that FAC-V can achieve performance improvements of several orders of magnitude when compared to the software-only AES implementation; e.g., encrypting a message of 16 bytes with AES-256 can reach a performance gain of around 8000× with an energy consumption of 0.1 μJ.

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11

Pietzsch, Marcus. "RISC-V Processor for Network Platforms According to ISO 26262." ATZelectronics worldwide 16, no. 11 (November 2021): 8–13. http://dx.doi.org/10.1007/s38314-021-0691-y.

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12

Gao, Shan, Wan’ang Xiao, Zhenghong Yang, Dehua Wu, and Wanlin Gao. "A fast on-chip debugging design for RISC-V processor." Journal of Physics: Conference Series 1976, no. 1 (July 1, 2021): 012056. http://dx.doi.org/10.1088/1742-6596/1976/1/012056.

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13

Cheng, Yuan-Hu, Li-Bo Huang, Yi-Jun Cui, Sheng Ma, Yong-Wen Wang, and Bing-Cai Sui. "RV16: An Ultra-Low-Cost Embedded RISC-V Processor Core." Journal of Computer Science and Technology 37, no. 6 (November 30, 2022): 1307–19. http://dx.doi.org/10.1007/s11390-022-0910-x.

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14

Jamieson, Peter, Huan Le, Nathan Martin, Tyler McGrew, Yicheng Qian, Eric Schonauer, Alan Ehret, and Michel A. Kinsy. "Computer Engineering Education Experiences with RISC-V Architectures—From Computer Architecture to Microcontrollers." Journal of Low Power Electronics and Applications 12, no. 3 (August 9, 2022): 45. http://dx.doi.org/10.3390/jlpea12030045.

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With the growing popularity of RISC-V and various open-source released RISC-V processors, it is now possible for computer engineers students to explore this simple and relevant architecture, and also, these students can explore and design a microcontroller at a low-level using real tool-flows and implement and test their hardware. In this work, we describe our experiences with undergraduate engineers building RISC-V architectures on an FPGA and then extending their experiences to implement an Arduino-like RISC-V tool-flow and the respective hardware and software to handle input-output ports, interrupts, hardware timers, and communication protocols. The microcontroller is implemented on an FPGA as a Senior Design project to test the viability of such efforts. In this work, we will explain how undergraduates can achieve these experiences including preparation for these projects, the tool-flows they use, the challenges in understanding and extending a RISC-V processor with microcontroller functionality, and a suggestion of how to integrate this learning into an existing curriculum, including a discussion on if we should include these deeper experiences in the Computer Engineering undergraduate curriculum.

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15

B, Rajeshwari, Rithvik Kumar, Shweta P. Hegde, Manav Eswar Prasad, Vandhya D M, and Bajrangabali B. "Dual Quaternion Hardware Accelerator for RISC-V based System." International Journal of Research and Scientific Innovation 09, no. 05 (2022): 77–81. http://dx.doi.org/10.51244/ijrsi.2022.9506.

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In this work, a hardware accelerator has been developed for a RISC-V processor. The ‘Parashu’ Shakti processor is the SoC of choice for application testing and development. The IP is designed to speed up applications involving dual quaternion operations. Our module primarily aids dual quaternion multiplication which further helps with other complex operations like translation, rotation and transformation. Two solutions have been proposed for the same, i.e. either a quaternion IP if power and resource utilization is a concern, or a dual quaternion IP if performance gain is the primary objective. The latter is however at the expense of relatively more resource utilization. The former IP takes longer execution time to perform the same task but is more versatile since it can be used in applications involving both quaternion and dual quaternion operations.

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16

Lim, Seung-Ho, WoonSik William Suh, Jin-Young Kim, and Sang-Young Cho. "RISC-V Virtual Platform-Based Convolutional Neural Network Accelerator Implemented in SystemC." Electronics 10, no. 13 (June 23, 2021): 1514. http://dx.doi.org/10.3390/electronics10131514.

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The optimization for hardware processor and system for performing deep learning operations such as Convolutional Neural Networks (CNN) in resource limited embedded devices are recent active research area. In order to perform an optimized deep neural network model using the limited computational unit and memory of an embedded device, it is necessary to quickly apply various configurations of hardware modules to various deep neural network models and find the optimal combination. The Electronic System Level (ESL) Simulator based on SystemC is very useful for rapid hardware modeling and verification. In this paper, we designed and implemented a Deep Learning Accelerator (DLA) that performs Deep Neural Network (DNN) operation based on the RISC-V Virtual Platform implemented in SystemC in order to enable rapid and diverse analysis of deep learning operations in an embedded device based on the RISC-V processor, which is a recently emerging embedded processor. The developed RISC-V based DLA prototype can analyze the hardware requirements according to the CNN data set through the configuration of the CNN DLA architecture, and it is possible to run RISC-V compiled software on the platform, can perform a real neural network model like Darknet. We performed the Darknet CNN model on the developed DLA prototype, and confirmed that computational overhead and inference errors can be analyzed with the DLA prototype developed by analyzing the DLA architecture for various data sets.

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17

Gao, Shan, Dehua Wu, Wan’ang Xiao, Zetao Wang, Zhenghong Yang, and Wanlin Gao. "A novel method for on-chip debugging based on RISC-V processor." MATEC Web of Conferences 355 (2022): 03055. http://dx.doi.org/10.1051/matecconf/202235503055.

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An on-chip debugging method based on the RISC-V processor is introduced, which simplifies the complicated debugging operation into instructions and improves the debugging efficiency effectively. The method adopts a JTAG interface to realize the debugging functions of the processor, such as running control, software breakpoint, hardware breakpoint and single-step execution. The method was verified by simulation at the RTL level, and the logic synthesis was carried out in SMIC 180nm process library.

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18

MIYAZAKI, Hiromu, Takuto KANAMORI, Md Ashraful ISLAM, and Kenji KISE. "RVCoreP: An Optimized RISC-V Soft Processor of Five-Stage Pipelining." IEICE Transactions on Information and Systems E103.D, no. 12 (December 1, 2020): 2494–503. http://dx.doi.org/10.1587/transinf.2020pap0015.

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19

Li, Jiemin, Shancong Zhang, and Chong Bao. "DuckCore: A Fault-Tolerant Processor Core Architecture Based on the RISC-V ISA." Electronics 11, no. 1 (December 30, 2021): 122. http://dx.doi.org/10.3390/electronics11010122.

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With the development of large-scale CMOS-integrated circuit manufacturing technology, microprocessor chips are more vulnerable to soft errors and radiation interference, resulting in reduced reliability. Core reliability is an important element of the microprocessor’s ability to resist soft errors. This paper proposes DuckCore, a fault-tolerant processor core architecture based on the free and open instruction set architecture (ISA) RISC-V. This architecture uses improved SECDED (single error correction, double error detection) code between pipelines, detects processor operating errors in real-time through the Supervision unit, and takes instruction rollbacks for different error types, which not only saves resources but also improves the reliability of the processor core. In the implementation process, all error injection tests are passed to verify the completeness of the function. In order to better verify the performance of the processor under different error intensity injections, the software is used to inject errors, the running program is run on the FPGA (Field Programmable Gate Array), and the impact of the actual radiation environment on the architecture is evaluated through the results. The architecture is applied to three–five-stage open-source processor cores and the results show that this method consumes fewer resources and its discrete design makes it more portable.

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20

Patrick, Mark. "What's all the Hype About?" New Electronics 53, no. 14 (August 11, 2020): 22–23. http://dx.doi.org/10.12968/s0047-9624(22)61362-2.

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21

Kwon, Donghyun, Dongil Hwang, and Yunheung Paek. "A Hardware Platform for Ensuring OS Kernel Integrity on RISC-V." Electronics 10, no. 17 (August 26, 2021): 2068. http://dx.doi.org/10.3390/electronics10172068.

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The OS kernel is typically preassumed as a trusted computing base in most computing systems. However, it also implies that once an attacker takes control of the OS kernel, the attacker can seize the entire system. Because of such security importance of the OS kernel, many works have proposed security solutions for the OS kernel using an external hardware module located outside the processor. By doing this, these works can realize the physical isolation of security solutions from the OS kernel running in the processor, but they cannot access the inner state of the processor, which attackers can manipulate. Thus, they elaborated several methods to overcome such limited capability of external hardware. However, those methods usually come with several side effects, such as high-performance overhead, kernel code modifications, and/or excessively complicated hardware designs. In this paper, we introduce RiskiM, a new hardware-based monitoring platform to ensure kernel integrity from outside the host system. To deliver the inner state of the host to RiskiM, we have devised a hardware interface architecture, called PEMI. Through PEMI, RiskiM is supplied with all internal states of the host system essential for fulfilling its monitoring task to protect the kernel. To empirically validate our monitoring platform’s security strength and performance, we have fully implemented PEMI and RiskiM on a RISC-V based processor and FPGA, respectively. Our experiments show that RiskiM succeeds in the host kernel protection by detecting even the advanced attacks which could circumvent previous solutions, yet suffering from virtually no aforementioned side effects.

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22

Cococcioni, Marco, Federico Rossi, Emanuele Ruffaldi, and Sergio Saponara. "Vectorizing posit operations on RISC-V for faster deep neural networks: experiments and comparison with ARM SVE." Neural Computing and Applications 33, no. 16 (February 28, 2021): 10575–85. http://dx.doi.org/10.1007/s00521-021-05814-0.

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AbstractWith the arrival of the open-source RISC-V processor architecture, there is the chance to rethink Deep Neural Networks (DNNs) and information representation and processing. In this work, we will exploit the following ideas: i) reduce the number of bits needed to represent the weights of the DNNs using our recent findings and implementation of the posit number system, ii) exploit RISC-V vectorization as much as possible to speed up the format encoding/decoding, the evaluation of activations functions (using only arithmetic and logic operations, exploiting approximated formulas) and the computation of core DNNs matrix-vector operations. The comparison with the well-established architecture ARM Scalable Vector Extension is natural and challenging due to its closedness and mature nature. The results show how it is possible to vectorize posit operations on RISC-V, gaining a substantial speed-up on all the operations involved. Furthermore, the experimental outcomes highlight how the new architecture can catch up, in terms of performance, with the more mature ARM architecture. Towards this end, the present study is important because it anticipates the results that we expect to achieve when we will have an open RISC-V hardware co-processor capable to operate natively with posits.

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23

Li, Zhiyu, Yuhao Huang, Longfeng Tian, Ruimin Zhu, Shanlin Xiao, and Zhiyi Yu. "A Low-Power Asynchronous RISC-V Processor With Propagated Timing Constraints Method." IEEE Transactions on Circuits and Systems II: Express Briefs 68, no. 9 (September 2021): 3153–57. http://dx.doi.org/10.1109/tcsii.2021.3100524.

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Murabayashi, F., T. Yamauchi, H. Yamada, T. Nishiyama, K. Shimamura, S. Tanaka, T. Hotta, T. Shimizu, and H. Sawamoto. "2.5 V CMOS circuit techniques for a 200 MHz superscalar RISC processor." IEEE Journal of Solid-State Circuits 31, no. 7 (July 1996): 972–80. http://dx.doi.org/10.1109/4.508211.

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Zhang, Haifeng, Xiaoti Wu, Yuyu Du, Hongqing Guo, Chuxi Li, Yidong Yuan, Meng Zhang, and Shengbing Zhang. "A Heterogeneous RISC-V Processor for Efficient DNN Application in Smart Sensing System." Sensors 21, no. 19 (September 28, 2021): 6491. http://dx.doi.org/10.3390/s21196491.

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Extracting features from sensing data on edge devices is a challenging application for which deep neural networks (DNN) have shown promising results. Unfortunately, the general micro-controller-class processors which are widely used in sensing system fail to achieve real-time inference. Accelerating the compute-intensive DNN inference is, therefore, of utmost importance. As the physical limitation of sensing devices, the design of processor needs to meet the balanced performance metrics, including low power consumption, low latency, and flexible configuration. In this paper, we proposed a lightweight pipeline integrated deep learning architecture, which is compatible with open-source RISC-V instructions. The dataflow of DNN is organized by the very long instruction word (VLIW) pipeline. It combines with the proposed special intelligent enhanced instructions and the single instruction multiple data (SIMD) parallel processing unit. Experimental results show that total power consumption is about 411 mw and the power efficiency is about 320.7 GOPS/W.

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26

Schmidt, Colin, John Wright, Zhongkai Wang, Eric Chang, Albert Ou, Woorham Bae, Sean Huang, et al. "An Eight-Core 1.44-GHz RISC-V Vector Processor in 16-nm FinFET." IEEE Journal of Solid-State Circuits 57, no. 1 (January 2022): 140–52. http://dx.doi.org/10.1109/jssc.2021.3118046.

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27

Tada, Jubee, and Keiichi Sato. "An Implementation of a Grid Square Codes Generator on a RISC-V Processor." International Journal of Networking and Computing 12, no. 1 (2022): 204–17. http://dx.doi.org/10.15803/ijnc.12.1_204.

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28

de Oliveira, Adria B., Lucas A. Tambara, Fabio Benevenuti, Luis A. C. Benites, Nemitala Added, Vitor A. P. Aguiar, Nilberto H. Medina, Marcilei A. G. Silveira, and Fernanda L. Kastensmidt. "Evaluating Soft Core RISC-V Processor in SRAM-Based FPGA Under Radiation Effects." IEEE Transactions on Nuclear Science 67, no. 7 (July 2020): 1503–10. http://dx.doi.org/10.1109/tns.2020.2995729.

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29

Cho, Hyungmin. "Impact of Microarchitectural Differences of RISC-V Processor Cores on Soft Error Effects." IEEE Access 6 (2018): 41302–13. http://dx.doi.org/10.1109/access.2018.2858773.

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30

Kaneko, Hiroaki, and Akinori Kanasugi. "An integrated machine code monitor for a RISC-V processor on an FPGA." Artificial Life and Robotics 25, no. 3 (March 9, 2020): 427–33. http://dx.doi.org/10.1007/s10015-020-00593-8.

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Garofalo, Angelo, Manuele Rusci, Francesco Conti, Davide Rossi, and Luca Benini. "PULP-NN: accelerating quantized neural networks on parallel ultra-low-power RISC-V processors." Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences 378, no. 2164 (December 23, 2019): 20190155. http://dx.doi.org/10.1098/rsta.2019.0155.

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We present PULP-NN, an optimized computing library for a parallel ultra-low-power tightly coupled cluster of RISC-V processors. The key innovation in PULP-NN is a set of kernels for quantized neural network inference, targeting byte and sub-byte data types, down to INT-1, tuned for the recent trend toward aggressive quantization in deep neural network inference. The proposed library exploits both the digital signal processing extensions available in the PULP RISC-V processors and the cluster’s parallelism, achieving up to 15.5 MACs/cycle on INT-8 and improving performance by up to 63 × with respect to a sequential implementation on a single RISC-V core implementing the baseline RV32IMC ISA. Using PULP-NN, a CIFAR-10 network on an octa-core cluster runs in 30 × and 19.6 × less clock cycles than the current state-of-the-art ARM CMSIS-NN library, running on STM32L4 and STM32H7 MCUs, respectively. The proposed library, when running on a GAP-8 processor, outperforms by 36.8 × and by 7.45 × the execution on energy efficient MCUs such as STM32L4 and high-end MCUs such as STM32H7 respectively, when operating at the maximum frequency. The energy efficiency on GAP-8 is 14.1 × higher than STM32L4 and 39.5 × higher than STM32H7, at the maximum efficiency operating point. This article is part of the theme issue ‘Harmonizing energy-autonomous computing and intelligence’.

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32

C, Rohan. "Design of a 32-Bit, Dual Pipeline Superscalar RISC-V Processor on FPGA: A Review." International Journal for Research in Applied Science and Engineering Technology 10, no. 6 (June 30, 2022): 4044–46. http://dx.doi.org/10.22214/ijraset.2022.44654.

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Abstract: A 40 MHz with 32-bit and 5-stage dual-pipeline superscalar processor based on RISC-V Instruction Set Architecture is presented. It supports integer, multiply-divide and atomic read-modify-write operations. The proposed system implements inorder issuing of instructions. The design includes a dynamic branch prediction unit, memory subsystem with virtual memory, separate instruction cache and data cache, integer and floating-point execution units, interrupt controller, error control module, and a UART peripheral. Individual interrupts can have up to four levels of primary priority set in the interrupt controller. For the main memory, the error control module provides single error correction and double error detection. For on-chip communication, the Wishbone B.3 bus standard is used. On a Virtex-7 XC7VX485T FFG 1761-2 FPGA-based board, the processor is implemented. The architecture has CoreMark and Dhrystone benchmark ratings of 3.84/MHz and 1.0603 DMIPS/MHz, respectively

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Yu, Hongjiang, Guoshun Yuan, Dewei Kong, and Chuhuai Chen. "An Optimized Implementation of Activation Instruction Based on RISC-V." Electronics 12, no. 9 (April 24, 2023): 1986. http://dx.doi.org/10.3390/electronics12091986.

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Activation is an important component of the neural network, and the standard instructions of RISC-V are difficult to use to effectively handle the activation of the array. In this paper, we propose an optimized implementation of activation instruction based on RISC-V. Based on the opensource RISC-V processor Hummingbird E203, we designed a special instruction for the implementation of activation functions. A single instruction is chosen to implement the entire activation operation, including data loading, data arithmetic and data write-back. At the hardware level, we designed a method of alternate reading and writing that only needs a small hardware storage unit to meet the requirements of the activation operation for long arrays without affecting the activation efficiency. In addition, we added the length of the array as a new parameter to instruct our designed hardware to adapt to any length of arrays. Finally, the scheduling method of some instructions in the activation process was optimized in accordance with the law of instructions, which improves the execution efficiency of instructions. Considering an activation process with an array length of 15, our design demonstrates a 4.89-fold increase in speed compared to RISC-V standard instructions while consuming only 7.78% of the energy.

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Kalapothas, Stavros, Manolis Galetakis, Georgios Flamis, Fotis Plessas, and Paris Kitsos. "A Survey on RISC-V-Based Machine Learning Ecosystem." Information 14, no. 2 (January 21, 2023): 64. http://dx.doi.org/10.3390/info14020064.

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In recent years, the advancements in specialized hardware architectures have supported the industry and the research community to address the computation power needed for more enhanced and compute intensive artificial intelligence (AI) algorithms and applications that have already reached a substantial growth, such as in natural language processing (NLP) and computer vision (CV). The developments of open-source hardware (OSH) and the contribution towards the creation of hardware-based accelerators with implication mainly in machine learning (ML), has also been significant. In particular, the reduced instruction-set computer-five (RISC-V) open standard architecture has been widely adopted by a community of researchers and commercial users, worldwide, in numerous openly available implementations. The selection through a plethora of RISC-V processor cores and the mix of architectures and configurations combined with the proliferation of ML software frameworks for ML workloads, is not trivial. In order to facilitate this process, this paper presents a survey focused on the assessment of the ecosystem that entails RISC-V based hardware for creating a classification of system-on-chip (SoC) and CPU cores, along with an inclusive arrangement of the latest released frameworks that have supported open hardware integration for ML applications. Moreover, part of this work is devoted to the challenges that are concerned, such as power efficiency and reliability, when designing and building application with OSH in the AI/ML domain. This study presents a quantitative taxonomy of RISC-V SoC and reveals the opportunities in future research in machine learning with RISC-V open-source hardware architectures.

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35

Jaiswal, Nidhi. "Design of High Performance Core Micro-Architecture Based on RISC-V ISA for Low Power Applications." International Journal for Research in Applied Science and Engineering Technology 11, no. 7 (July 31, 2023): 734–42. http://dx.doi.org/10.22214/ijraset.2023.54647.

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Abstract: Numerous current and future applications aim to create highly efficient central processing units (CPUs). The RISC V processor micro-architecture is one illustration of a design that satisfies the necessities. The RISC-V Instruction Set Architecture [ISA] provides support for the micro-architecture. The instruction set architecture and the micro-architecture of a processor are two of the most crucial aspects of its design. The multiplier and divider circuits have a relatively high level of hardware complexity compared to other stages of the instruction execution process, which must be taken into account in any core microarchitecture. The construction of an appropriate hardware circuit that is capable of multiplication and division determines the overall size, power, and performance of a core. This center has four phases, and during those stages, each guidance is done, except for stacking and putting away information. The arithmetic operations can be completed within one clock cycle. On the other hand, the division and multiplication operations are repeated in an effort to shorten the critical path latency.

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36

GuangTang, Jiancheng, and Li. "Research and design of low-power, high-performance processor based on RISC-V instruction set architecture." Journal of Physics: Conference Series 2221, no. 1 (May 1, 2022): 012008. http://dx.doi.org/10.1088/1742-6596/2221/1/012008.

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Abstract In embedded IoT applications, in order to meet the needs of small area, low power consumption, and high performance, this paper designs a 32-bit low-power, high-performance microprocessor based on the RISC-V instruction set architecture. It uses a 3-stage pipeline structure with static branch prediction function, supports RV32IM instruction set, and adopts AHB bus as the control bus. The logic function of the processor was verified under the iverilog environment, and the simulation results showed that the processor can run normally. The CoreMark score of 2.38 CoreMark/MHz was measured by running the CoreMark running program, and it supports FreeRTOS transplantation. The analysis and verification results show that the design can be well applied to small-area, low-power embedded application scenarios.

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Ragini, Dr K., and Nidhi Jaiswal. "Design of High-Performance Core Micro-Architecture Based on 32- Bit RISC-V Instruction Set Architecture [ISA]." International Journal for Research in Applied Science and Engineering Technology 11, no. 7 (July 31, 2023): 1025–33. http://dx.doi.org/10.22214/ijraset.2023.54791.

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Abstract: A wide range of present and future applications strive to develop highly efficient central processing units (CPUs). One particular design that meets these requirements is the RISC V processor micro-architecture. The RISC-V Instruction Set Architecture (ISA) provides the necessary support for this micro-architecture. The instruction set architecture and microarchitecture are crucial components in processor design. Among these components, the multiplier and divider circuits exhibit a relatively high level of hardware complexity compared to other stages of instruction execution. Therefore, it is essential to consider these factors when designing the core micro-architecture. The size, power, and performance of a core are determined by the construction of an appropriate hardware circuit capable of handling multiplication and division operations. The core consists of four phases, with each instruction being executed within these stages, except for data storage and retrieval. Arithmetic operations can be completed within a single clock cycle. However, division and multiplication operations are repeated in order to reduce the latency of the critical path.

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Nişancı, Görkem, Paul G. Flikkema, and Tolga Yalçın. "Symmetric Cryptography on RISC-V: Performance Evaluation of Standardized Algorithms." Cryptography 6, no. 3 (August 10, 2022): 41. http://dx.doi.org/10.3390/cryptography6030041.

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The ever-increasing need for securing computing systems using cryptographic algorithms is spurring interest in the efficient implementation of common algorithms. While the algorithms can be implemented in software using base instruction sets, there is considerable potential to reduce memory cost and improve speed using specialized instructions and associated hardware. However, there is a need to assess the benefits and costs of software implementations and new instructions that implement key cryptographic algorithms in fewer cycles. The primary aim of this paper is to improve the understanding of the performance and cost of implementing cryptographic algorithms for the RISC-V instruction set architecture (ISA) in two cases: software implementations of the algorithms using the rv32i instruction set and using cryptographic instructions supported by dedicated hardware in additional functional units. For both cases, we describe a RISC-V processor with cryptography hardware extensions and hand-optimized RISC-V assembly language implementations of eleven cryptographic algorithms. Compared to implementations with only the rv32i instruction set, implementations with the cryptography set extension provide a 1.5× to 8.6× faster execution speed and 1.2× to 5.8× less program memory for five of the eleven algorithms. Based on our performance analyses, a new instruction is proposed to increase the implementation efficiency of the algorithms.

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39

Andorno, M., M. Andersen, G. Borghello, A. Caratelli, D. Ceresa, J. Dhaliwal, K. Kloukinas, and R. Pejasinovic. "Rad-hard RISC-V SoC and ASIP ecosystems studies for high-energy physics applications." Journal of Instrumentation 18, no. 01 (January 1, 2023): C01018. http://dx.doi.org/10.1088/1748-0221/18/01/c01018.

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Abstract The increase in complexity and size of modern ASIC designs in the HEP community and the use of advanced semiconductor fabrication processes raises the need for a shift toward a more abstract design methodology, that takes advantage of modularity and programmability to achieve a faster turnaround time both for design and verification. This contribution will present two complementary approaches, one using a RISC-V based System-on-Chip (SoC) and the other based on Application-Specific Instruction set Processors (ASIP). The SoC uses the PicoRV32 open-source RISC-V core and a rad-hard version of the AMBA APB bus to connect peripherals and is primarily geared towards control and monitoring applications. This solution is a demonstrator of what can become a more complete fully radiation-tolerant SoC platform with a standardized interconnect and an IP block library, to serve as the starting point for future ASIC designs. The ASIP based approach targets more the design of data path elements and the use in data processing applications. The presented approach makes use of a commercial ASIP Designer EDA tool to demonstrate an integrated workflow to define, benchmark and optimize an ASIP for a specific use case, starting from a general-purpose processor.

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40

Rathi, C. Arul, G. Rajakumar, T. Ananth Kumar, and T. S. Arun Samuel. "Design and Development of an Efficient Branch Predictor for an In-order RISC-V Processor." Journal of Nano- and Electronic Physics 12, no. 5 (2020): 05021–1. http://dx.doi.org/10.21272/jnep.12(5).05021.

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41

RAO, Jinli, Tianyong AO, Shu XU, Kui DAI, and Xuecheng ZOU. "Design Exploration of SHA-3 ASIP for IoT on a 32-bit RISC-V Processor." IEICE Transactions on Information and Systems E101.D, no. 11 (November 1, 2018): 2698–705. http://dx.doi.org/10.1587/transinf.2017icp0019.

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42

Xin, Guozhu, Jun Han, Tianyu Yin, Yuchao Zhou, Jianwei Yang, Xu Cheng, and Xiaoyang Zeng. "VPQC: A Domain-Specific Vector Processor for Post-Quantum Cryptography Based on RISC-V Architecture." IEEE Transactions on Circuits and Systems I: Regular Papers 67, no. 8 (August 2020): 2672–84. http://dx.doi.org/10.1109/tcsi.2020.2983185.

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43

Cho, Hyungmin. "Correction to “Impact of Microarchitectural Differences of RISC-V Processor Cores on Soft Error Effects”." IEEE Access 7 (2019): 35034. http://dx.doi.org/10.1109/access.2019.2904033.

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44

Zhou, Yuzhi, Xi Jin, Tian Xiang, and Daolu Zha. "Enhancing energy efficiency of RISC-V processor-based embedded graphics systems through frame buffer compression." Microprocessors and Microsystems 77 (September 2020): 103140. http://dx.doi.org/10.1016/j.micpro.2020.103140.

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45

Le, Anh-Tien, Trong-Thuc Hoang, Ba-Anh Dao, Akira Tsukamoto, Kuniyasu Suzaki, and Cong-Kha Pham. "A cross-process Spectre attack via cache on RISC-V processor with trusted execution environment." Computers and Electrical Engineering 105 (January 2023): 108546. http://dx.doi.org/10.1016/j.compeleceng.2022.108546.

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Zhou, Ziqiao, and Michael K. Reiter. "Interpretable noninterference measurement and its application to processor designs." Proceedings of the ACM on Programming Languages 5, OOPSLA (October 20, 2021): 1–30. http://dx.doi.org/10.1145/3485518.

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Noninterference measurement quantifies the secret information that might leak to an adversary from what the adversary can observe and influence about the computation. Static and high-fidelity noninterference measurement has been difficult to scale to complex computations, however. This paper scales a recent framework for noninterference measurement to the open-source RISC-V BOOM core as specified in Verilog, through three key innovations: logically characterizing the core’s execution incrementally, applying specific optimizations between each cycle; permitting information to be declassified, to focus leakage measurement to only secret information that cannot be inferred from the declassified information; and interpreting leakage measurements for the analyst in terms of simple rules that characterize when leakage occurs. Case studies on cache-based side channels generally, and on specific instances including Spectre attacks, show that the resulting toolchain, called DINoMe, effectively scales to this modern processor design.

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Chen, Yuehai, Huarun Chen, Shaozhen Chen, Chao Han, Wujian Ye, Yijun Liu, and Huihui Zhou. "DITES: A Lightweight and Flexible Dual-Core Isolated Trusted Execution SoC Based on RISC-V." Sensors 22, no. 16 (August 10, 2022): 5981. http://dx.doi.org/10.3390/s22165981.

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A Trusted Execution Environment (TEE) is an efficient way to secure information. To obtain higher efficiency, the building of a dual-core system-on-chip (SoC) with TEE security capabilities is the hottest topic. However, TEE SoCs currently commonly use complex processor cores such as Rocket, resulting in high resource usage. More importantly, the cryptographic unit lacks flexibility and ignores secure communication in dual cores. To address the above problems, we propose DITES, a dual-core TEE SoC based on a Reduced Instruction Set Computer-V (RISC-V). At first, we designed a fully isolated multi-level bus architecture based on a lightweight RISC-V processor with an integrated crypto core supporting Secure Hashing Algorithm-1 (SHA1), Advanced Encryption Standard (AES), and Rivest–Shamir–Adleman (RSA), among which RSA can be configured to five key lengths. Then, we designed a secure boot based on Chain-of-Trust (CoT). Furthermore, we propose a hierarchical access policy to improve the security of inter-core communication. Finally, DITES is deployed on a Kintex 7 Field-Programmable-Gate-Array (FPGA) with a power consumption of 0.297 W, synthesized using TSMC 90 nm. From the results, the acceleration ratios of SHA1 and RSA1024 decryption/encryption can reach 75 and 1331/1493, respectively. Compared to exiting TEE SoCs, DITES has lower resource consumption, higher flexibility, and better security.

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Taştan, İbrahim, Mahmut Karaca, and Arda Yurdakul. "Approximate CPU Design for IoT End-Devices with Learning Capabilities." Electronics 9, no. 1 (January 9, 2020): 125. http://dx.doi.org/10.3390/electronics9010125.

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With the rise of Internet of Things (IoT), low-cost resource-constrained devices have to be more capable than traditional embedded systems, which operate on stringent power budgets. In order to add new capabilities such as learning, the power consumption planning has to be revised. Approximate computing is a promising paradigm for reducing power consumption at the expense of inaccuracy introduced to the computations. In this paper, we set forth approximate computing features of a processor that will exist in the next generation low-cost resource-constrained learning IoT devices. Based on these features, we design an approximate IoT processor which benefits from RISC-V ISA. Targeting machine learning applications such as classification and clustering, we have demonstrated that our processor reinforced with approximate operations can save power up to 23% for ASIC implementation while at least 90% top-1 accuracy is achieved on the trained models and test data set.

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Han, Xiaojing, Liang Liu, Zhe Zhang, Yufeng Sun, Jiahui Zhou, and Hao Cai. "Design of a High Performance Vector Processor Based on RISIC-V Architecture." Journal of Physics: Conference Series 2560, no. 1 (August 1, 2023): 012027. http://dx.doi.org/10.1088/1742-6596/2560/1/012027.

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Abstract This paper proposes a high performance Vector processor based on the high performance Embedded Core which is named TS800. The TS800 is a 4-core processor based on RISC-V architecture, implements IMAFDV instruction set, supports L2 Cache, branch prediction, sequential pipeline, and dual-issue structure. The traditional CPU mainly supports Scalar calculations, or only supports Vector calculations. For applications such as image and signal processing, there are a large number of data parallel computing operations. To solve the problem of low performance of parallel data calculations in industrial power applications, it is proposed to add VPU hardware implementation in the TS800. The TS800 can support FFT algorithm, adaptive controllers Reinforcement learning and learning-based underlying algorithm requirements. In this paper, the module and data flow between each processing unit and the control circuit, that is, the hardware realization of VPU module are proposed. Large-area units such as float arithmetic, multiplication and division are multiplexed with the Scalar operator in the CPU, while the control circuit is placed in the VPU-ALU, and the area is small. Units such as arithmetic and logic operation instructions, shift operation instructions, comparison operation instructions, and permutation instruction are implemented through the VPU-ALU, which makes the overall design area smaller and the performance better. At the same time, through the fir, fft, conv, matrix, Signal Converge and variance test, it is proved that while executing the same program, the running time of the cpu only with Scalar is 1.44 to 9.55 times that of the CPU with Vector module, which can support the underlying algorithm of the adaptive controller.

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Mach, Ján, Lukáš Kohútka, and Pavel Čičák. "In-Pipeline Processor Protection against Soft Errors." Journal of Low Power Electronics and Applications 13, no. 2 (May 10, 2023): 33. http://dx.doi.org/10.3390/jlpea13020033.

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The shrinking of technology nodes allows higher performance, but susceptibility to soft errors increases. The protection has been implemented mainly by lockstep or hardened process techniques, which results in a lower frequency, a larger area, and higher power consumption. We propose a protection technique that only slightly affects the maximal frequency. The area and power consumption increase are comparable with dual lockstep architectures. A reaction to faults and the ability to recover from them is similar to triple modular redundancy architectures. The novelty lies in applying redundancy into the processor’s pipeline and its separation into two sections. The protection provides fast detection of faults, simple recovery by a flush of the pipeline, and allows a large prediction unit to be unprotected. A proactive component automatically scrubs a register file to prevent fault accumulation. The whole protection scheme can be fully implemented at the register transfer level. We present the protection scheme implemented inside the RISC-V core with the RV32IMC instruction set. Simulations confirm that the protection can handle the injected faults. Synthesis shows that the protection lowers the maximum frequency by only about 3.9%. The area increased by 108% and power consumption by 119%.

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