Дисертації з теми "RISC V processor"
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Vavro, Tomáš. "Periferie procesoru RISC-V." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2021. http://www.nusl.cz/ntk/nusl-445553.
Повний текст джерелаSkála, Milan. "Prostředí pro spouštění testů kompatibility RISC-V." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2018. http://www.nusl.cz/ntk/nusl-386021.
Повний текст джерелаChovančíková, Lucie. "Implementace mikroprocesoru RISC-V s rozšířením pro bitové manipulace." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2020. http://www.nusl.cz/ntk/nusl-413229.
Повний текст джерелаSláma, Pavel. "Paralelismus na úrovni instrukcí v moderních procesorech." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2020. http://www.nusl.cz/ntk/nusl-413231.
Повний текст джерелаFang, Gloria(Gloria Yu Liang). "Instruction-level power consumption simulator for modeling simple timing and power side channels in a 32-bit RISC-V micro-processor." Thesis, Massachusetts Institute of Technology, 2021. https://hdl.handle.net/1721.1/130686.
Повний текст джерелаCataloged from the official PDF of thesis.
Includes bibliographical references (pages 139-140).
We create a Python based RISC-V simulator that is capable of simulating any assembly code written in RISC-V, and even perform simple power analysis of RISC-V designs. The power consumption of non-privileged RISC-V RV32IM instructions are measured experimentally, forming the basis for our simulator. These instructions include memory loads and stores, PC jumps and branches, as well as arithmetic instructions with register values. The object-oriented simulator also supports stepping and debugging. In the context of designing software for hardware use, the simulator helps assess vulnerability to side channel attacks by accepting input power consumption values. The power consumption graph of any disassembled RISC-V code can be obtained if the power consumption of each instruction is given as an input; then, from the output power consumption waveforms, we can assess how vulnerable a system is to side channel attacks. Because the power values can be customized based on what's experimentally measured, this means that our simulator can be applied to any disassembled code and to any system as long as the input power consumption of each instruction is supplied. Finally, we demonstrate an example application of the simulator on a pseudorandom function for simple side channel power analysis.
by Gloria (Yu Liang) Fang.
M. Eng.
M.Eng. Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science
Vávra, Jan. "Grafický simulátor superskalárních procesorů." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2021. http://www.nusl.cz/ntk/nusl-445476.
Повний текст джерелаBarták, Jiří. "Model procesoru RISC-V." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2016. http://www.nusl.cz/ntk/nusl-255393.
Повний текст джерелаBardonek, Petr. "Specifikace scénářů portovatelných stimulů pro moduly procesoru RISC-V." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2018. http://www.nusl.cz/ntk/nusl-385914.
Повний текст джерелаOttavi, Gianmarco. "Sviluppo e Ottimizzazione di un Processore Configurabile con Unità di Calcolo a Precisione Variabile." Master's thesis, Alma Mater Studiorum - Università di Bologna, 2019.
Знайти повний текст джерелаMusasa, Mutombo Mike. "Evaluation of embedded processors for next generation asic : Evaluation of open source Risc-V processors and tools ability to perform packet processing operations compared to Arm Cortex M7 processors." Thesis, KTH, Skolan för elektroteknik och datavetenskap (EECS), 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-299656.
Повний текст джерелаNätverksprocessorer är en viktig byggsten av informationsteknik idag. I takt med att 5G nätverk byggs ut runt om i världen, många fler enheter kommer att kunna ta del av deras kraftfulla prestanda och programerings flexibilitet. Informationsteknik företag som Ericsson, spenderarmycket ekonomiska resurser på licenser för att kunna använda proprietära instruktionsuppsättnings arkitektur teknik baserade processorer från ARM holdings. Det är väldigt kostam att fortsätta köpa licenser då dessa arkitekturer är en byggsten till designen av många processorer och andra komponenter. Idag finns det en lovande ny processor instruktionsuppsättnings arkitektur teknik som inte är licensierad så kallad Risc-V. Tack vare Risc-V har många propietära och öppen källkod processor utvecklats idag. Det finns dock väldigt lite information kring hur bra de presterar i nätverksapplikationer är känt idag. Kan en öppen-källkod Risc-V processor utföra nätverks databehandling funktioner lika bra som en proprietär Arm Cortex M7 processor? Huvudsyftet med detta arbete är att bygga en test model som undersöker hur väl en öppen-källkod Risc-V baserad processor utför databehandlings operationer av nätverk datapacket jämfört med en Arm Cortex M7 processor. Detta har utförts genom att ta fram en C programmeringskod som simulerar en mottagning och behandling av 72 bytes datapaket. De följande funktionerna testades, inramning, parsning, mönster matchning och klassificering. Koden kompilerades och testades i både en Arm Cortex M7 processor och 3 olika emulerade öppen källkod Risc-V processorer, Arianne, SweRV core och Rocket-chip. Efter att ha testat några öppen källkod Risc-V processorer och använt test koden i en ArmCortex M7 processor, kan det hävdas att öppen-källkod Risc-V processor verktygen inte är tillräckligt pålitliga än. Denna rapport tyder på att öppen-källkod Risc-V emulatorer och verktygen behöver utvecklas mer för att användas i nätverks applikationer. Det finns ett behov av ytterligare undersökning inom detta ämne i framtiden. Exempelvis, en djupare undersökning av SweRV core processor, eller en öppen-källkod Risc-V byggd hårdvara krävs.
Javor, Adrián. "Formalní verifikace RISC-V procesoru s využitím Questa PropCheck." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2020. http://www.nusl.cz/ntk/nusl-413219.
Повний текст джерелаMoussa, Imed. "Applications des circuits numériques en arseniure de gallium dans les systèmes à haut débit de communication et dans les calculateurs performants." Grenoble INPG, 1996. http://www.theses.fr/1996INPG0077.
Повний текст джерелаMELO, Cecil Accetti Resende de Ataíde. "Projeto de uma arquitetura baseada num processador RISC-V para desenvolvimento de aplicações em software-defined radio." Universidade Federal de Pernambuco, 2016. https://repositorio.ufpe.br/handle/123456789/26036.
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CNPq
Os sistemas de software-defined radio práticos normalmente se dividem em duas classes: arquiteturas reconfiguráveis em FPGA que implementam os algoritmos de processamento de digital de sinais, com granularidade alta e, as arquiteturas baseadas em processador. Um dos problemas no projeto de arquiteturas de processamento digital de sinais baseadas em processador é o do suporte a compiladores e linguagens de alto nível. Arquiteturas muito especializadas, com conjuntos de instruções extensos e muitos modos de endereçamento, dificultam a implementação de compiladores para linguagens de alto nível. Neste trabalho buscou-se explorar a viabilidade de um conjunto de instruções emergente, RISC-V, e uma extensão do seu conjunto de instruções para a aplicação em processamento digital de sinais de banda base, sobretudo nas funcionalidades de modem, em aplicações de software-defined radio. A análise das operações de um modem, para as modulações digitais mais utilizadas, revela que as operações feitas para modulação/ demodulação envolvem números complexos. No entanto, aritmética de complexos não é normalmente suportada pelo hardware em arquiteturas tradicionais. Além da arquitetura proposta para o processador, com suporte a novas instruções especializadas, os periféricos necessários para o front-end de rádio frequência e o software de suporte foram implementados, resultando num SoC para software defined radio.
Practical software-defined radio systems are usually classified in two main architecture classes: Reconfigurable architectures on FPGAs, that implement coarse grained digital signal processing algorithms, or processor-based architectures. One of the issues in the design of processor-based digital signal processing architectures is compiler and high-level languages support. Highly specialized architectures, with extensive instruction sets (ISA) and addressing modes turn high-level languages compiler design a complex task. In this work we explore the viability to extend the emerging RISC-V instruction set for baseband processing applications for software-defined radio, especially for modem applications. The analysis of modem functions, for the most used digital modulation schemes, reveals that the modulation/demodulation tasks involve complex number operations. Complex number arithmetic, however, is not supported on traditional architectures. The proposed platform includes a 3-stage pipelined processor with new specialized instructions, as well as the peripherals needed to the radio-frequency front-end and supporting software, resulting on a system-on-a-chip for software-defined radio applications. software-defined radio.
Birkus, Kristián. "Systém pro podporu managementu rizik v IT projektech." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2009. http://www.nusl.cz/ntk/nusl-236705.
Повний текст джерелаKošinová, Kateřina. "Rizikové chování ETL procesů v prostředí datového skladu." Master's thesis, Vysoké učení technické v Brně. Ústav soudního inženýrství, 2015. http://www.nusl.cz/ntk/nusl-233204.
Повний текст джерелаKneblová, Jana. "Metody analýzy korporátních ukazatelů a jejich využití v rámci preventivního Risk managementu pro Škoda Auto a.s." Master's thesis, Vysoké učení technické v Brně. Fakulta podnikatelská, 2015. http://www.nusl.cz/ntk/nusl-224954.
Повний текст джерелаPokorný, David. "Zavedení BYOD pro notebooky v Telefónica Czech Republic." Master's thesis, Vysoká škola ekonomická v Praze, 2013. http://www.nusl.cz/ntk/nusl-198248.
Повний текст джерелаCheng-TingKao and 高振庭. "Automate and Accelerate RISC-V Processor Verification by Compositional Formal Method." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/zg7993.
Повний текст джерелаChen, Yu-Jui, and 陳俞睿. "A High efficiency 16-Channel ICA RISC-V Processor for Biomedical Signal Processing." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/19879372082744467690.
Повний текст джерела國立交通大學
電機工程學系
105
To improve the performance of epileptic seizure detection, independent component analysis (ICA) is applied to multi-channel signals to separate artifacts and signals of interest. FastICA is an efficient algorithm to compute ICA. However, the number of channels will limit by chip area. ICA has much matrix operations. The complexity of matrix is O (n2~3). It is hard to extend channel out of four to eight channels. In the case of ECoG signal, the electrode patches are fixed after installation. Some of the FastICA algorithm can be reduced because of fixed electrode patches. We only need one-time singular value decomposition for eigenvalue at first time. We can implement singular value decomposition by firmware in stand of hardware to reduce area. We can have more area to get more channels. The microcontroller can implement other protocol and signal process making this chip more applicable. The performance of the chip was verified by human dataset.
Baral, Pushpa. "Static Analysis and Dynamic Monitoring of Program Flow on REDEFINE Manycore Processor." Thesis, 2021. https://etd.iisc.ac.in/handle/2005/5577.
Повний текст джерелаRodrigues, Cristiano António Azevedo. "Heterogeneous fault tolerance architecture based on Arm and RISC-V processors." Master's thesis, 2019. http://hdl.handle.net/1822/64956.
Повний текст джерелаSafety-critical systems deployed in harsh environments rely on fault tolerance and redundancy techniques to keep them operating even in the presence of faults. Although there are effective techniques to mitigate one side faults, they are not enough to protect the system against simultaneously multi side faults. These kinds of faults trigger the same error in faulty redundant components, which makes resulting errors invisible and undetectable for fault tolerant mechanisms. To overcome this problem, design diversity is applied in fault tolerant system to mitigate the Common-Mode Failure (CMF) and build a more robust and reliable system. Despite several fault tolerance architectures based on FPGA are available in the literature, to the best of our knowledge, none of them aims both hardening of heterogeneous processors and applying design diversity at processor level. To address this lack of solutions in the current state of the art, this dissertation proposes a novel heterogeneous fault tolerance architecture, Lock-V, which enables design diversity at processors architecture level. It deals with CMF, as well as both error detection and recovery fault tolerance techniques to mitigate errors triggered by external environment interactions, e.g., radiation. To eliminate the CMF, Lock-V explores an implementation based on different processing units: a hard-core Arm Cortex-A9 and a soft-core RISC-V-based processors, to leverage design diversity through ISA heterogeneity. To implement fault tolerance, Lock-V proposes a hybrid DCLS solution where the error detection is done by hardware, resorting to a FPGA accelerator, while error recovery is performed by software using rollback technique. After the deployment of Lock-V on a Zynq-7000 SoC, over 45000 faults were injected. The results taken from such injection shows that when an application runs on the Lock-V architecture, besides its protection against the CMF due to processors design diversity, it is also protected against 97% of the triggered errors. Nevertheless implement Lock-V came up with some tradeoffs. It used 79% of the LUT and 34% of the FF available on the Zedboard FPGA platform. Regarding the software part, implementing Lock-V leads to an 8% increase in memory footprint and also an increase in the execution overhead around 12%, mainly in the worst case scenario as tested in the absence of errors. Knowing that all the redundancy has its cost, Lock-V proved to be able to grant a system with design diversity and fault tolerance capabilities.
Quando sistemas críticos operam em ambientes hostis, estes necessitam de serviços de redundância e de tolerância a falhas para continuarem em funcionamento mesmo na presença de faltas. Embora a técnica de tolerância a falhas seja eficaz para mitigar faltas que ocorrem num único componente, ela perde eficácia, quando múltiplas faltas acontecem simultaneamente em vários componentes. Estes tipos de faltas, despoletam o mesmo erro em todos os componentes afetados, tornando-as indetectáveis. Para solucionar este problema, usualmente, recorre-se a diversidade de desenho para mitigar as Falhas de Modo Comum (FMC), construindo assim um sistema mais robusto e confiável. Várias arquiteturas de tolerância a falhas, baseadas em Field-Programmable Gate Array (FPGA), têm sido descritas na literatura, no entanto, pelas pesquisas efetuadas, nenhuma delas tem como objetivo proteger processadores heterogéneos e aplicar diversidade de desenho ao nível do processador. Para resolver a supracitada falta de soluções, esta dissertação propõe uma nova arquitetura heterogénea de tolerância a falhas, Lock-V. O Lock-V promove diversidade de desenho, ao nível da arquitetura do processador, assim como técnicas de tolerância a falhas para, respetivamente, mitigar FMC e detetar e recuperar erros despoletados por causas externas, por exemplo, radiação. Para eliminar as FMC, o Lock-V possuí duas unidades de processamento diferentes: um hard-core Arm Cortex-A9 e um soft-core baseado em RISC-V. Desta forma é aplicada diversidade de desenho, usando heterogeneidade no Instruction Set Architecture (ISA). Por outro lado, para implementar tolerância a falhas, o Lock-V propõe uma solução híbrida de Dual-Core Lockstep (DCLS), onde a deteção de erros é feita em hardware, recorrendo a um acelerador na FPGA, e a recuperação dos erros é suportado por software, usando técnicas de rollback. Após o Lock-V ser implementado na Zynq-7000 System-on-Chip (SoC), mais de 45000 faltas foram injetadas. Os resultados dessa injeção mostram que quando uma aplicação executa na arquitetura Lock-V, para além de estar protegida contra FMC, devido à diversidade do desenho ao nível dos processadores, também está protegida contra 97% dos erros ocorridos. No entanto, implementar o Lock-V acarreta alguns tradeoffs. 79% das Look-Up Tables (LUT) e 34% dos Flip-Flops (FF) disponíveis na plataforma (Zedboard), são usados. Ao nível do software, o Lock-V aumenta em 8% o consumo de memoria e, para o pior cenário testando sem a ocorrência de erros, aumenta em 12% o overhead de execução. Tendo em conta que toda a redundância tem o seu custo, o Lock-V provou ser capaz de dotar um sistema com diversidade de desenho e capacidades de tolerância a falhas.
CHEIKH, ABDALLAH. "Energy-efficient digital electronic systems design for edge-computing applications, through innovative RISC-V compliant processors." Doctoral thesis, 2020. http://hdl.handle.net/11573/1363198.
Повний текст джерела