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Статті в журналах з теми "RISC V processor"
Pitcher, Graham. "RISC-V Powers IoT Apps Processor." New Electronics 51, no. 4 (February 27, 2018): 7. http://dx.doi.org/10.12968/s0047-9624(23)60141-5.
Повний текст джерелаGamino del Río, Iván, Agustín Martínez Hellín, Óscar R. Polo, Miguel Jiménez Arribas, Pablo Parra, Antonio da Silva, Jonatan Sánchez, and Sebastián Sánchez. "A RISC-V Processor Design for Transparent Tracing." Electronics 9, no. 11 (November 7, 2020): 1873. http://dx.doi.org/10.3390/electronics9111873.
Повний текст джерелаHongsheng, Zhang, Zekun Jiang, and Yong Li. "Design of a dual-issue RISC-V processor." Journal of Physics: Conference Series 1693 (December 2020): 012192. http://dx.doi.org/10.1088/1742-6596/1693/1/012192.
Повний текст джерелаAn, Hyogeun, Sudong Kang, Guard Kanda, and Kwangki Ryoo. "RISC-V Hardware Synthesizable Processor Design Test and Verification Using User-Friendly Desktop Application." Webology 19, no. 1 (January 20, 2022): 4597–620. http://dx.doi.org/10.14704/web/v19i1/web19305.
Повний текст джерелаNúñez-Prieto, Ricardo, David Castells-Rufas, and Lluís Terés-Terés. "RisCO2: Implementation and Performance Evaluation of RISC-V Processors for Low-Power CO2 Concentration Sensing." Micromachines 14, no. 7 (July 4, 2023): 1371. http://dx.doi.org/10.3390/mi14071371.
Повний текст джерелаMichel Deves de Souza, Eduardo, Nathalia Nathalia Adriana de Oliveira, Douglas Almeida dos Santos Almeida dos Santos, and Douglas Rossi de Melo. "RVSH - Um processador RISC-V para fins didáticos." Anais do Computer on the Beach 14 (May 3, 2023): 450–52. http://dx.doi.org/10.14210/cotb.v14.p450-452.
Повний текст джерелаZhou, Weixin, Dehua Wu, Wan’ang Xiao, Shan Gao, and Wanlin Gao. "A Novel Sleep Scheduling Strategy on RISC-V Processor." Journal of Physics: Conference Series 1631 (September 2020): 012028. http://dx.doi.org/10.1088/1742-6596/1631/1/012028.
Повний текст джерелаXue, Wang, Liu, Lv, Wang, and Zeng. "An RISC-V Processor with Area-Efficient Memristor-Based In-Memory Computing for Hash Algorithm in Blockchain Applications." Micromachines 10, no. 8 (August 16, 2019): 541. http://dx.doi.org/10.3390/mi10080541.
Повний текст джерелаSantos, Douglas A., André M. P. Mattos, Douglas R. Melo, and Luigi Dilillo. "Enhancing Fault Awareness and Reliability of a Fault-Tolerant RISC-V System-on-Chip." Electronics 12, no. 12 (June 6, 2023): 2557. http://dx.doi.org/10.3390/electronics12122557.
Повний текст джерелаGomes, Tiago, Pedro Sousa, Miguel Silva, Mongkol Ekpanyapong, and Sandro Pinto. "FAC-V: An FPGA-Based AES Coprocessor for RISC-V." Journal of Low Power Electronics and Applications 12, no. 4 (September 27, 2022): 50. http://dx.doi.org/10.3390/jlpea12040050.
Повний текст джерелаДисертації з теми "RISC V processor"
Vavro, Tomáš. "Periferie procesoru RISC-V." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2021. http://www.nusl.cz/ntk/nusl-445553.
Повний текст джерелаSkála, Milan. "Prostředí pro spouštění testů kompatibility RISC-V." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2018. http://www.nusl.cz/ntk/nusl-386021.
Повний текст джерелаChovančíková, Lucie. "Implementace mikroprocesoru RISC-V s rozšířením pro bitové manipulace." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2020. http://www.nusl.cz/ntk/nusl-413229.
Повний текст джерелаSláma, Pavel. "Paralelismus na úrovni instrukcí v moderních procesorech." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2020. http://www.nusl.cz/ntk/nusl-413231.
Повний текст джерелаFang, Gloria(Gloria Yu Liang). "Instruction-level power consumption simulator for modeling simple timing and power side channels in a 32-bit RISC-V micro-processor." Thesis, Massachusetts Institute of Technology, 2021. https://hdl.handle.net/1721.1/130686.
Повний текст джерелаCataloged from the official PDF of thesis.
Includes bibliographical references (pages 139-140).
We create a Python based RISC-V simulator that is capable of simulating any assembly code written in RISC-V, and even perform simple power analysis of RISC-V designs. The power consumption of non-privileged RISC-V RV32IM instructions are measured experimentally, forming the basis for our simulator. These instructions include memory loads and stores, PC jumps and branches, as well as arithmetic instructions with register values. The object-oriented simulator also supports stepping and debugging. In the context of designing software for hardware use, the simulator helps assess vulnerability to side channel attacks by accepting input power consumption values. The power consumption graph of any disassembled RISC-V code can be obtained if the power consumption of each instruction is given as an input; then, from the output power consumption waveforms, we can assess how vulnerable a system is to side channel attacks. Because the power values can be customized based on what's experimentally measured, this means that our simulator can be applied to any disassembled code and to any system as long as the input power consumption of each instruction is supplied. Finally, we demonstrate an example application of the simulator on a pseudorandom function for simple side channel power analysis.
by Gloria (Yu Liang) Fang.
M. Eng.
M.Eng. Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science
Vávra, Jan. "Grafický simulátor superskalárních procesorů." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2021. http://www.nusl.cz/ntk/nusl-445476.
Повний текст джерелаBarták, Jiří. "Model procesoru RISC-V." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2016. http://www.nusl.cz/ntk/nusl-255393.
Повний текст джерелаBardonek, Petr. "Specifikace scénářů portovatelných stimulů pro moduly procesoru RISC-V." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2018. http://www.nusl.cz/ntk/nusl-385914.
Повний текст джерелаOttavi, Gianmarco. "Sviluppo e Ottimizzazione di un Processore Configurabile con Unità di Calcolo a Precisione Variabile." Master's thesis, Alma Mater Studiorum - Università di Bologna, 2019.
Знайти повний текст джерелаMusasa, Mutombo Mike. "Evaluation of embedded processors for next generation asic : Evaluation of open source Risc-V processors and tools ability to perform packet processing operations compared to Arm Cortex M7 processors." Thesis, KTH, Skolan för elektroteknik och datavetenskap (EECS), 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-299656.
Повний текст джерелаNätverksprocessorer är en viktig byggsten av informationsteknik idag. I takt med att 5G nätverk byggs ut runt om i världen, många fler enheter kommer att kunna ta del av deras kraftfulla prestanda och programerings flexibilitet. Informationsteknik företag som Ericsson, spenderarmycket ekonomiska resurser på licenser för att kunna använda proprietära instruktionsuppsättnings arkitektur teknik baserade processorer från ARM holdings. Det är väldigt kostam att fortsätta köpa licenser då dessa arkitekturer är en byggsten till designen av många processorer och andra komponenter. Idag finns det en lovande ny processor instruktionsuppsättnings arkitektur teknik som inte är licensierad så kallad Risc-V. Tack vare Risc-V har många propietära och öppen källkod processor utvecklats idag. Det finns dock väldigt lite information kring hur bra de presterar i nätverksapplikationer är känt idag. Kan en öppen-källkod Risc-V processor utföra nätverks databehandling funktioner lika bra som en proprietär Arm Cortex M7 processor? Huvudsyftet med detta arbete är att bygga en test model som undersöker hur väl en öppen-källkod Risc-V baserad processor utför databehandlings operationer av nätverk datapacket jämfört med en Arm Cortex M7 processor. Detta har utförts genom att ta fram en C programmeringskod som simulerar en mottagning och behandling av 72 bytes datapaket. De följande funktionerna testades, inramning, parsning, mönster matchning och klassificering. Koden kompilerades och testades i både en Arm Cortex M7 processor och 3 olika emulerade öppen källkod Risc-V processorer, Arianne, SweRV core och Rocket-chip. Efter att ha testat några öppen källkod Risc-V processorer och använt test koden i en ArmCortex M7 processor, kan det hävdas att öppen-källkod Risc-V processor verktygen inte är tillräckligt pålitliga än. Denna rapport tyder på att öppen-källkod Risc-V emulatorer och verktygen behöver utvecklas mer för att användas i nätverks applikationer. Det finns ett behov av ytterligare undersökning inom detta ämne i framtiden. Exempelvis, en djupare undersökning av SweRV core processor, eller en öppen-källkod Risc-V byggd hårdvara krävs.
Книги з теми "RISC V processor"
Serafimova, Vera. History of Russian literature of XX-XXI centuries. ru: INFRA-M Academic Publishing LLC., 2020. http://dx.doi.org/10.12737/1138897.
Повний текст джерелаLaperdin, V. K. Geodinamika opasnykh prot︠s︡essov v zonakh prirodno-tekhnogennykh kompleksov Vostochnoĭ Sibiri: The geodynamics of hazardous processes in the zones of natural-technical complexes of East Siberia. Irkutsk: Institut zemnoĭ kory SO RAN, 2010.
Знайти повний текст джерелаSerafimova, Vera, Ivan Pankeev, and L. G. Tyurina. History of Russian literature of the XX-XXI centuries. ru: INFRA-M Academic Publishing LLC., 2022. http://dx.doi.org/10.12737/1866868.
Повний текст джерелаGoossens, Bernard. Guide to Computer Processor Architecture: A RISC-V Approach, with High-Level Synthesis. Springer International Publishing AG, 2022.
Знайти повний текст джерелаBalestero, Gabriela Soares, and Ana Silvia Marcatto Begalli. Estudos de Direito Latino Americano. 11th ed. Editora Amplla, 2022. http://dx.doi.org/10.51859/amplla.edl1037-0.
Повний текст джерелаЧастини книг з теми "RISC V processor"
Goossens, Bernard. "Testing Your RISC-V Processor." In Undergraduate Topics in Computer Science, 201–31. Cham: Springer International Publishing, 2023. http://dx.doi.org/10.1007/978-3-031-18023-1_7.
Повний текст джерелаGoossens, Bernard. "A Multicore RISC-V Processor." In Undergraduate Topics in Computer Science, 377–99. Cham: Springer International Publishing, 2023. http://dx.doi.org/10.1007/978-3-031-18023-1_12.
Повний текст джерелаGoossens, Bernard. "Building a RISC-V Processor." In Undergraduate Topics in Computer Science, 183–200. Cham: Springer International Publishing, 2023. http://dx.doi.org/10.1007/978-3-031-18023-1_6.
Повний текст джерелаGoossens, Bernard. "Building a Pipelined RISC-V Processor." In Undergraduate Topics in Computer Science, 233–65. Cham: Springer International Publishing, 2023. http://dx.doi.org/10.1007/978-3-031-18023-1_8.
Повний текст джерелаGoossens, Bernard. "A Multicore RISC-V Processor with Multihart Cores." In Undergraduate Topics in Computer Science, 401–23. Cham: Springer International Publishing, 2023. http://dx.doi.org/10.1007/978-3-031-18023-1_13.
Повний текст джерелаGoossens, Bernard. "Building a RISC-V Processor with a Multicycle Pipeline." In Undergraduate Topics in Computer Science, 267–99. Cham: Springer International Publishing, 2023. http://dx.doi.org/10.1007/978-3-031-18023-1_9.
Повний текст джерелаSharat, Kavya, Sumeet Bandishte, Kuruvilla Varghese, and Amrutur Bharadwaj. "A Custom Designed RISC-V ISA Compatible Processor for SoC." In Communications in Computer and Information Science, 570–77. Singapore: Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-7470-7_55.
Повний текст джерелаGoossens, Bernard. "Building a RISC-V Processor with a Multiple Hart Pipeline." In Undergraduate Topics in Computer Science, 301–51. Cham: Springer International Publishing, 2023. http://dx.doi.org/10.1007/978-3-031-18023-1_10.
Повний текст джерелаChen, Mengxue, Xiaochang Ma, and Bangjian Xu. "A Design of ALU Comparator for High Performance RISC-V Processor." In Lecture Notes in Electrical Engineering, 351–57. Singapore: Springer Nature Singapore, 2023. http://dx.doi.org/10.1007/978-981-99-0416-7_35.
Повний текст джерелаLiu, Yu, Kejiang Ye, and Cheng-Zhong Xu. "Performance Evaluation of Various RISC Processor Systems: A Case Study on ARM, MIPS and RISC-V." In Cloud Computing – CLOUD 2021, 61–74. Cham: Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-030-96326-2_5.
Повний текст джерелаТези доповідей конференцій з теми "RISC V processor"
Patsidis, Kariofyllis, Chrysostomos Nicopoulos, Georgios Ch Sirakoulis, and Giorgos Dimitrakopoulos. "RISC-V2: A Scalable RISC-V Vector Processor." In 2020 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2020. http://dx.doi.org/10.1109/iscas45731.2020.9181071.
Повний текст джерелаBirari, Akshay, Piyush Birla, Kuruvilla Varghese, and Amrutur Bharadwaj. "A RISC-V ISA Compatible Processor IP." In 2020 24th International Symposium on VLSI Design and Test (VDAT). IEEE, 2020. http://dx.doi.org/10.1109/vdat50263.2020.9190558.
Повний текст джерелаPekkarinen, Esko, and Timo D. Hamalainen. "Modeling RISC-V Processor in IP-XACT." In 2018 21st Euromicro Conference on Digital System Design (DSD). IEEE, 2018. http://dx.doi.org/10.1109/dsd.2018.00036.
Повний текст джерелаAskariHemmat, MohammadHossein, Olexa Bilaniuk, Sean Wagner, Yvon Savaria, and Jean-Pierre David. "RISC-V Barrel Processor for Accelerator Control." In 2020 IEEE 28th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM). IEEE, 2020. http://dx.doi.org/10.1109/fccm48280.2020.00063.
Повний текст джерелаIslam, Md Ashraful, and Kenji Kise. "Efficient Resource Shared RISC-V Multicore Processor." In 2021 IEEE 14th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC). IEEE, 2021. http://dx.doi.org/10.1109/mcsoc51149.2021.00061.
Повний текст джерелаZang, Zhenya, Yao Liu, and Ray C. C. Cheung. "Reconfigurable RISC-V Secure Processor And SoC Integration." In 2019 IEEE International Conference on Industrial Technology (ICIT). IEEE, 2019. http://dx.doi.org/10.1109/icit.2019.8755206.
Повний текст джерелаLee, Wooyoung, Jina Park, Changjun Byun, Eunjin Choi, Jae-Hyoung Lee, Woojoo Lee, Kyung Jin Byun, and Kyuseung Han. "K-means Clustering-specific Lightweight RISC-V processor." In 2021 18th International SoC Design Conference (ISOCC). IEEE, 2021. http://dx.doi.org/10.1109/isocc53507.2021.9613863.
Повний текст джерелаBudi, Suseela, Pradeep Gupta, Kuruvilla Varghese, and Amrutur Bharadwaj. "A RISC-V ISA compatible processor IP for SoC." In 2018 International Symposium on Devices, Circuits and Systems (ISDCS). IEEE, 2018. http://dx.doi.org/10.1109/isdcs.2018.8379629.
Повний текст джерелаJohns, Matthew, and Tom J. Kazmierski. "A Minimal RISC-V Vector Processor for Embedded Systems." In 2020 Forum for Specification and Design Languages (FDL). IEEE, 2020. http://dx.doi.org/10.1109/fdl50818.2020.9232940.
Повний текст джерелаAskariHemmat, MohammadHossein, Olexa Bilaniuk, Sean Wagner, Yvon Savaria, and Jean-Pierre David. "RISC-V Barrel Processor for Deep Neural Network Acceleration." In 2021 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2021. http://dx.doi.org/10.1109/iscas51556.2021.9401617.
Повний текст джерелаЗвіти організацій з теми "RISC V processor"
Kira, Beatriz, Rutendo Tavengerwei, and Valary Mumbo. Points à examiner à l'approche des négociations de Phase II de la ZLECAf: enjeux de la politique commerciale numérique dans quatre pays d'Afrique subsaharienne. Digital Pathways at Oxford, March 2022. http://dx.doi.org/10.35489/bsg-dp-wp_2022/01.
Повний текст джерела