Статті в журналах з теми "REVERSIBLE MULTIPLIER"
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HAGHPARAST, MAJID, MAJID MOHAMMADI, KEIVAN NAVI, and MOHAMMAD ESHGHI. "OPTIMIZED REVERSIBLE MULTIPLIER CIRCUIT." Journal of Circuits, Systems and Computers 18, no. 02 (April 2009): 311–23. http://dx.doi.org/10.1142/s0218126609005083.
Повний текст джерелаRashno, Meysam, Majid Haghparast, and Mohammad Mosleh. "A new design of a low-power reversible Vedic multiplier." International Journal of Quantum Information 18, no. 03 (April 2020): 2050002. http://dx.doi.org/10.1142/s0219749920500021.
Повний текст джерелаRayudu, Kurada Verra Bhoga Vasantha, Dhananjay Ramachandra Jahagirdar, and Patri Srihari Rao. "Design and testing of systolic array multiplier using fault injecting schemes." Computer Science and Information Technologies 3, no. 1 (March 1, 2022): 1–9. http://dx.doi.org/10.11591/csit.v3i1.p1-9.
Повний текст джерелаDurgam, Veena, and Dr K. Ragini. "Design of 32x32 Reversible Unsigned Multiplier Using Dadda Tree Algorithm." ECS Transactions 107, no. 1 (April 24, 2022): 16251–58. http://dx.doi.org/10.1149/10701.16251ecst.
Повний текст джерелаRaviteja, Ragoju, Mittapelli Kalyan Krishna, Gare Sandhya, and N. Srinivasa Reddy. "Approximative Signed Wallace Tree Multiplier Using Reversible Logic." International Journal for Research in Applied Science and Engineering Technology 11, no. 4 (April 30, 2023): 2474–78. http://dx.doi.org/10.22214/ijraset.2023.50668.
Повний текст джерелаZomorodi Moghadam, Mariam, and Keivan Navi. "Ultra-area-efficient reversible multiplier." Microelectronics Journal 43, no. 6 (June 2012): 377–85. http://dx.doi.org/10.1016/j.mejo.2012.02.004.
Повний текст джерелаEshack, Ansiya, and S. Krishnakumar. "Reversible logic in pipelined low power vedic multiplier." Indonesian Journal of Electrical Engineering and Computer Science 16, no. 3 (December 1, 2019): 1265. http://dx.doi.org/10.11591/ijeecs.v16.i3.pp1265-1272.
Повний текст джерелаSaravanan. "NOVEL REVERSIBLE VARIABLE PRECISION MULTIPLIER USING REVERSIBLE LOGIC GATES." Journal of Computer Science 10, no. 7 (July 1, 2014): 1135–38. http://dx.doi.org/10.3844/jcssp.2014.1135.1138.
Повний текст джерелаAriafar, Zahra, and Mohammad Mosleh. "Effective Designs of Reversible Vedic Multiplier." International Journal of Theoretical Physics 58, no. 8 (May 24, 2019): 2556–74. http://dx.doi.org/10.1007/s10773-019-04145-0.
Повний текст джерелаSaiAbhinav, B., M. Jaipal Reddy, Y. Siva Kumar, and S. Sivanantham S.Sivanantham. "ASIC Design of Reversible Adder and Multiplier." International Journal of Computer Applications 109, no. 10 (January 16, 2015): 6–10. http://dx.doi.org/10.5120/19222-0638.
Повний текст джерелаRashno, Meysam, Majid Haghparast, and Mohammad Mosleh. "Designing of Parity Preserving Reversible Vedic Multiplier." International Journal of Theoretical Physics 60, no. 8 (July 13, 2021): 3024–40. http://dx.doi.org/10.1007/s10773-021-04903-z.
Повний текст джерелаH.G, Rangaraju, Aakash Babu Suresh, and Muralidhara K.N. "Design and Optimization of Reversible Multiplier Circuit." International Journal of Computer Applications 52, no. 10 (August 30, 2012): 44–50. http://dx.doi.org/10.5120/8242-1523.
Повний текст джерелаPourAliAkbar, Ehsan, Keivan Navi, Majid Haghparast, and Midia Reshadi. "Novel Optimum Parity-Preserving Reversible Multiplier Circuits." Circuits, Systems, and Signal Processing 39, no. 10 (April 8, 2020): 5148–68. http://dx.doi.org/10.1007/s00034-020-01406-w.
Повний текст джерелаBaraniya, Shweta, and Sujeet Mishra. "Review Paper on Reversible Multiplier Circuit using Different Programmable Reversible Gate." International Journal of Electrical and Electronics Engineering 2, no. 10 (October 25, 2015): 16–20. http://dx.doi.org/10.14445/23488379/ijeee-v2i10p104.
Повний текст джерелаZhou, Rigui, Yang Shi, Hui’an Wang, and Jian Cao. "Transistor realization of reversible “ZS” series gates and reversible array multiplier." Microelectronics Journal 42, no. 2 (February 2011): 305–15. http://dx.doi.org/10.1016/j.mejo.2010.11.008.
Повний текст джерелаRahman, Md M., Md M. Hossain, Lafifa Jamal, and S. Nowrin. "Designing of a reversible fault tolerant booth multiplier." Bangladesh Journal of Scientific and Industrial Research 53, no. 3 (September 18, 2018): 199–204. http://dx.doi.org/10.3329/bjsir.v53i3.38266.
Повний текст джерелаGholpe, Minal, and Prasad Sangare. "ASIC Design of Reversible Multiplier Using Adiabatic Technique." International Journal of Computer Applications Technology and Research 6, no. 2 (February 20, 2017): 117–20. http://dx.doi.org/10.7753/ijcatr0602.1009.
Повний текст джерелаPourAliAkbar, Ehsan, and Mohammad Mosleh. "An efficient design for reversible Wallace unsigned multiplier." Theoretical Computer Science 773 (June 2019): 43–52. http://dx.doi.org/10.1016/j.tcs.2018.06.007.
Повний текст джерелаIslam, M. S., M. M. Rahman, Z. Begum, and M. Z. Hafiz. "Low Cost Quantum Realization of Reversible Multiplier Circuit." Information Technology Journal 8, no. 2 (February 1, 2009): 208–13. http://dx.doi.org/10.3923/itj.2009.208.213.
Повний текст джерелаH R, Bhagyalakshmi. "Optimized Multiplier Using Reversible Multicontrol Input Toffoli Gates." International Journal of VLSI Design & Communication Systems 3, no. 6 (December 31, 2012): 27–40. http://dx.doi.org/10.5121/vlsic.2012.3603.
Повний текст джерелаAmrutha, P., and P. A. Sunny Dayal. "A Novel Design of Low Power Reversible Multiplier." IOSR Journal of Electronics and Communication Engineering 9, no. 3 (2014): 08–14. http://dx.doi.org/10.9790/2834-09350814.
Повний текст джерелаSakode, Prof V. M., and Prof A. D. Morankar. "Reversible Multiplier with Peres Gate and Full Adder." IOSR Journal of Electronics and Communication Engineering 9, no. 3 (2014): 43–50. http://dx.doi.org/10.9790/2834-09364350.
Повний текст джерелаSanjeevaiah, Girija, and Sangeetha Bhandari Gajanan. "Design of efficient reversible floating-point arithmetic unit on field programmable gate array platform and its performance analysis." International Journal of Electrical and Computer Engineering (IJECE) 13, no. 1 (February 1, 2023): 697. http://dx.doi.org/10.11591/ijece.v13i1.pp697-708.
Повний текст джерелаRajmohan, V., and O. Uma Maheswari. "Design of Compact Baugh-Wooley Multiplier Using Reversible Logic." Circuits and Systems 07, no. 08 (2016): 1522–29. http://dx.doi.org/10.4236/cs.2016.78133.
Повний текст джерелаRaveendran, Sithara, Pranose J. Edavoor, Y. B. Nithin Kumar, and M. H. Vasantha. "Inexact Signed Wallace Tree Multiplier Design Using Reversible Logic." IEEE Access 9 (2021): 108119–30. http://dx.doi.org/10.1109/access.2021.3100892.
Повний текст джерелаDayal, Anand, and Himanshu Shekhar. "A Result Analysis of ASIC Design of Reversible Multiplier Circuit." International Journal of Computer Applications 160, no. 8 (February 22, 2017): 40–43. http://dx.doi.org/10.5120/ijca2017913071.
Повний текст джерелаAlexander, S. "Design and Implementation of Efficient Reversible Multiplier Using Tanner EDA." International Journal of MC Square Scientific Research 5, no. 1 (June 6, 2013): 15–22. http://dx.doi.org/10.20894/ijmsr.117.005.001.003.
Повний текст джерелаSagar, Sagar. "Design of Low Power Vedic Multiplier Based on Reversible Logic." International Journal of Engineering Research and Applications 07, no. 03 (March 2017): 73–78. http://dx.doi.org/10.9790/9622-0703027378.
Повний текст джерелаNayeem. "Efficient Reversible Montgomery Multiplier and Its Application to Hardware Cryptography." Journal of Computer Science 5, no. 1 (January 1, 2009): 49–56. http://dx.doi.org/10.3844/jcs.2009.49.56.
Повний текст джерелаAnanthaLakshmi, A. V., and G. F. Sudha. "Design of an Efficient Reversible Single Precision Floating Point Multiplier." Journal of Bioinformatics and Intelligent Control 4, no. 1 (March 1, 2015): 21–30. http://dx.doi.org/10.1166/jbic.2015.1109.
Повний текст джерелаNayeem. "Efficient Reversible Montgomery Multiplier and Its Application to Hardware Cryptography." Journal of Computer Science 5, no. 1 (January 1, 2009): 49–56. http://dx.doi.org/10.3844/jcssp.2009.49.56.
Повний текст джерелаPandey, Neeta, Nalin Dadhich, and Mohd Zubair Talha. "An Optimized and Cost Efficient Realization of Reversible Braun Multiplier." i-manager's Journal on Circuits and Systems 3, no. 3 (August 15, 2015): 17–24. http://dx.doi.org/10.26634/jcir.3.3.4781.
Повний текст джерелаBanerjee, Arindam, and Debesh Kumar Das. "The Design of Reversible Signed Multiplier Using Ancient Indian Mathematics." Journal of Low Power Electronics 11, no. 4 (December 1, 2015): 467–78. http://dx.doi.org/10.1166/jolpe.2015.1413.
Повний текст джерелаHridya, S., Dr S. Bhavani, Dr K. G. Dharani, and M. Darani Kumar. "A Multiplier Design based on Ancient Indian Vedic Mathematics Using Reversible Logic: A Review." Journal of Advanced Research in Dynamical and Control Systems 11, no. 10-SPECIAL ISSUE (October 31, 2019): 911–24. http://dx.doi.org/10.5373/jardcs/v11sp10/20192887.
Повний текст джерелаAnitha, R., R. Thenmozhi, M. Madhunila, and Sarat Kumar Sahoo. "A Comparitive Study of Vedic BCD Multiplier using Reversible Logic Gates." Research Journal of Applied Sciences, Engineering and Technology 11, no. 12 (December 25, 2015): 1298–304. http://dx.doi.org/10.19026/rjaset.11.2238.
Повний текст джерелаMukku, Venkateswarlu, and Jaddu MallikharjunaReddy. "An Area Efficient and High Speed Reversible Multiplier Using NS Gate." International Journal of Engineering Research and Applications 7, no. 01 (January 2017): 29–33. http://dx.doi.org/10.9790/9622-0701042933.
Повний текст джерелаPChavan, Arunkumar, Prakash Pawar, and Varun R. "Design of Pulse Detectors and Unsigned Sequential Multiplier using Reversible Logic." International Journal of Computer Applications 92, no. 4 (April 18, 2014): 11–17. http://dx.doi.org/10.5120/15996-4891.
Повний текст джерелаNandal, Amita, T. Vigneswaran, and Ashwani Rana. "Optimized Reversible Logic Based Add and Shift Multiplier Using Linear Transformation." Advanced Science, Engineering and Medicine 5, no. 5 (May 1, 2013): 431–35. http://dx.doi.org/10.1166/asem.2013.1282.
Повний текст джерелаPankaj, N. Rajeev, P. Venugopal, and Prasanthi Mortha. "Design of quantum cost efficient reversible multiplier using Reed-Muller expressions." International Journal of Computing Science and Mathematics 7, no. 3 (2016): 221. http://dx.doi.org/10.1504/ijcsm.2016.077861.
Повний текст джерелаKamaraj, A., and P. Marichamy. "Design of fault-tolerant reversible Vedic multiplier in quantum cellular automata." Journal of the National Science Foundation of Sri Lanka 47, no. 4 (December 17, 2019): 371. http://dx.doi.org/10.4038/jnsfsr.v47i4.9677.
Повний текст джерелаKumar, Ravi. "Implementation of the Binary Multiplier on CPLD Using Reversible Logic Gates." IOSR Journal of Electronics and Communication Engineering 12, no. 01 (March 2017): 40–42. http://dx.doi.org/10.9790/2834-1201034042.
Повний текст джерелаGowthami, Nekkanti, and K. Srilakshmi. "Design and Implementation of Reversible Multiplier using optimum TG Full Adder." IOSR Journal of Electronics and Communication Engineering 12, no. 03 (July 2017): 81–89. http://dx.doi.org/10.9790/2834-1203048189.
Повний текст джерелаAhmad, Nabihah, Ahmad Hakimi Mokhtar, Nurmiza binti Othman, Chin Fhong Soon, and Ab Al Hadi Ab Rahman. "VLSI Implementation of Fault Tolerance Multiplier based on Reversible Logic Gate." IOP Conference Series: Materials Science and Engineering 226 (August 2017): 012140. http://dx.doi.org/10.1088/1757-899x/226/1/012140.
Повний текст джерелаShukla, Vandana, O. P. Singh, G. R. Mishra, and R. K. Tiwari. "Reversible Realization of 4-Bit Vedic Multiplier Circuit with Optimized Performance Parameters." Sensor Letters 17, no. 10 (October 1, 2019): 826–31. http://dx.doi.org/10.1166/sl.2019.4155.
Повний текст джерелаD.V.R, Mohan, Vidyamadhuri K, RamaLakshmanna Y, and K. H. S. Suresh kumar. "Design of Low Power Multiplier using Reversible logic: A Vedic Mathematical Approach." IJARCCE 6, no. 3 (March 30, 2017): 96–102. http://dx.doi.org/10.17148/ijarcce.2017.6321.
Повний текст джерелаS M, Mayur. "Design of a Low Power Vedic Multiplier using BKG Reversible Logic Gate." International Journal for Research in Applied Science and Engineering Technology 6, no. 6 (June 30, 2018): 1586–90. http://dx.doi.org/10.22214/ijraset.2018.6232.
Повний текст джерелаYogeswari, K. "Design and Performance Comparison of 16-Bit UT Multiplier using Reversible Logic." International Journal for Research in Applied Science and Engineering Technology 7, no. 4 (April 30, 2019): 903–11. http://dx.doi.org/10.22214/ijraset.2019.4161.
Повний текст джерелаK N, Hemalatha, and Sangeetha B G. "Efficient Design of Compact 8-bit Wallace Tree Multiplier Using Reversible Logic." International Journal of Engineering and Manufacturing 12, no. 4 (August 8, 2022): 29–36. http://dx.doi.org/10.5815/ijem.2022.04.03.
Повний текст джерелаAkbar, Ehsan Pour Ali, Majid Haghparast, and Keivan Navi. "Novel design of a fast reversible Wallace sign multiplier circuit in nanotechnology." Microelectronics Journal 42, no. 8 (August 2011): 973–81. http://dx.doi.org/10.1016/j.mejo.2011.05.007.
Повний текст джерелаNandal, Amita. "Booth Multiplier using Reversible Logic with Low Power and Reduced Logical Complexity." Indian Journal of Science and Technology 7, no. 4 (April 20, 2014): 525–29. http://dx.doi.org/10.17485/ijst/2014/v7i4.15.
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