Дисертації з теми "Reliability characterization"

Silicon carbide (SiC) is a wide bandgap material capable of higher voltage and higher temperature operation compared to its silicon (Si) counterparts due to its higher critical electric field (E-field) and higher thermal conductivity. Using SiC, MOSFETs with a theoretical high temperature operation and reliability is achievable. However, current bottlenecks in high temperature SiC MOSFETs lie within the limitations of standard packaging. Additionally, there are reliability issues relating to the gate oxide region of the MOSFET, which is exacerbated through high temperature conditions. In this thesis, high temperature effects on current-generation SiC MOSFETs are studied and analyzed. To achieve this, a high temperature package is created to achieve reliable operation of a SiC MOSFET at junction temperatures of 300 °C. The custom, high temperature package feasibility is verified through studying trends in SiC MOSFET behavior with increasing temperature up to 300 °C by static characterization. Additionally, the reliability of SiC MOSFETs at 300 °C is tested with accelerated lifetime bias tests.
M.S.
Electrical devices that are rated for high temperature applications demand a use of a material that is stable and reliable at the elevated temperatures. Silicon carbide (SiC) is such a material. Devices made from SiC are able to switch faster, have a superior efficiency, and are capable of operating at extreme temperatures much better than the currently widely used silicon (Si) devices. There are limitations on SiC certain structures of SiC devices, such as the metal oxide semiconductor field effect transistor (MOSFET), have inherent reliability issues related to the fabrication of the device. These reliability issues can get worse over higher temperature ranges. Therefore, studies must be made to determine the feasibility of SiC MOSFETs in high temperature applications. To do so, industry standard tests are conducted on newer generation SiC MOSFETs to ascertain their use for said conditions.

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Alternative energy products are an increasingly common sight on military bases in the United States. Energy product reliability affects the sustainability and cost-effectiveness of these systems, which must be tested by outside entities to ensure quality. The purpose of this thesis is to perform component level reliability testing on a high voltage power capacitor used in an electrical vehicle solar charging system. A component level characterization was performed to better understand the physical attributes of these capacitors. This investigation identified the expected component lifetime and conditions in which this component will become less reliable. Results are compared to those published by the manufacturer.

This thesis aims at studying, characterizing and modeling the trapping and de-trapping mechanisms occurring during the ON-state operation mode and leading to the degradation of semiconductor power devices. In this operating condition, the combined effect of moderate electric fields, high currents and temperatures due to self-heating effects can seriously affect the long-term reliability leading to device failure. Detailed analyses are performed on both silicon and gallium nitride based technologies by means of accelerated life test methods and electro-thermal simulations, aimed at understanding the physical origins of the degradation. In particular, this thesis provides the following contributions: i) the role of the interface and oxide trapped charge induced by negative bias temperature instability (NBTI) stress in p-channel Si-based U-MOSFETs is investigated. The impact of relevant electrical and physical parameters, such as stress voltage, recovery voltage and temperature, is accounted for and proper models are also proposed. In the field of innovative semiconductor power devices, this work focuses on the study of GaN-based devices. In particular, three different subtopics are considered: ii) a thermal model, accounting for the temperature dependence of the thermal boundary resistance (TBR), is implemented in TCAD simulator in order to realistically model self-heating effects in GaN-based power devices; iii) the degradation mechanisms induced by ON-state stress in GaN-based Schottky barrier diodes (SBDs) are proposed by analyzing their dependence on the device geometry; iv) the trapping mechanisms underlying the time-dependent gate breakdown and their effects on the performance of GaN-based power HEMTs with p-type gate are investigated, and an original empirical model representing the relationship between gate leakage current and time to failure is proposed.

The increased demand of offshore power conversion systems is driven by newly initiated offshore projects for wind farms and oil production. Because of long distances to shore and inaccessibility of the equipment long repair times must be expected. At the same time the offshore environment is extremely harsh. Thus, high reliability is required for the converters and it is important to have good knowledge of the switching devices. This thesis investigates switching characteristics and losses of commercially available IGBT modules to be used for this application. It focuses on switching time and switching energy losses depending on gate resistance, current and voltage levels, operation temperatures, and show differences between several devices of the same type. Some test show how device characteristics and losses when the device has been exposed to stress over a certain period.

Die-attachment, as the first level of electronics packaging, plays a key role for the overall performance of the power electronics packages. Nanosilver sintering has becoming an emerging solder-free, environmental friendly die-attach technology. Researchers have demonstrated the feasibility of die-attachment on silver (Ag) or gold (Au) surfaces by pressure-less or low-pressure (< 5 MPa) nanosilver sintering. This study extended the application of nanosilver sintering die-attach technique to copper (Cu) surface. The main challenge of nanosilver sintering on Cu is the formation of thick Cu oxide during processing, which may lead to weak joints. In this study, different processes were developed based on the die size: for small-area dice (< 5 * 5 mm2), different sintering atmospheres (e.g. forming gas) were applied to protect Cu surface from oxidation; for large-area dice (> 5 * 5 mm2), a double-print, low-pressure (< 5 MPa) assisted sintering process was developed. For both processes, die-shear tests demonstrated die-shear strength can reach 40 MPa. The effects of different sintering parameters of the processing were analyzed by different material characterization techniques. With forming gas as sintering atmosphere, not only Cu surface was protected from oxidation, but also the organics in the paste were degraded with nanosilver particles as catalyst. External pressure applied in the processing not only increased the density of sintered Ag, but also enhanced the contact area of sintered-Ag/Cu interface. Microstructure of Ag/Cu interface were characterized by transmission electron microscopy (TEM). Characterization results indicate that Ag/Cu metallic bonds formed at the interface, which verified the high die-shear strength of the die-attachment. Thermal performance of nanosilver sintered die-attachment on Cu was evaluated. A system was designed and constructed for measuring both transient thermal impedance (Zth) and steady-state thermal resistance (Rth) of insulated gate bipolar transistor (IGBT) packages. The coefficient of variation (CV) of Zth measurement by the system was lower than 0.5%. Lead-free solder (SAC305) was applied in comparison of thermal performance with nanosilver paste. With same sample geometry and heating power level, nanosilver sintered joints on Cu showed in average 12.6% lower Zth and 20.1% lower Rth than SAC305 soldered joints. Great thermal performances of nanosilver sintering die-attachment on Cu were mainly due to the low thermal resistivity of sintered-Ag and the good bonding quality. Both passive temperature cycling and active power cycling tests were conducted to evaluate the reliability of nanosilver sintered joints on Cu. For passive temperature cycling tests (-40 - 125 C), the die-shear strengths of mechanical samples had no significant drop over 1000 cycles, and nanosilver sintered IGBT on Cu packages showed almost no change on Zth after 800 cycles. For active power cycling test (Tj = 45 - 175 C), nanosilver sintered IGBT on Cu assembly had a lifetime over 48,000 cycles. The failure point of the assembly was the detachment of the wirebonds. Great reliability performances of nanosilver sintered die-attachment on Cu were mainly due to the low mismatch of coefficient of thermal expansion (CTE) between sintered-Ag and Cu. Meanwhile, low inter-diffusion rate between Ag and Cu prevented the interface from the reliability issue related to Kirkendall voids, which often took place in tin (Sn) -based solder joints.
Ph. D.

As technologies continue advancing, semiconductor devices with dimensions in nanometers have entered all spheres of human life. This research deals with both the statistical aspect of reliability and some electrical aspect of reliability characterization. As an example of nano devices, TaO_x-based high k dielectric thin films are studied on the failure mode identification, accelerated life testing, lifetime projection, and failure rate estimation. Experiment and analysis on dielectric relaxation and transient current show that the relaxation current of high k dielectrics is distinctive to the trapping/detrapping current of SiO₂; high k films have a lower leakage current but a higher relaxation current than SiO₂. Based on the connection between polarization-relaxation and film integrity demonstrated in ramped voltage stress tests, a new method of breakdown detection is proposed. It monitors relaxation during the test, and uses the disappearing of relaxation current as the signal of a breakdown event. This research develops a Bayesian approach which is suitable to reliability estimation and prediction of current and future generations of nano devices. It combines the Weibull lifetime distribution with the empirical acceleration relationship, and put the model parameters into a hierarchical Bayesian structure. The value of the Bayesian approach lies in that it can fully utilize available information in modeling uncertainty and provide cogent prediction with limited resources in a reasonable period of time. Markov chain Monte Carlo simulation is used for posterior inference of the reliability projection and for sensitivity analysis over a variety of vague priors. Time-to-breakdown data collected in the accelerated life tests also are modeled with a bathtub failure rate curve. The decreasing failure rate is estimated with a non-parametric Bayesian approach, and the constant failure rate is estimated with a regular parametric Bayesian approach. This method can provide a fast and reliable estimation of failure rate for burn-in optimization when only a small sample of data is available.

Enclosed in this thesis work it can be found the results of a three years long research activity performed during the XXIV-th cycle of the Ph.D. school in Engineering Science of the Università degli Studi di Ferrara. The topic of this work is concerned about the electrical characterization, physics, modeling and reliability of innovative non-volatile memories, addressing most of the proposed alternative to the floating-gate based memories which currently are facing a technology dead end. Throughout the chapters of this thesis it will be provided a detailed characterization of the envisioned replacements for the common NOR and NAND Flash technologies into the near future embedded and MPSoCs (Multi Processing System on Chip) systems. In Chapter 1 it will be introduced the non-volatile memory technology with direct reference on nowadays Flash mainstream, providing indications and comments on why the system designers should be forced to change the approach to new memory concepts. In Chapter 2 it will be presented one of the most studied post-floating gate memory technology for MPSoCs: the Phase Change Memory. The results of an extensive electrical characterization performed on these devices led to important discoveries such as the kinematics of the erase operation and potential reliability threats in memory operations. A modeling framework has been developed to support the experimental results and to validate them on projected scaled technology. In Chapter 3 an embedded memory for automotive environment will be shown: the SimpleEE p-channel memory. The characterization of this memory proven the technology robustness providing at the same time new insights on the erratic bits phenomenon largely studied on NOR and NAND counterparts. Chapter 4 will show the research studies performed on a memory device based on the Nano-MEMS concept. This particular memory generation proves to be integrated in very harsh environment such as military applications, geothermal and space avionics. A detailed study on the physical principles underlying this memory will be presented. In Chapter 5 a successor of the standard NAND Flash will be analyzed: the Charge Trapping NAND. This kind of memory shares the same principles of the traditional floating gate technology except for the storage medium which now has been substituted by a discrete nature storage (i.e. silicon nitride traps). The conclusions and the results summary for each memory technology will be provided in Chapter 6. Finally, on Appendix A it will be shown the results of a recently started research activity on the high level reliability memory management exploiting the results of the studies for Phase Change Memories.

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1996.
Includes bibliographical references (leaves 52-54).
by Huy X.P. Le.
M.Eng.

Thesis (M.S. in Aeronautical Engineering)--Naval Postgraduate School, June 1990.
Thesis Advisor(s): Wu, Edward M. "June 1990." Description based on signature page as viewed on October 21, 2009. DTIC Identifier(s): Graphite fiber strength testing, graphite fiber statistical evaluation. Author(s) subject terms: Graphite fiber strength testing, graphite fiber statistical evaluation, composite reliability predictions. Includes bibliographical references (p. 78-79). Also available in print.

GaN-based high electron mobility transistors (HEMTs) have excellent performance for power applications. Indeed, characteristics such as the high breakdown electric filed (3.3 MV/cm), the low ON-Resistance (RON) and the good thermal dissipation make the GaN-based diode and transistor a good potential for high frequency and power applications. The other outstanding feature of GaN-based HEMTs is the high electron mobility (1200 cm2/V.s) of the 2-dimensional electron gas (2DEG), formed at the interface between AlGaN and GaN, which leads to a low channel resistance and a high current density. This thesis presents an overview of the most relevant trapping and degradation mechanisms that limit the performance and lifetime of GaN-based transistors for power electronics applications. To that end, pulsed I-V and drain current transient measurements are employed in order to investigate the trapping effects. The degradations of AlGaN/GaN MIS-HEMTs submitted to the gate step-stress experiments are investigated in the first part of this thesis. The results, that are obtained by a combined electrical and optical characterization over the different voltages, are discussed in chapter 2 which indicate the existence of a field- and hot-electron induced phenomena as the AlGaN/GaNMIS-HEMTs degradation mechanism. A specific discussion is devoted to investigate the proton irradiation effect on the dynamic-Ron in HEMTs and is presented in chapter 3. It is shown that the proton irradiation is an effective and controllable method to reduce the dynamic-Ron in AlGaN/GaN HEMTs. Indeed, it is shown that samples that are submitted to a proton irradiation at high fluences (1.5£1014 cm– 2, 3MeV) exhibit a complete suppression of dynamic-Ron (complete voltage range, 150°C). This chapter further continuous to describe the voltage and temperature-dependent pulsed I-V characteristics of 650 V-rated transistors. It also points out the physical origin of dynamic RON in these devices. Furthermore, owing to the positive and stable threshold voltage, the low on-resistance and the high breakdown field, the p-GaN gate GaN-based transistors are commonly accepted as promising devices for application in power converters. To that end, chapter 4 deals with the mechanisms that limit the dynamic performance and the reliability of normally-off GaN-based transistors. This chapter proposed the suppression of threshold voltage instability by a suitable passivation on the p-GaN sidewall. The improved reliability of device highlights that hole trapping mostly takes place on the sidewalls. Finally, in chapter 5, a low leakage current and a state-of-the-art vertical breakdown voltage of above 1400 V a carbon-free GaN-on-Si device are demonstrated. These characteristics are achieved thanks to a thick and excellent crystal quality of GaN buffer. Indeed, low trapping effects are observed all the way to 1200 V with a low dependency of the substrate bias on the current density. The first demonstration of trap-free at such high voltage with this material system, could paves the way for 1200 V applications with GaN-on-Si resulting in a lower Ron and thus higher efficiency as compared to SiC and Si devices.

Nowadays, numerous power electronics application requires operation at high temperatures. In order to address increasing change of reliability problems in power die attachments for high temperature and high reliability applications, sintering Ag nanoparticles has been used as bonding material for this work. Firstly, quantitative microstructure characterization of as-sintered Ag joints has been carried out. The resulting normalized thickness, pore size and porosity decreased, and grain size increased with increasing the sintering time. A time dependence of the form t1/n with n close to 2 or 3 can be further derived for the kinetics of the thinning, densification and grain growth within the sintered Ag joints. From the results can be seen, sintering kinetics is still in the intermediate stage, the densification had not been completed, and Ag grain would continue growing afterwards, which could further explain degradation behaviours of sintered joints during isothermal ageing tests and thermal cycling tests. Secondly, sintered Ag joints with four kinds of substrate metallization have been subjected to isothermal ageing tests at temperatures of 150°C, 200°C and 250°C for up to 32 days. The different microstructure patterns of sintered joints with four substrate finishes during isothermal ageing tests have been presented and compared, which could use the results to explain part of the degradation behaviours of the sintered Ag joints during thermal cycling tests and guide selection of suitable substrate finish for the die attachments in high temperature power electronic system. Furthermore, thermal cycling tests have been carried out to investigate the reliability of two sizes of sintered Ag joints and solder joints during temperature cycling between -55°C to 125°C and -55°C to 150°C. Microstructure evolution of sintered Ag joints was investigated by non-destructive and destructive characterization methods, which revealed the factors which could effect on the degradation during thermal cycling tests. With microstructure features of sintered joints observed from X-ray tomography and SAM, because a specific specimen can be evaluated over its lifetime, a true image of microstructure evolution of damage during operation can be obtained, and crack and degradation can be observed three-dimensionally.

Thesis (M.S.)--University of California, San Diego, 2008.
Title from first page of PDF file (viewed August 1, 2008). Available via ProQuest Digital Dissertations. Includes bibliographical references (p. 190-193).

Le sujet de cette thèse est l’analyse de la fiabilité des transistors bipolaires à hétérojonction SiGe:C et descircuits intégrés associés. Dans ce but, un modèle compact prenant en compte l’évolution des caractéristiquesdes transistors SiGe:C a été développé. Ce modèle intègre les lois de vieillissement des mécanismes dedéfaillance des transistors identifiés lors des tests de vieillissement. Grâce aux simulations physiques TCADcomplétées par une analyse du bruit basses fréquences, deux mécanismes de dégradations ont été localisés. Eneffet, selon les conditions de polarisation, des porteurs chauds se retrouvent injectés aux interfaces dutransistor. Ces porteurs chauds ont suffisamment d’énergie pour dégrader l’interface en augmentantprogressivement leurs densités de pièges. L’une des deux interfaces dégradées se situe au niveau del’’’espaceur’’ émetteur-base dont l’augmentation de la densité de piège dépend des porteurs chauds créés parionisation par impact. L’autre interface dégradée se situe entre le silicium et le STI dont l’augmentation dedensité de pièges dépend des porteurs chauds générés par ionisation par impact et/ou par génération Auger.En se basant sur ces résultats, une loi de vieillissement a été incorporée dans le modèle compact HICUM. Enutilisant ce modèle, l’étude de l’impact des mécanismes de défaillance sur un circuit amplificateur faible bruit aété menée. Cette étude a montré que le modèle compact intégrant les lois de vieillissement offre la possibilitéd’étudier la fiabilité d’un circuit complexe en utilisant les outils de conception standard permettant ainsi dediminuer le temps de conception global
The SiGe:C HBT reliability is an important issue in present and future practical applications. To reduce the designtime and increase the robustness of circuit applications, a compact model taking into account aging mechanismactivation has been developed in this thesis. After an aging test campaign and physical TCAD simulations, onemain damage mechanism has been identified. Depending on the bias conditions, hot carriers can be generatedby impact ionization in the base-collector junction and injected into the interfaces of the device where trapdensity can be created, leading to device degradation. This degradation mechanism impacting the EB/spacerinterface has been implemented in the HICUM compact model. This compact model has been used to performreliability studies of a LNA circuit. The CPU simulation time is not impacted by the activation of the degradationcompact model with an increase in computation time lower than 1%. This compact model allows performing areliability analysis with conventional circuit simulators and can be used to assist the design of more robustcircuits, which could help in reducing the design time cycle
L’affidabilità dei transistori a eterogiunzione SiGe:C è un aspetto molto importante nella progettazione circuitale,sia per le tecnologie attuali che per quelle in fase di sviluppo. In questo lavoro di tesi è stato sviluppato un modellocompatto in grado di descrivere i principali meccanismi di degrado, in modo da contribuire alla progettazione dicircuiti relativamente più robusti rispetto a tali fenomeni, ciò che potrebbe favorire una riduzione dei tempi diprogetto. A seguito di una campagna sperimentale e di un’analisi con tecniche TCAD, è stato identificato unmeccanismo principale di degrado. In particolari condizioni di polarizzazione, i portatori ad elevata energiagenerati per ionizzazione a impatto nella regione di carica spaziale, possono raggiungere alcune interfacce deldispositivo e ivi provocare la formazione di trappole. Solo la generazione di trappole relativa allo spaceremettitore-base è stata considerata nella formulazione del modello, essendo il fenomeno più rilevante. Ilmodello è stato utilizzato per effettuare alcuni studi di affidabilità di un amplificatore a basso rumore. Il tempocomputazionale non è significativamente influenzato dall’attivazione del modello di degrado, aumentando solodell’1%. Il modello sviluppato è compatibile con i comuni programmi di simulazione circuitale, e può essereimpiegato nella progettazione di circuiti con una migliore immunità rispetto ai fenomeni di degrado,contribuendo così a un riduzione dei tempi di progetto

The main goal of this thesis is the failure and reliability investigation of RF-MEMS switches and photovoltaic solar cells. For technical developer people the reliability issue is often consider a secondary problem in electronic devices since it is not considered an important factor in the production chain. This concept is changing is the last years because reliability studies are considered an important technological step to improve the production process. This fact is confirmed by the investments that companies adopt to test their products. In the particular case of this thesis, we can easily mention the solar cell production line where the cells are subjected to reliability tests that extrapolate the efficiency and the fill factor in order to study the performances and to consequently improve the production process. Concerning RF MEMS Wireless communication systems for space applications require electronic components with a high level of reliability, a low power consumption and they should be as small as possible in order to be better integrated in satellites. Radio Frequency Micro Electro Mechanical System (RF-MEMS) can be considered one of the best candidates to comply with previous requirements and, under certain conditions, they can completely replace an entire solid-state circuit. RF-MEM devices in general are characterized by a good miniaturization, an easily integration in a standard solid-state circuit, an almost zero power consumption, a good RF linearity and a high quality factor Q. Concerning RF-MEMS switches RF performances, they exhibit a very low insertion loss, lower than 0.1 dBm up to 60 GHz and, at the same time, a good isolation, more than 20 dBm. From an electrical and mechanical point of view the power consumption of these switches is close to zero because of an “on-state” current around pA and they are almost unaffected by high level of acceleration or deceleration because of their mass that is extremely small. The possibility to integrate the production of these devices in the standard foundry silicon processes and their integration with mature semiconductor technology are a great advantage for their spread making possible to produce them in an easy and cheap way. Over the last 10 years important developments on MEMS switches have been done all over the world. As a matter of fact, these switches are quite attractive since they combine excellent RF performances and low power consumption of mechanical switches with the small size and low weight of semiconductor devices. However, the appearance of MEMS switches on the market has been hindered by the need for specific packaging as well as by reliability issues. Reliability is a major issue for any satellite since it is almost impossible to envisage any repair work once the spacecraft has been launched. Hence, reliability is a key driver when designing any RF equipment. If we consider a RF-MEMS switch, we have to guarantee that his electromechanical performances will be the same after an intensive usage in harsh environment, for instance after millions or billions of cycles and after the exposure to different kind of radiations. In case of their application in a redundancy scheme, they have to be completely operative even after a long period of activity or inactivity. The aim of this thesis is to perform an electrical characterization and several reliability tests on different kind of RF-MEMS switches in order to analyze which are the weaknesses and the strengths of this new technology. Electrical characterizations have been done using two different measurement systems. The first, based on a vector network analyzer and a power supply, has been used to test the RF performances of the devices and to extract the actuation and deactuation voltages. The second set up, based on the internal RF signal generator of the VNA, an 8-GHz digital signal oscilloscope and a profilometer (polytec MSA 500), has been used to characterize the electrical performances like actuation time, release delay and dynamic performances. Cycling stress, one of the most common test used to understand the robustness of this kind of devices, has been performed on different topologies of switch in order to better understand how some parameters of the RF MEMS switch, such as the shape of the beams or the actuation voltage, impact on the reliability of the device. Furthermore, the influence of continuous actuation stress on the reliability of dielectric-less switches has been investigated, comparing different designs and studying the variation of the main electrical parameters induced by the stress and the successive recovery phase. Concerning PV solar cells A solar cell, or photovoltaic cell, is an electrical device that converts the energy of light directly into electricity by the photovoltaic effect. The operation of a photovoltaic (PV) cell requires 3 basic attributes: (i) the absorption of light, generating either electron-hole pairs or excitons, (ii) the separation of charge carriers of opposite types and (iii) the extraction of those carriers to an external circuit. Over the last decades, many research groups have tried to improve the conversion processes in order to increase the efficiency of solar cells and to reduce the parasitic effects that limit the energy conversion. This has generated a real challenge to the best conversion efficiency. The average efficiency of multicrystalline silicon solar cells at the beginning of 2014 was about 16% but in research labs different solar cells have exceeded the 20% with records over 24%. The continuous growth of the solar cells efficiency has been achieved thanks to the reliability study of the single cells and to the degradation analysis of the real photovoltaic systems. These studies have revealed the critical points of PV solar cells and have led to a constant improvement of the production processes. The aim of this thesis is the study of the reliability problems related to a single solar cell and to a string of solar cells subjected to different illumination conditions. Different characterization procedures have been developed in order to study the failure mechanisms and to study the weaknesses and the strengths of the technology. Four types of measurement set-ups have been utilized: (i) the first system is able to extract the IV curves in dark and light conditions. This simple measurement procedure has to be opportunely calibrated in order to obtain right results in term of efficiency and fill factor. (ii) The second system extracts the thermographic image of a single solar cell. It can be used to analyze hot spot and other failure mechanisms in the silicon structure. (iii) The third system extracts the electroluminescence and the photoluminescence of a single solar cell. It is able to extract and analyze the defects in the crystalline structure of the materials. (iv) The fourth is the LOANA system: a commercial tool able to extract the External Quantum Efficiency and the Internal Quantum Efficiency with the measurement of the reflectance. All these characterization procedures have been utilized to study the evolution of the failure mechanisms when a single solar cell is subjected to reverse biasing stresses. The study of the catastrophic degradation of solar cells submitted to reverse current stress is of crucial importance since the failure can lead to the rapid increase of the temperature with a consequent risk of fire and to the breaking of the entire PV system. This particular situation can occur when the PV system is not uniformly illuminated and the solar cells of the system present not uniform shunt resistance. Additional studies have been performed in the modelization of a solar cell with the two-diode model. The study and modeling of solar cells allow to obtain right results in term of efficiency and fill factor extrapolation. Moreover, the modelization allows the study of string of solar cells working in particular conditions in which the illumination level is not uniform in a whole panel. The simulations allow to predict the dangerous situations and to design appropriate prevention systems.
Lo scopo principale di questa tesi è investigare i meccanismi di rottura e l'affidabilità di interruttori RF MEMS e celle solari. I problemi affidabilistici sono spesso considerati dagli sviluppatori un problema secondario nei dispositivi elettronici dal momento che non sono considerati un fattore importante nella catena produttiva. Questo concetto sta cambiando negli ultimi anni visto che gli studi affidabilistici stanno diventando uno step tecnologico per migliorare i processi produttivi stessi. Questo fatto è confermato dagli innumerevoli investimenti che le aziende stanno elargendo per testare i loro prodotti. Nel caso particolare di questa tesi possiamo facilmente menzionare la linea produttiva di una cella solare dove le celle sono soggette a test di affidabilità che estrapolano l'efficienza e il fill factor. Questo permette di studiare le prestazioni delle celle e di conseguenza di migliorare il processo produttivo. Interruttori RF MEMS I sistemi di comunicazione Wireless per applicazioni spaziali richiedono componenti elettronici con un alto livello di affidabilità, un consumo di potenza basso e un’occupazione di spazio ridotta in modo da essere integrati in un satellite. Gli interruttori microelettromeccanici (RF-MEMS) possono essere considerati per sostituire i dispositivi meccanici attuali e, in determinate condizioni, possono sostituire un intero circuito a stato solido. I dispositivi RF MEMS in generale sono caratterizzati da una buona miniaturizzazione, una buona capacità di integrazione nei circuiti a stato solido, un consumo di potenza quasi nullo, una buona linearità e una alto fattore di qualità Q. Riguardo le prestazioni, gli interruttori RF MEMS presentano una bassa perdita per inserzione, minore di 0.1 dBm fino a 60 GHz e, allo stesso tempo, un buon isolamento, maggiore di 20 dBm. Dal punto di vista elettro meccanico il consumo di potenza è vicino allo zero a causa della corrente di "on-state” vicina ai picoAmpere. Inoltre questi dispositivi non risultano disturbati dagli alti livelli di accelerazione e decelerazione (a causa della loro massa molto piccola). La possibilità di integrare la produzione di questi dispositivi nei processi standard di lavorazione del silicio e l'integrazione con tecnologie al silicio ormai mature sono dei grandi vantaggi per la loro diffusione su larga scala e per l'abbattimento dei costi di produzione. Negli ultimi dieci anni molti miglioramenti sono stati fatti sugli switch MEMS da vari gruppi di ricerca. Gli switch RF MEMS stanno diventando interessanti per le loro prestazioni RF, per il loro basso consumo di potenza, per le piccole dimensioni e basso peso. Nonostante le loro prestazioni, la diffusione sul mercato è stata rallentata per la necessità di package specifici e per i loro problemi di affidabilità. L'affidabilità dei dispositivi RF MEMS è un fattore predominante in applicazioni spaziali dal momento che risulta impossibile qualsiasi intervento di manutenzione una volta che il satellite è stato lanciato. Quindi per applicazioni spaziali l'affidabilità deve essere considerata un fattore dominante nella fase di progettazione di ogni switch MEMS. Infatti dobbiamo garantire che le sue proprietà elettromagnetiche rimangano le stesse dopo un periodo di utilizzo prolungato in ambiente ostile, per esempio dopo milioni o bilioni di cicli e dopo la continua esposizione a diversi tipo di radiazioni. In caso di utilizzo di switch MEMS in schemi di ridondanza, devono essere completamente funzionanti anche dopo un lungo periodo di attività o inattività (mesi o anni). Lo scopo di questa tesi è di effettuare caratterizzazioni di tipo elettrico e diverse tipologie di stress di affidabilità su switch RF MEMS in modo da studiare la tipologia di dispositivo più promettente e robusta. La caratterizzazione elettrica è stata eseguita utilizzando due diversi sistemi di misura. Il primo, basato su un "Vector network analyzer" e alimentatori, è stato utilizzato per verificare le prestazioni RF dei dispositivi ed estrapolare le tensioni di attuazione e disattuazione dei singoli dispositivi. Il secondo sistema di misura, composto dal generatore interno del "Vector network analyzer", da un oscilloscopio digitale con banda di 8-GHz e un profilometro ottico (polytec MSA 500), è stato utilizzato per caratterizzare le prestazioni elettriche e meccaniche come il tempo di attuazione, il ritardo introdotto in fase di rilascio e le prestazioni dinamiche dei dispositivi. Lo stress di tipo "Cycling", uno dei test di affidabilità più comuni usato per comprendere la robustezza dei dispositivi, è stato eseguito su differenti tipologie di dispositivi per comprendere come le caratteristiche intrinseche dei dispositivi (per esempio la forma del ponte mobile) possano impattare sull'affidabilità del dispositivo stesso. Oltre a stress di tipo "Cycling" si è studiato l'influenza di stress di attuazione prolungata sull'affidabilità di dispositivi senza dielettrico, comparando differenti design e studiando la variazione dei parametri elettrici indotti dallo stress prolungato e dalle successive fasi di rilassamento dei dispositivi. Celle Solari Una cella solare, o cella fotovoltaica, è un dispositivo elettronico che converte l'energia della luce direttamente in energia elettrica attraverso l'effetto fotovoltaico. Il funzionamento delle celle fotovoltaiche richiede 3 principi di base: (i) l'assorbimento della luce, generando coppie elettrone lacuna, (ii) la separazione delle cariche generate e (iii) l'estrazione di queste cariche attraverso un circuito esterno opportunamente dimensionato. Nelle ultime decadi molti gruppi di ricerca hanno provato ad incrementare il processo di conversione in modo da aumentare l'efficienza delle celle solari e ridurre così gli effetti parassiti che limitano il processo di conversione dell'energia. Tutto questo ha generato una vera e propria corsa alla migliore cella fotovoltaica in termini di efficienza di conversione. L'efficienza media di una cella solare multicristallina all'inizio del 2014 era di circa il 16% ma in alcuni laboratori di ricerca molte celle solari superavano il limite del 20% con record superiori al 24%. La continua crescita dell'efficienza delle celle solari è stata possibile anche grazie agli studi affidabilistici sulla cella solare singola e agli studi eseguiti sui meccanismi di degrado dei sistemi fotovoltaici esistenti. Questi studi hanno permesso di identificare i punti critici delle celle solari e hanno portato ad un costante aumento di prestazione dei processi produttivi. Lo scopo di questa tesi è lo studio dell'affidabilità delle singole celle fotovoltaiche e di stringhe di celle sottoposte a differenti livelli di illuminazione. Diverse procedure di caratterizzazione sono state sviluppate per studiare i meccanismi di rottura e per studiare i punti di forza e i punti deboli di questa tecnologia. Quattro diversi sistemi di misura sono stati utilizzati: (i) il primi sistema è in grado di estrapolare le curve corrente tensione al buio e in condizione di illuminazione di una singola cella fotovoltaica. Questo sistema di misura apparentemente semplice deve essere opportunamente calibrato in modo da ottenere risultati corretti in termine di efficienza e fill factor. (ii) Il secondo sistema di misura permette di estrarre l'immagine termografica di una singola cella fotovoltaica. Può essere utilizzato per analizzare la presenza di "hot spot" e altri meccanismi di rottura nella struttura cristallina della cella solare. (iii) Il terzo sistema permette di estrarre l'elettroluminescenza e la fotoluminescenza di una singola cella solare. Questo sistema permette di analizzare la presenza di difetti nella struttura cristallina della cella stessa. (iv) Il quarto sistema di misura è il sistema commerciale LOANA (PVTools): questo strumento permette di estrarre l’efficienza quantica esterna e interna attraverso misure di riflettività. Tutte questi sistemi di misura sono stati utilizzati per studiare l'evoluzione dei meccanismi di rottura quando una singola cella fotovoltaica viene sottoposta a stress in polarizzazione inversa. Lo studio della rottura catastrofica di una cella solare sottoposta a stress in polarizzazione inversa è di cruciale importanza dal momento che la rottura di una singola cella può portare an un aumento repentino della temperatura con conseguente rischio di incendio e rottura dell'intero sistema fotovoltaico. Questa particolare situazione può accadere quando un pannello fotovoltaico non è illuminato in modo uniforme e le singole celle fotovoltaiche presentano resistenza di "shunt" non uniformi in un singolo pannello. Studi addizionali sono stati eseguiti nella modellizzazione di una singola cella solare con il modello a due diodi. Lo studio e la modellizzazione di una cella solare permette di ottenere risultati corretti in termini di efficienza e fill factor. Inoltre la modellizzazione permette lo studio di stringhe di celle solari che lavorano in particolari condizioni di illuminazione non uniformi all'interno di uno stesso pannello fotovoltaico. Le simulazioni permetto di predire situazioni potenzialmente dannose e quindi di prevedere opportuni circuiti di protezione.

Thesis (M.S.)--Mechanical Engineering, Georgia Institute of Technology, 2004.
Daniel Baldwin, Committee Chair; Suresh Sitaraman, Committee Member; Steven Danyluk, Committee Member. Includes bibliographical references (leaves 238-241).

Non traduit
The introduction of nanometer technologies, has allowed the semiconductor industry to create nanoscale devices in combination with gigascale complexity. However, new technologies bring with them new challenges. In the era of large systems embedded in a single System-On-Chip and fabricated in continuously shrinking technologies, it is important to test and ensure fault-free operation of the whole system. The cost involved in semiconductor test has been steadily growing and testing techniques for integrated circuits are today facing many exciting and complex challenges. Although important advances have been made, existing test solutions are still unable to exhaustively cover all types of defects in advanced technology nodes. Consequently, innovative solutions are required to cope with new failure mechanisms under the constraints of higher density and complexity, cost and time to market pressure, product quality level and usage of low cost test equipment.The work of this thesis is focused on the development of silicon test and characterization methodologies that aid in the accurate detection and resolution of issues that may arise due to variability, manufacturing defects, wear-out or interference. A wide spectrum of these challenges has been addressed from a test perspective to ensure that the availability of effective test solutions does not become a bottleneck in the path towards further scaling. Additionally the advances and innovations introduced in the myriad domains of electronic design, reliability management, manufacturing process improvements etc. that call for the development of advanced, modular and agile test methodologies have been effectively covered within the scope of this work.This thesis presents the significant contributions made for enabling resolution of state of the art industrial test challenges via the design and implementation of novel test strategies (targeting the 28nm FDSOI technology node) for:•Detection & diagnosis of timing faults in standard cells.•Analysis of Setup and Hold margins within silicon.•Verification & reliability analysis of innovative test structures.•Analysis of on-chip self heating.•Enabling characterization and performance evaluation of high speed digital IPs

Thesis (M.S. in Electrical Engineering)--S.M.U.
Title from PDF title page (viewed Mar. 16, 2009). Source: Masters Abstracts International, Volume: 47-03. Adviser: Marc P. Christensen. Includes bibliographical references.

Dye-sensitized solar cells (DSC) have recently proved to be a low-cost alternative to inorganic photovoltaics and they could attract a remarkable market share in the future. On the other hand, reliability issues must be solved to improve the competitiveness of this new solar energy technology. The present thesis deals with a characterization and reliability study of DSC aiming to have a comprehensive picture of the efficiency, stability, and degradation mechanisms of DSC, with the purpose to promote these devices as an alternative energy source in agreement with the European Community directions. Since Michael Gratzel advanced the concept of sensitized materials and nanoporous semiconductors in 1991, dye-sensitized solar cells have attracted the interest of many academic and solar company researchers opening the road to photovoltaics of the third generation. Noticeable achievements in dye synthesis and wide band-gap semiconductor fabrication allow physicists, chemists, and engineers to produce more efficient and reliable DSC. At the time of this dissertation, DSC efficiency has reached 15% allowing them to compete with conventional inorganic photovoltaic systems in terms of cost and material complexity especially in those applications where the efficiency-to-production ratio cost must be maximized. There are several applications where the performances of photo-electrochemical solar cells are already sufficient: outdoor applications such as windows of buildings and greenhouse coverage; indoor applications such as windows, decoration structures, and shop windows. In spite of the advantages, many technological and reliability issues still have to be solved. Those include: the stability of the electrical characteristics, weak or damaged sealing, environmental related factors (i.e. UV exposure for outdoor applications), humidity, high temperature, and the improvement of DSC lifetime. Intensive research is performed by researchers all around the world to understand the reliability and causes of instability in DSC: those efforts involve the study of many physic aspects including the effects of the different layers and materials, morphology, dyes, electrolytes, counter electrodes, growth conditions and the presence of oxygen and moisture. The characterization methods used to understand and monitor the electrical properties of silicon-based solar cells cannot be used "`as is"' for DSC without considering the completely different nature of DSC compared to silicon-based solar cells. Starting from the knowledge about the characterization of silicon base solar cells and a background on electrochemistry, we carefully transposed the same characterization technique to DSC. Access to full details of the devices and to "`ad hoc"' structures for the analysis has been granted thanks to the collaboration with our University of Rome "`Tor Vergata"'. We developed a measurement procedure, which allows us to define the standards for the characterization of dye-sensitized solar cells. This procedure is based on DC measurements as well as electrochemical impedance spectroscopy (EIS), the latter coming from electrochemistry. This technique allowed us to characterize DSC interfaces and identify which interfaces were been degraded during accelerated tests. This measurement set gives a comprehensive description of the behavior of all analyzed devices. Our characterization and reliability study mostly involves the use of the AM1.5 solar simulator, where its spectrum spreads from UV to far IR wavelength. As an alternative illumination source, we designed a LED-based monochromatic light source in order to illuminate solar cells during characterization. We designed the illuminator as well as the driver circuitry. We found that these monochromatic sources trigger different portions of the solar cells’ absorption spectrum as a function of the illumination source wavelength, giving the possibility of gathering additional information about DSC efficiency and degradation. In addition, during accelerated stresses we found that the degradation kinetic of open-circuit voltage, short-circuit current, efficiency, and fill-factor change if the characterization is performed with different illumination source wavelengths. This fact points out that characterization performed under monochromatic light could give additional information about the degradation mechanism behind DSC degradation. To make a picture of DSC reliability, we carried out several accelerated stresses, stressing devices under different illumination sources. All these tests were carried out indoors. We analyzed the degradation of samples subjected to accelerated life tests with different illumination conditions and the role of the temperature on the device degradation by means of: the AM1.5 solar simulator, white LED, UV exposure, and both thermal and electrical stresses. Since DSC gain heat during sunlight exposure thereby increasing their temperature, we examined the role of temperature on the DSC degradation. We showed that the temperature alone may strongly impact on the degradation rate of DSC reducing the overall DSC performance; in addition, we proved that the temperature has a twofold impact on cell performance. A moderate temperature induces an annealing process: it enhances the performances of the dye material likely recovering and rearranging some dangling or weak bonds at the transparent semiconductor interface or among the dye molecules. On the other hand, at high temperatures or for longer storage times regardless of the temperature level, the temperature strongly reduces the DSC performance as well as its lifetime. In order to understand the effects induced by sun illumination exposure, we carried out accelerated optical stresses by means of AM1.5 solar simulator. Furthermore, we compared the degradation kinetics of DC parameters gathered from optical and thermal stresses. The responsible of the degradation during thermal or illumination stress is the formation of defects and chemical species at transparent semiconductor/sensitizer/electrolyte interface which reduces the charge transfer at interface and the ion migration across electrolyte. During optical stresses, we observed a main difference between the open-circuit degradation kinetics and the short-circuit degradation kinetics: the latter usually features a turnaround phase during optical stresses. The turnaround phase is strongly dependent on the illumination intensity used during the accelerated stress: the higher the illumination level, the shorter the turnaround phase. The device features faster degradation kinetics with higher illumination levels likely due increase of the interface temperature, as also confirmed by pure thermal stresses. High power-to-weight ratio allows DSC to be used as solar energy harvester in space application. To make some light on the high energetic photons effects (even present at ground level) on DSC, we performed accelerated UV illumination stresses. We designed and assembled a UV illuminator as well as the driving circuitry. We found that UV exposure has detrimental effects on DSC and the main responsible for the cell failure during UV exposure is the electrolyte bleaching. It is worth to remark that the sensitizer seems to have a minor role in cell degradation as we proved. Concerning DSC studied in this Thesis, we strongly recommend some solutions in order to prevent electrolyte bleaching. Good UV filtering and encapsulation bring benefits for a reliable operation over time, even though they potentially go against the low weight and transparency nature of DSC. High efficiency even at low illumination intensity or under diffused light allows DSC to be taken into account for indoor applications. We carried out accelerated stresses by means of high power white LED and we compared the DC parameters degradation kinetics as well as the EIS plot evolution measured by means both AM1.5 solar simulator and white-led illuminator. In addition, we proposed a white led-based illumination system as a cheap and versatile alternative to expensive AM1.5 solar simulator. We designed the white LED-based illuminator as well as the driving circuit. We found that white led exposure leads to the degradation of DSC performance and even though the white spectrum has not UV component, dye-molecules are not be able to absorb wavelength in the UV. Comparing white-led and AM1.5 solar simulator characterizations, we proved and showed that the latter provides more information than the former. From the solar panel point of view, some DSC could be run into failure or be shaded during solar exposure. This likely real situation forces a single cell or a whole DSC string to work under certain bias conditions. To examine this non-trivial real condition, we designed and assembled current drivers and we performed forward and reverse biased constant current stresses (CCS) on dye-sensitized solar cells kept in the dark. We showed that DC parameters feature different degradation rates depending on that bias polarity and current intensity. We showed that forward CCS lead to the modification in the electrolyte composition, lowering the dark current of the cell while reverse CCS lead to the degradation of counter-electrode, accelerating the corrosion of the counter electrode by the electrolyte. In addition, we proved that most degradation occurs at those interfaces where the electrons are emitted during stress.
Dye-sensitized solar cells (DSC) hanno recentemente dimostrato di essere un’alternativa a basso costo al fotovoltaico inorganico e in futuro non lontano potrebbero detenere una quota di mercato notevole. Tuttavia, i problemi di affidabilità devono essere risolti per migliorare la competitività di questa nuova tecnologia. La presente tesi tratta la caratterizzazione e lo studio affidabilità di DSC al fine di avere un quadro completo circa l'efficienza, la stabilità e i meccanismi di degradazione nelle DSC, al fine di promuovere questi dispositivi come un nuova fonte di energia rispettando inoltre le normative della Comunità Europea. Da quando Michael Grätzel nel 1991 avanzò il concetto di materiali sensibilizzati e semiconduttori nanoporosi, dye-sensitized solar cells hano attirato l'interesse di molti ricercatori universitari e di aziende operanti nel fotovoltaico, aprendo così la strada al fotovoltaico di terza generazione. Risultati notevoli nella sintesi di cromofori sempre più pancromatici e nella fabbricazione di semiconduttori ad ampio bad-gap, consentono a fisici, chimici ed ingegneri di produrre DSC sempre più efficienti e affidabili. Al momento di questa tesi, l’efficienza delle DSC ha raggiunto il 13.4% il che consente loro di competere con i sistemi fotovoltaici inorganici convenzionali in termini di costi di produzione e complessità materiale, in particolar modo in quelle applicazioni in cui il rapporto efficienza costi di produzione deve essere massimizzato. Ci sono diverse applicazioni in cui le prestazioni di queste celle solari foto-elettrochimiche sono già sufficienti: applicazioni outdoor, come le finestre degli edifici e la copertura delle serre; applicazioni indoor come finestre, strutture di decorazione, e le vetrate dei negozi. Nonostante i vantaggi, molti problemi tecnologici e di affidabilità devono ancora essere risolti. Alcune delle problematiche sono: stabilità delle caratteristiche elettriche, incapsulamento, effetti dei fattori ambientali (ad esempio l'esposizione ai raggi UV per applicazioni esterne), l'umidità, la temperatura elevata, l’incremento del lifetime. Un'intensa attività di ricerca è portata avanti da ricercatori di tutto il mondo per capire l'affidabilità e le cause di instabilità delle DSC: questi sforzi coinvolgono lo studio di molti aspetti fisici e chimici compresi gli effetti nell’uso di diversi materiali, strutture, morfologie, coloranti, elettroliti, contro-elettrodi, fabbricazione in condizioni e presenza di ossigeno e di umidità. I metodi di caratterizzazione utilizzati per caratterizzare celle solari silicon-based non possono essere utilizzati "as is" per le DSC senza considerare la diversa natura delle DSC rispetto alle celle silicon-based. Partendo dalla conoscenza nella caratterizzazione di celle solari silicon-based e da un background in elettrochimica, abbiamo attentamente trasposto i metodi di caratterizzazione alle DSC. L'accesso a tutti i dettagli tecnologici delle DSC sono disponibili grazie alla collaborazione con l'Università di Roma "Tor Vergata". Abbiamo sviluppato una procedura di misura che permette di definire gli standard per la caratterizzazione di dye-sensitized solar cells. Questa procedura si basa su misure DC e spettroscopia di impedenza (EIS), dove quest'ultima tecnica proviene dall’elettrochimica. Questa tecnica permette di caratterizzare le interfacce presenti nelle DSC e di identificare quali interfacce stanno degradando durante gli stress accelerati. Questo set di misure fornisce una descrizione completa delle celle e del loro comportamento durante gli stress accelerati. La caratterizzazione e lo studio di affidabilità viene esguita illuminando le celle con un simulatore solare AM 1.5, dove il suo spettro si estende dagli UV sino al lontano IR. Come fonte di illuminazione alternativa, abbiamo progettato una sorgente di luce monocromatica basata su LED per illuminare le celle solari durante la caratterizzazione. Abbiamo progettato l'illuminatore nonché la circuiteria di pilotaggio. Abbiamo scoperto che queste sorgenti monocromatiche eccitano una porzione diversa dello spettro di assorbimento delle celle: in particolare, la porzione dello spettro eccitata è funzione della lunghezza d'onda della sorgente di illuminazione. Ciò permette di avere ulteriori informazioni sull’efficienza e sulla degradazione delle DSC. Inoltre, durante gli aging test, abbiamo notato che la cinetica di degradazione della tensione di circuito aperto, della corrente di corto circuito, dell'efficienza, e del fill factor, cambia se la caratterizzazione viene eseguita con diverse lunghezze d'onda della sorgente di illuminazione. Questo fatto sottolinea che la caratterizzazione effettuata con luce monocromatica potrebbe dare ulteriori informazioni sul meccanismo di degradazione che causa il degrado delle DSC. Per avere un quadro sull’affidabilità delle DSC, abbiamo effettuato molti ageing test, con altrettante fonti di illuminazione o in generale di stress. Tutte queste prove sono state effettuate indoor. Abbiamo studiato il degrado delle celle sottoposte a stress accelerati con diverse condizioni di illuminazione e il ruolo della temperatura nel degrado delle celle. Questo studio è stato possbile effettuando stress accelerati per mezzo di: simulatore solare AM1.5, camere climatiche, illuminatore a LED bianco, illuminatore UV, e driver in corrente per gli constant current stress (CCS). Poiché le DSC si scaldano durante l'esposizione alla luce solare e quindi la loro temperatura interna aumenta, abbiamo cercato di capire il ruolo della temperatura nella degradazione delle DSC. Abbiamo dimostrato che la sola temperatura può incidere fortemente sul tasso di degradazione delle DSC riducendo le prestazioni complessive delle celle; inoltre, abbiamo dimostrato che la temperatura ha un duplice impatto sulle prestazioni delle celle. Una temperatura moderata induce un processo di annealing: migliora le prestazioni del colorante probabilmente ristabilendo alcuni legami liberi o deboli all'interfaccia semiconduttore trasparente/colorante o tra le molecole di colorante. D'altra parte, a temperature elevate o per tempi più lunghi di stress, indipendentemente dal livello di temperatura, la temperatura riduce fortemente le prestazioni DSC nonché il lifetime. Per capire gli effetti indotti da esposizione alla luce solare, abbiamo effettuato stress ottici accelerati per mezzo di un simulatore solare AM 1.5. Inoltre, abbiamo confrontato la cinetica di degradazione dei parametri DC misuratu durante gli stress ottici e termici. Il responsabile della degradazione durante lo stress termico o ottico è la formazione di difetti e di specie chimiche all’interfaccia tra il semiconduttore trasparente/dye/elettrolita i quali riducono la capacità di trasferimento di carica all'interfaccia e la migrazione degli ioni attraverso l’elettrolita. Durante gli stress ottici, abbiamo osservato una chiara differenza tra la cinetica di degradazione della tensione di circuito aperto e la cinetica di degradazione della corrente di corto circuito: quest'ultimo solitamente presenta una fase di inversione di tendenza durante gli stress ottici. La fase di inversione di tendenza è fortemente dipendente dalla intensità di illuminazione utilizzata durante lo stress accelerato: maggiore è il livello di illuminazione, minore è la durata della fase di inversione di tendenza. La degradazione della cella è più veloce con livelli di illuminazione più elevati probabilmente dovuta all'aumento della temperatura di interfaccia, come confermato anche dagli stress termici puri. L’elevato rapporto efficienza-peso consente alle DSC di poter essere utilizzate come fonte di energia in applicazioni spaziali. Per indagare gli effetti di fotoni ad alta energia (presenti anche a livello del suolo) sulle DSC, abbiamo effettuato stress accelerati utilizzando una fonte di illuminazione UV. Abbiamo progettato e assemblato un illuminatore a raggi UV, così come il circuito di pilotggio. Abbiamo scoperto che l'esposizione ai raggi UV ha effetti negativi su DSC e il principale responsabile della degradazione delle celle durante l'esposizione ai raggi UV è il bleaching dell'elettrolita (scolorimento dell’elettrolita). Vale la pena notare che il dye sembra avere un ruolo secondario nella degradazione della cella come è stato dimostrato. Per quanto riguarda le DSC studiate in questa tesi, si consiglia di adottare alcune soluzioni per evitare il bleaching dell’elettrolita. Il filtraggio UV e un buon incapsulamento potrebbero portare benefici per un funzionamento affidabile nel tempo, anche se potenzialmente vanno contro il peso contenuto e la naturale trasparenza delle DSC. Alta efficienza anche a basse intensità di illuminazione o con luce diffusa permette alle DSC di essere prese in considerazione per applicazioni indoor. Abbiamo effettuato ageing test tramite LED bianchi ad alta potenza e abbiamo confrontato la cinetica di degradazione dei parametri DC così come l’evoluzione dell’impedenza (EIS). Queste caratteristiche sono state misurate illuminando le celle sia con simulatore solare AM 1.5 che con un illuminatore a LED bianchi. Congiuntamente allo studio di affidabilità, abbiamo proposto un sistema di illuminazione basato su LED bianchi come un'alternativa economica e versatile ai costosi simulatori solari AM 1.5. Abbiamo progettato l'illuminatore basato su LED bianchi cosi come il suo circuito di pilotaggio. Dai risultati raccolti durente gli stress, abbiamo scoperto che l'esposizione alla luce bianca porta al degrado delle prestazioni delle DSC. Anche se lo spettro bianco non ha componente UV, le molecole del dye non sono più in grado di assorbire lunghezze d'onda nella regione UV. Confrontando le caratteristiche (DC ed EIS) misurate con il simulatore solare a LED bianchi e con il simulatore solare AM 1.5, abbiamo mostrato e provato che quest'ultimo fornisce più informazioni rispetto al primo. Dal punto di vista pannello solare, alcune DSC potrebbero incorrere in guasti o essere ombreggiate durante l'esposizione solare. Tale situazione potrebbe verificarsi nel caso in cui una cella/stringa di un pannello solare non sia funzionante oppure sia in ombra e non siano state adottate soluzioni atte a prevenirne una condizione operativa non convenzionale (ovvero non sono presenti diodi di by-pass o blocking diode). Per esaminare questa condizione reale non banale, abbiamo progettato e assemblato diversi driver di corrente e abbiamo eseguito molti constant current stress (CCS). I CCS eseguiti sono di due tipi: postive CCS e negative CCS. Il primo prevede di polarizzare la cella in modo tale che la corrente scorra nello verso che scorre quando esposta a luce solare, cioè in condizione standard di funzionamento; negative CCS, prevede di polarizzare la cella nel senso opposto al positive CCS. Durante gli stress le DSC vengono mantenute al buio, per evitare effetti dovuti all’illuminazione. Dai dati raccolti durante i due tipi di CCS, si è potuto envincere che entrambe portano ad una degradazione delle performance della cella e che all’aumentare del modulo della corrente di stress diminuisce il tempo di vita della DSC. Osservando le caratteristiche DC delle celle stressate, positive e negative CCS degradano le DSC in maniera diversa: i primi portano ad un degrado lento e costante della cella, i secondi, apparentemente non degradano le celle in maniera significativa all’inizio dello stress, ma ne causano un’improvvisa e rapida degradazione (sudden failure) dopo diverse ore. L’istante in cui si verifica il sudden failure della DSC è funzione dell’intensità della corrente di stress. Abbiamo mostrato che durante i positive CCS, la composizione elettrolita cambia, abbassando la dark current della cella solare, mentre i negative CCS portano alla degradazione del contro-elettrodo, accelerandone la corrosione da parte dell’elettrolita. Inoltre, abbiamo dimostrato che la maggior della degradazione avviene alle interfacce in cui gli elettroni sono emessi durante lo stress. I risultati ottenuti, dimostrano che i CCS hanno effetti irreversibili sulle prestazioni elettriche delle DSC e che alcune soluzioni circuitali devono essere adottate allo scopo di prevenire inoppurtune condizioni di funzionamento delle celle.

This thesis describes a comprehensive, simulation based scaling study – including device design, performance characterization, and the impact of statistical variability – on deca-nanometer bulk MOSFETs. After careful calibration of fabrication processes and electrical characteristics for n- and p-MOSFETs with 35 nm physical gate length, 1 nm EOT and stress engineering, the simulated devices closely match the performance of contemporary 45 nm CMOS technologies. Scaling to 25 nm, 18 nm and 13 nm gate length n and p devices follows generalized scaling rules, augmented by physically realistic constraints and the introduction of high-k/metal-gate stacks. The scaled devices attain the performance stipulated by the ITRS. Device a.c. performance is analyzed, at device and circuit level. Extrinsic parasitics become critical to nano-CMOS device performance. The thesis describes device capacitance components, analyzes the CMOS inverter, and obtains new insights into the inverter propagation delay in nano-CMOS. The projection of a.c. performance of scaled devices is obtained. The statistical variability of electrical characteristics, due to intrinsic parameter fluctuation sources, in contemporary and scaled decananometer MOSFETs is systematically investigated for the first time. The statistical variability sources: random discrete dopants, gate line edge roughness and poly-silicon granularity are simulated, in combination, in an ensemble of microscopically different devices. An increasing trend in the standard deviation of the threshold voltage as a function of scaling is observed. The introduction of high-k/metal gates improves electrostatic integrity and slows this trend. Statistical evaluations of variability in Ion and Ioff as a function of scaling are also performed. For the first time, the impact of strain on statistical variability is studied. Gate line edge roughness results in areas of local channel shortening, accompanied by locally increased strain, both effects increasing the local current. Variations are observed in both the drive current, and in the drive current enhancement normally expected from the application of strain. In addition, the effects of shallow trench isolation (STI) on MOSFET performance and on its statistical variability are investigated for the first time. The inverse-narrow-width effect of STI enhances the current density adjacent to it. This leads to a local enhancement of the influence of junction shapes adjacent to the STI. There is also a statistical impact on the threshold voltage due to random STI induced traps at the silicon/oxide interface.

GaN-based devices have emerged as a promising solution for power management applications. The intrinsic physical properties of the Gallium Nitride are exploited in order to considerably improve the efficiency and to reduce the volume of the next generation power switching converters. The wide energy gap allows to fabricate high voltage-rate devices with a reduced area consumption, whereas the high mobility guarantees a considerably low on-Resistance of the transistor. Moreover, thanks to the reduced parasitic capacitances, the operating frequency of the devices can be higher than conventional Silicon based transistors. In order to ensure a wide spreading of Gallium Nitride technology in the power transistors market, the price of the devices needs to be kept as low as possible. The costs of native substrates for the fabrication of GaN transistors are nowadays prohibitive, so that the epitaxial growth of Gallium Nitride on Silicon substrates has been developed. GaN-on-Silicon is the most suitable technology to fabricate GaN-based devices on a cheap and large area wafers (up to 200 mm), resulting in a significant reduction of the production costs. On the other hand, growing GaN on a foreign substrate results in high dislocation and defect densities which could affect the performance of the devices in terms of both losses and reliability issues. A so-called “buffer decomposition experiment” allowed to evaluate the role of the different layers which compose the vertical stack of a GaN-on-Silicon wafer by characterizing samples obtained by stopping the epitaxial growth at different stages of the process. It is demonstrated that both the thickness and the composition of the epitaxial stack, beside enhancing the breakdown voltage, improve the material quality by limiting the propagation of defects and dislocations. Moreover, a study on the reliability of the Aluminum Nitride layer grown on silicon is presented, showing that the AlN fails due to a wear-out process following a Weibull distribution. Furthermore, an extensive analysis on the reliability of the GaN-on-Silicon vertical stack is presented, as well as a systematic study on the failure statistic. It is shown that the time to failure of the GaN-on-Silicon stack is Weibull distributed, and, although it is weakly temperature-activated, it exponentially depends on the applied voltage. Moreover, the expected lifetime of the tested devices at the operating voltage is extracted. Aiming to further improve the performance of lateral High Electrons Mobility Transistors (HEMTs) in terms of vertical robustness and losses reduction, the impact of the resistivity of the silicon substrates has been evaluated. It is shown that highly resistive p-doped substrate results in a plateau region in the IV characteristic which considerably increases the vertical breakdown voltage of the devices. Nevertheless, the existence of a trade-off between the vertical robustness and the stability of the threshold voltage is demonstrated. A set of electrical characterization ascribes the threshold voltage shift to the positive backgating effect possibly related to the capacitive coupling of the partially depleted substrate which only occurs if lowly p-doped silicon is used. The origin of the plateau region is further investigated by means of a set of TCAD simulations, allowing to develop a two-diodes model which confirms the hypothesis on the substrate depletion. Even if stable and reliable lateral HEMTs are commercially available, their operating voltage is limited to ~ 900 V. In order to expand the applications field of the GaN-based devices to higher operating voltage, different device concepts have been developed so far. A promising solution is represented by (semi-)vertical trench gate devices, which are characterized by a thick drift layer where the OFF-state electric field spreads vertically in a bulky region, thus avoiding surface effects. Thanks to the vertical architecture, the OFF-state breakdown only depends on the thickness of the epitaxial stack, thus allowing to reach high breakdown voltages with a limited area consumption. Since the carriers must flow vertically, the gate of the devices lies in an etched trench, and it consists of a Metal Oxide Semiconductor (MOS) system. Within this thesis the gate leakage is deeply studied on devices with different gate dielectric, by means of electrical characterizations performed with different connection configurations and different bias polarities. Moreover, the gate capacitance is analytically calculated, and the experimental behavior observed for the Gate-Source and Gate-Drain capacitances over the applied voltage is discussed and modeled considering the GaN bias condition close to the dielectric interface. Lastly, a preliminary dielectric trap characterization is performed by evaluating the capacitance hysteresis induced by the electric field within different gate oxide materials. The last section of this work presents a custom setup developed for the characterization of the threshold voltage variations over the time. The stability of the threshold voltage is fundamental for allowing a device to operate properly in a switching converter. Standard pulsed systems used for the characterization of the threshold voltage allow to evaluate the impact of the bias level on the threshold variation, but no details on the time evolution can be obtained. The presented threshold transient setup monitors the threshold voltage variation over a wide time-interval, ranging from 10 µs to 100 s, allowing the analysis of the trapping and detrapping kinetics. Moreover, by monitoring the transient variation as a function of the temperature it is possible to full characterize (energy level and cross section) the traps involved in the observed instabilities.

HBT-based MMIC performance is very sensitive to the variation of core device characteristics and the reliability issues put the limit on its radio frequency (RF) behaviors. While many researchers have reported the observed stress-induced degradations of GaAs HBT characteristics, there has been little published data on the full understanding of stress impact on the GaAs HBT-based MMICs. If care is not taken to understand this issue, stress-induced degradation paths can lead to built-in circuit failure during regular operations. However, detection of this failure may be difficult due to the circuit complexity and lead to erroneous data or output conditions. Thus, a practical and analytical methodology has been developed to predict the stress impacts on HBT-based MMICs. It provides a quick way and guidance for the RF design engineer to evaluate the circuit performance with reliability considerations. Using the present existing EDA tools (Cadance SpectreRF and Agilent ADS) with the extracted pre- and post-stress transistor models, the electrothermal stress effects on InGaP/GaAs HBT-based RF building blocks including power amplifier (PA), low-noise amplifier (LNA) and oscillator have been systematically evaluated. This provides a potential way for the RF/microwave industry to save tens of millions of dollars annually in testing costs. The world now stands at the threshold of the age of advanced GaAs HBT MMIC technology and researchers have been exploring here for years. The reliability of GaAs HBT technology is no longer the post-design evaluation, but the pre-design consideration. The successful and fruitful results of this dissertation provide methods and guidance for the RF designers to achieve more reliable RF circuits with advanced GaAs HBT technology in the future.; Recent years have shown real advances of microwave monolithic integrated circuits (MMICs) for millimeter-wave frequency systems, such as wireless communication, advanced imaging, remote sensing and automotive radar systems, as MMICs can provide the size, weight and performance required for these systems. Traditionally, GaAs pseudomorphic high electron mobility transistor (pHEMT) or InP based MMIC technology has dominated in millimeter-wave frequency applications because of their high fsubscript T] and fsubscript max] as well as their superior noise performance. But these technologies are very expensive. Thus, for low cost and high performance applications, InGaP/GaAs heterojunction bipolar transistors (HBTs) are quickly becoming the preferred technology to be used due to their inherently excellent characteristics. These features, together with the need for only one power supply to bias the device, make InGaP/GaAs HBTs very attractive for the design of high performance fully integrated MMICs. With the smaller dimensions for improving speed and functionality of InGaP/GaAs HBTs, which dissipate large amount of power and result in heat flux accumulated in the device junction, technology reliability issues are the first concern for the commercialization. As the thermally triggered instabilities often seen in InGaP/GaAs HBTs, a carefully derived technique to define the stress conditions of accelerated life test has been employed in our study to acquire post-stress device characteristics for the projection of long-term device performance degradation pattern. To identify the possible origins of the post-stress device behaviors observed experimentally, a two dimensional (2-D) TCAD numerical device simulation has been carried out. Using this approach, it is suggested that the acceptor-type trapping states located in the emitter bulk are responsible for the commonly seen post-stress base current instability over the moderate base-emitter voltage region.
ID: 030423028; System requirements: World Wide Web browser and PDF reader.; Mode of access: World Wide Web.; Thesis (Ph.D.)--University of Central Florida, 2011.; Includes bibliographical references (p. 82-88).
Ph.D.
Doctorate
Electrical Engineering and Computer Science
Engineering and Computer Science

Recent trends to miniaturized systems such as smartphones and wearables, as well as the rise of autonomous vehicles relying on all-electric and smart in-car systems, have brought unprecedented needs for superior performance, functionality, and cost requirements. Transistor scaling alone cannot meet these metrics unless the remaining system components such as substrates and interconnections are scaled down to bridge the gap between transistor and system scaling. In this regard, 3D glass system packages have emerged as a promising alternative due to their ultra-short system interconnection lengths, higher component densities and system reliability enabled by the tailorable coefficient of thermal expansion (CTE), high dimensional stability and surface smoothness, outstanding electrical properties and low-cost panel-level processability of glass. The research objectives are to demonstrate board-level reliability of large, thin, glass packages directly mounted on PCB with conventional BGAs at pitches of 400µm SMT and smaller. Two key innovations are introduced to accomplish the objectives: a.) Reworkable circumferential polymer collars providing strain-relief at critical high stress concentration areas in the solder joints, b.) novel Mn-doped SACMTM solder to provide superior drop test performance without degrading thermomechanical reliability. Modeling, package and board design, fabrication and reliability characterization were carried out to demonstrate reliable board-level interconnections of large, ultra-thin glass packages. Finite-element modeling (FEM) was used to investigate the effectiveness of circumferential polymer collars as a strain-relief solution on fatigue performance. Experimental results with polymer collars indicated a 2X improvement in drop performance and 30% improvement in fatigue life. Failure analysis was performed using characterization techniques such as confocal surface acoustic microscopy (C-SAM), optical microscopy, X-ray imaging, and scanning electron microscopy/energy dispersive spectrometry (SEM/EDS). Model-to-experiment correlation was performed to validate the effectiveness of polymer collars as a strain-relief mechanism. Enhancement in board-level reliability performance with advances in solder materials based on Mn-doped SACMTM is demonstrated in the last part of the thesis.The studies, thus, demonstrate material, design and process innovations for package-to-board interconnection reliability with ultra-thin, large glass packages.

Ce travail a été dédié à l'étude expérimentale des mesures capacitives avec le microscope à force atomique (AFM) pour la caractérisation des profils des dopants dans des structures semiconductrices et pour la caractérisation des oxydes minces. La SCM est une méthode de caractérisation très utile pour les mesures de défaillance des profils des dopants, par exemple pour vérifier si des différentes étapes technologique s comme l'implantation des dopants dans des substrats semiconducteurs a été correctement effectuée. Nous avons démontré le potentiel de la SCM pour la caractérisation des profils des dopants en utilisant des échantillons de test qui couvrent à peu prés toutes les structures semiconductrices rencontrées dans l'industrie de la microélectronique: des profils des dopants, de type escalier, des puits quantiques, des jonctions p-n. Des images qualitatives ont été obtenues sur des échantillons contenant des profils des dopants des concentrations entre 2. E+15 at. Cm-3 et 5. E+19cm-3. Nous avons montré que la SCM est capable de détecter des puits quantiques avec une épaisseur d'environ 7 nm. La SCM est capable de faire la différence entre les dopants de type n et les dopants de type p. Tous ces résultats confirment l'utilité de la SCM comme méthode de caractérisation qualitative des profils des dopants à nano-échelle. Nous avons aussi étudié les paramètres expérimentaux qui jouent un rôle dans l'interprétation et la reproductibilité du signal capacitif: la lumière laser parasite provenant du système de détection de l'AFM, des couplage capacitifs parasites, les problèmes de contact entre la sonde AFM et l'échantillon, l'influence des champs électriques forts générés par la sonde AFM, la topographie des échantillons, la qualité et les propriétés de l'oxyde de grille. Nous avons proposé des solutions pour l'élimination de tous ces facteurs parasites et pour l'avancement de la SCM vers des mesures reproductibles et quantifiables
This work was devoted to the experimental study of the scanning capacitance microscopy (SCM) and spectroscopy (SCS) for the mapping of the dopants in the semiconductor structures and for the characterization of thin oxides. SCM has appeared to be a very powerful technique for doping mapping as long as qualitative images are needed, for example in order to check whether fabrication steps like implantations have been correctly operated during the fabrication of devices (presence or absence of doping of a given type in a region where it should be present). When quantitativity is needed, the only way of performing a calibration of SCM images for dopant mapping seems to grow exactly the same oxide on two different samples, one being a calibration sample from which a semi-calibration curve associating doping levels and SCM signal levels will be measured and applied to the unknown sample (semi-calibration). We have shown the capabilities of SCM for dopant mapping using a series of experimental situations and test samples covering almost all frequently encountered structures in the industry of silicon microelectronics : doping staircases of p-type and n-type structures, quantum wells and p-n junctions. Qualitative images have been obtained for a wide range of doping levels between 2. E+15 at. Cm-3 to 5. E+19 at. Cm-3. SCM is able to detect quantum wells of ~ 7 nm width. SCM is also able to differentiate between dopants of different type (p-type or n-type). All these results confirm the usefulness of SCM as a qualitative imaging technique. We have studied the experimental parameters playing a role in the interpretation and reproducibility of SCM signal: stray light, stray capacitance, the tip-sample contact, the influence of strong electrical fields, the sample’s topography, the quality and the properties of the top oxide. We have proposed solutions for eliminating all these parasitic factors and for rendering the SCM measurements reproducible and quantitative

This thesis reports the results of the three-year research activity on Light Emitting Diodes (LEDs) for Solid State Lighting. In particular, the research project was focused on the study of thermal characterization of Gallium Nitride (GaN) based LEDs, and the impact of the temperature on the reliability of devices. The work starts from an overview of the State of the art of III-V optoelectronic devices and on reliability aspects of such devices. Afterwards, different characterization methods for thermal characterization of LEDs are presented and discussed with the description of some experimental implementations designed. In the remaining chapters three reliability approaches on different LED structures are presented: (i) an Accelerated Lifetime Testing (ALT) on low-flux Phosphors Converted LEDs, (ii) an ALT on High Brightness LEDs with Chip-on-Board technology, and (iii) a reliability analysis on Deep UV AlGaN-LEDs. In all case studies, the thermal aspects have been stressed in the analysis of the results. The different activities started from an in-depth knowledge of the device structure and the related issues, and aimed at (i) extrapolating the degradation model that can provide an accurate lifetime estimation, (ii) investigating on physical mechanisms responsible for degradation, (iii) finding a correlation between thermal behaviour and reliability. The present work permitted to collect new results concerning the mechanisms that still limit the reliability of LEDs, and will provide the experimental and analytical tools suitable for ALT design and implementation.
Con il presente lavoro di tesi vengono riportati i risultati dell'attività di ricerca triennale su Light Emitting Diode (LED) per illuminazione allo stato solido. In particolare, il progetto di ricerca è stato incentrato sullo studio della caratterizzazione termica di LED in nitruro di gallio (GaN) e sull'impatto della temperatura sull'affidabilità dei dispositivi. Il lavoro comincia da una panoramica sullo stato dell'arte di dispositivi optoelettronici a semiconduttore composito di tipo III-V e sugli aspetti affidabilistici ad essi legati. In seguito vengono presentati diversi metodi per la caratterizzazione termica dei LED, insieme alla descrizione dettagliata delle diverse implementazioni sperimentali per ottenere tali misure. Nei capitoli restanti vengono presentati e discussi tre diversi approcci di analisi affidabilistica: (i) un test di vita accelerato su LED bianchi a basso flusso luminoso, (ii) un test di vita accelerato su LED ad alto flusso con tecnologia Chip On Board, e (iii) un'analisi affidabilistica di LED in AlGaN con emissione nel profondo ultravioletto. In tutti questi studi, sono stati sottolineati gli aspetti termici nell'analisi dei risultati. Queste analisi partono da un'approfondita conoscenza della struttura dei dispositivi e delle problematiche relative, con l'obiettivo di (i) trovare un modello di degrado in grado di fornire una corretta stima del tempo di vita, (ii) indagare i meccanismi fisici alla base del degrado, e (iii) individuate una correlazione tra le proprietà termiche e l'affidabilità del dispositivo. Il lavoro presentato ha permesso di mettere insieme nuovi risultati relativi ai meccanismi che attualmente limitano l'affidabilità dei LED, e ha reso disponibile diversi strumenti sperimentali e analitici utili per la progettazione e l'implementazione di test di vita accelerati futuri.

Les phénomènes de chargement des diélectriques constituent l'un des principaux mécanismes de défaillance des microsystèmes à actionnement électrostatique, ce qui limite la commercialisation de ce type de dispositifs. Par exemple, dans le cas de micro-commutateurs capacitifs ce chargement entraîne des problèmes de collage entre la membrane actionnable et la surface du diélectrique qui recouvre l'électrode d'actionnement. Malgré de nombreux travaux réalisés dans le monde, les phénomènes de chargement des diélectriques sont encore mal compris aujourd'hui et les mécanismes de défaillances associés peu explicités. Par ailleurs de nombreuses méthodes de caractérisation ont été développées afin d'étudier ces phénomènes : capacité/tension dans les micro-commutateurs capacitifs, courant/tension dans les capacités MIM (Métal-Isolant-Métal). Bien que très souvent utilisées, ces méthodes donnent des résultats qui dépendent fortement de la nature du dispositif utilisé. Dans les capacités MIM par exemple, la décharge a lieu en situation de court-circuit et les charges injectées dans le diélectrique sont collectées seulement par l'électrode qui a servi à réaliser l'injection. Cette configuration est l'inverse de celle qui a lieu réellement dans les microsystèmes pour lesquels les charges sont injectées par la membrane actionnable et collectées par l'électrode d'actionnement, puisque la membrane ne touche pas le diélectrique lorsque la tension est supprimée. Par ailleurs les mécanismes de défaillances sont souvent liées à des phénomènes multi-physiques (électrique, mécanique, thermique). Ainsi le chargement des diélectriques peut être couplé notamment à des problèmes de fatigue mécanique de la membrane, ce qui peut fausser les interprétations. Des études récentes ont par ailleurs montré que les phénomènes tribologiques, comme l'adhésion et la friction, sont cruciaux pour les MEMS/NEMS et peuvent affecter radicalement leurs performances. Les micro-commutateurs RF étant basés sur le contact intermittent entre deux surfaces (membrane métallique et diélectrique), la fiabilité des ces composants est également impactée par ces phénomènes de surface. Des études sur la micro-nanotribologie appliquée aux micro-commutateurs RF sont donc nécessaires pour comprendre les phénomènes qui se passent aux interfaces et pour coupler ces phénomènes avec le chargement des diélectriques. Les travaux sur le chargement des diélectriques présentés dans ce mémoire sont basés sur la microscopie à force atomique (KPFM, FDC) et permettent de supprimer les inconvénients des méthodes conventionnelles. Le diélectrique étudié est le nitrure de silicium obtenu par PECVD pour des micro-commutateurs RF à contact capacitif. Les méthodes utilisées permettent de réaliser l'étude des diélectriques à l'échelle nanométrique grâce à l'utilisation de l'AFM dont la dimension de la pointe est comparable aux aspérités des microstructures. Différentes structures de tests ont été caractérisées incluant des films diélectriques, des capacités MIM et des micro-commutateurs. La pointe de l'AFM est utilisée pour réaliser l'injection des charges (comme dans le cas d'une aspérité en contact avec le diélectrique), mais également pour mesurer le potentiel de surface et la force d'adhésion. Les résultats obtenus ont été comparés à des mesures de charges et décharges plus conventionnelles sur des capacités MIM et sur des micro-commutateurs RF. Tous ces résultats ont également été comparés à des données de la littérature provenant de différents composants. L'influence de plusieurs paramètres clés sur le chargement des diélectriques a également a également été étudiée. Différentes épaisseurs de SiNx déposées sur de l'or (évaporé et électro-déposé), sur du Titane et sur du silicium ont été analysées. Différents modes d'élaboration du SiNx PECVD ont été utilisés en changeant le ratio des gaz, la température de dépôt, la puissance et la fréquence RF. Des analyses physico-chimiques ont également été menées pour déterminer les liaisons chimiques et les compositions des films de SiNx (FTIR, XPS). Ces données ont été utilisées pour expliquer les résultats électriques obtenus. Différentes conditions de chargement ont également été explorées : amplitude, durée et polarité de la tension, taux d'humidité, contamination dues aux hydro-carbones. Les différents phénomènes tribologiques (adhésion, friction) ont aussi été étudiés à l'échelle nanométrique sous différentes tensions et pour différents taux d'humidité. A partir de ces études, deux principaux mécanismes de collage dans les microsystèmes à actionnement électrostatique ont ainsi été explicités : le chargement des diélectriques et la formation d'un ménisque d'eau. L'interaction entre ces deux mécanismes a également été mise en évidence et a permis de mieux comprendre les phénomènes de collage dans les MEMS à actionnement électrostatique
The reliability of electrostatically actuated micro- and nano-electromechanical systems (MEMS and NEMS) is determined by several failure modes which originate from different failure mechanisms. Among various reliability concerns, the dielectric charging constitutes major failure mechanism which inhibits the commercialization of several electrostatic MEMS devices. In electrostatic capacitive MEMS switches, for example, the charging phenomenon results in shifting the electrical characteristics and leads to stiction causing the device failure. In spite of the extensive study done on this topic, a comprehensive understanding of the charging phenomenon and its relevant failure mechanisms are still missing. The characterization techniques employed to investigate this problem, though useful, have serious limitations in addition to the missing correlation between their results. On the other hand, recent studies show that tribological phenomena such as adhesion and friction are crucial in MEMS/NEMS devices requiring relative motion and could affect their performance. Since the operation of MEMS switch is based on intermittent contact between two surfaces, the movable electrode and the dielectric, critical tribological concerns may also occur at the interface and influence the device reliability. These concerns have not been investigated before, and consequently, micro/nanotribological studies are needed to develop a fundamental understanding of these interfacial phenomena. Also, the multiphysics coupling between the charging phenomena and those expected tribological effects needs to be studied. This thesis addresses the abovementioned weaknesses and presents numerous novel characterization techniques to study the charging phenomenon based on Kelvin probe force microscopy (KPFM) and, for the first time, force-distance curve (FDC) measurements. These methods were used to study plasma-enhanced chemical vapor deposition (PECVD) silicon nitride films for application in electrostatic capacitive MEMS switches. The proposed methods are performed on the nanoscale and take the advantage of the atomic force microscope (AFM) tip to simulate a single asperity contact between the switch movable electrode and the dielectric surface. Different device structures were characterized including bare dielectric films, MIM capacitors, and MEMS switches. In addition, the charge/discharge current transients (C/DCT) and thermally stimulated depolarization current (TSDC) assessment methods were used to study the charging/discharging processes in metal-insulator-metal (MIM) capacitors. A comparison and correlation between the results from the investigated characterization techniques were performed. Moreover, a correlation between the obtained nanoscale/macroscale results and the literature reported data obtained from device level measurements of actual MEMS devices was made. The influence of several key parameters on the charging/discharging processes was investigated. This includes the impact of the dielectric film thickness, dielectric deposition conditions, and substrate. SiNx films with different thicknesses were deposited over metal layers and over silicon substrates to study the effect of the dielectric thickness. The impact of the dielectric deposition conditions was investigated through depositing SiNx films using different gas ratio, temperature, power, and RF modes. To study the influence of the substrate, SiNx layers were deposited on evaporated gold, electrochemically-deposited gold, evaporated titanium layers, and over bare silicon substrates. Fourier transform infra-red spectroscopy (FT-IR) and X-ray photoelectron spectroscopy (XPS) material characterization techniques were used to determine the chemical bonds and compositions, respectively, of the investigated SiNx films. The obtained data from these techniques were used to explain the electrical characterization results. The impact of electrical charge injection conditions, which are the voltage amplitude, polarity and duration, was also explored. Finally, the influence of the relative humidity, environment medium, and contaminants on the charging phenomenon was studied. Furthermore, the thesis investigates different tribological phenomena at the interface between the two contacting surfaces of electrostatic MEMS switches as well as their multiphysics coupling with the dielectric charging failure mechanism. The adhesive and friction forces were measured on the nanoscale under different electrical stress conditions and relative humidity levels using an AFM to study different stiction mechanisms. In these devices, stiction can be caused by two main mechanisms: dielectric charging and meniscus formation resulting from the adsorbed water layer at the interface. The effect of each mechanism as well as their multiphysics interaction and impact on the overall adhesion or stiction was quantified. Finally, the impact of the dielectric charging on the friction force between the two contacting surfaces of the switch has been studied

In this thesis a extensive study of devices based on AlGaN/GaN heterostructure is reported. The work is fundamentally divided in two main topic: the first part is related to the investigation of traps and defects and their effects on the device performances; the second part is instead related to the reliability studies of this type of devices. The investigation of trapping effects is based on pulsed measurements of output characteristic and transcharacteristic of the device under test. The measurements carried out on High Electron Mobility Transistors (HEMT) with different gate materials (Ni/Au/Ni or ITO) and absence or presence of the surface passivation layer have shown how this technique can be used as a rapid and effective method to distinguish between the trapping phenomena occurring in the region under the gate and those occurring in the gate - drain access region. In particular we have seen that unpassivated devices have a transconductance peak dispersion, which can be ascribed to the presence of surface traps (absent in passivated devices). On the other hand the presence of a threshold voltage shift (found in the ITO samples) is related to traps below the gate electrode. The presence of traps under the ITO contact has been confirmed by low frequency capacitance - voltage measurements. Also the pulsed measurements have been correlated to electroluminescence characterization of the transistor showing the role of traps in limiting the maximum gate-drain electric field and, consequently, the intensity of the emitted light, related to the equivalent electron temperature. The combined dynamic IV - electroluminescence measurement technique has been also used in the analysis of state of the art GaN-HEMTs on Silicon substrate. The measurements carried on samples with different gate recess width and same gate length show better performances (in terms of frequency dispersion and gate - drain electric field) for transistors with shorter recess width. The analysis of defects in GaN-based devices has been carried out also by means of low frequency noise measurements. The purpose of the work on noise was to find a correlation between the intensity of the measured noise and the performances of the device (in particular the breakdown). Several devices have been tested (transistors and transmission line model - TLM) with different realization technology (aluminum content, ohmic contact annealing temperature, composition of ohmic contact electrode). A real correlation between noise in the conductive channel and breakdown has not been found; while measurements on the TLM show a possible relation between ohmic contact specific resistance and noise. The reliability of several samples has been investigated by means of both long-term stress (1000 h DC life-test) and short-term stress (2 min step-stress). The long - term stress has been carried out on AlGaN/GaN HEMTs processed on composite SopSiC substrate developed within the European HYPHEN project. These substrates have been realized through the transfer of a thin single crystal silicon layer on the top of a thick polycrystalline silicon carbide wafer. The aim of this project is to provide a valid and less expensive substrate for GaN - based devices in respect to the traditional bulk-SiC substrates. Three stress conditions (different DC biases and different ambient temperatures) have been selected for the test. The results at the end of the stress present good device stability and promising performance; reliability issues found in few samples are linked to the high levels of gate leakage current reached during the stress. This proves that devices failure can be ascribed to the technology used for the realization of transistors and does not appear correlated to the nature of the composite substrate. With concern the short-term stress, we have studied the influence of gate reverse bias test on the overall behavior of the transistor. This type of accelerated test usually brings to the definition of a critical voltage beyond that the gate leakage current increases drastically up to the failure of the device. In literature the phenomenon is called inverse piezoelectric effect and it is considered related to the lattice strain occurring during the stress. Our study was based on a split wafer experiment adopting passivated AlGaN/GaN HEMTs with different gate metallizations: Ni/Au/Ni, ITO, Ni/ITO. The results obtained suggest that the critical voltage is not related only to the piezoelectric strain, but also the initial gate leakage current of the fresh device plays a role in the degradation process. Moreover the dynamic of the degradation during the test seems to indicate that the ageing process can be ascribe to a defect percolation process in the AlGaN barrier layer
L'argomento esposto in questa tesi riguarda uno studio approfondito di dispositivi su eterostruttura AlGaN/GaN. Questo lavoro puo’ essere suddiviso in due argomenti principali: la prima parte riguarda lo studio di trappole e difetti e il loro effetto sulle prestazioni del dispositivo; la seconda parte e’ invece dedicata allo studio dell'affidabilita’ di questo tipo di dispositivi. L'analisi degli effetti trappola e’ basata sulla misurazione impulsata della caratteristica di uscita e della transconduttanza del dispositivo in esame. Le misure eseguite su transistor con diversa composizione dell'elettrodo di gate (Ni/Au/Ni o ITO) e presenza o assenza dello strato di passivazione hanno mostrato come questa tecnica puo’ essere utilizzata come rapido e valido sistema per distinguere tra gli effetti di trappole presenti nella regione sottostante il gate e quelli di trappole nella regione di accesso gate - drain. In dettaglio si e’ visto che dispositivi non passivati presentano una diminuzione del picco della transconduttanza, fenomeno riconducibile alla presenza di trappole superficiali; mentre nel caso di variazione della tensione di soglia (dispositivi con elettrodo di gate in ITO) le trappole sono localizzate nella regione al di sotto del contatto di gate. La presenza di trappole sotto il contatto in ITO e’ stata inoltre confermata da misure di capacita’ vs. tensione a bassa frequenza. Le misure impulsate sono state poi messe in relazione con le misure di elettroluminescenza effettuate sui transistor: questo confronto ha mostrato come le trappole presenti nel dispositivo limitino il massimo campo elettrico tra gate e drain e quindi l'intensita’ della radiazione emessa. Questa metodologia e’ stata poi applicata per l'analisi di dispositivi GaN su silicio caratterizzati da identica lunghezza del contatto di gate ma diversa ampiezza del recesso di gate. Dai risultati ottenuti si puo’ vedere che le prestazioni migliori, in termini di dispersione in frequenza e massimo campo elettrico, si hanno nei dispositivi con recesso piu’ piccolo. L'analisi dei difetti presenti nei dispositivi su GaN e’ stata effettuata anche per mezzo di misure di rumore a bassa frequenza. Lo scopo di questa parte di attivita’ era di trovare una correlazione tra il livello di rumore misurato e le caratteristiche elettriche del dispositivo (in particolare il breakdown). Diversi dispositivi sono stati testati (transistor e transmission line model - TLM) con differenti tecnologie di realizzazione (percentuale di alluminio, temperatura di processo, composizione dell'elettrodo dei contatti ohmici). Una correlazione rumore del canale conduttivo e breakdown non e’ stata trovata; mentre le misure sulle TLM hanno mostrato un possibile legame tra rumore e resistenza specifica del contatto ohmico. L'affidabilita’ dei dispositivi è stata studiata per mezzo di prove di stress a breve (2 min step - stress) e lungo termine (1000 hour). Lo stress a lungo termine e’ stato eseguito su dispositivi AlGaN/GaN processati su substrato composito di tipo SopSiC sviluppato nell'ambito del progetto europeo HYPHEN. Questi substrati sono realizzati tramite il trasferimento di un sottile strato di Silicio monocristallino su uno strato piu’ spesso di Carburo di Silicio policristallino, il loro scopo e’ di rappresentare una valida ed economica alternativa ai substrati in Carburo di Silicio monocristallino. Per questo esperimento sono state individuate tre condizioni a differente polarizzazione e temperatura; i risultati finali presentano una buona stabilita’ dei dispositivi ed inoltre mostrano come i problemi riscontrati durante il test siano riconducibili agli elevati livelli di corrente di perdita del gate. Il degrado dei dispositivi e’ quindi strettamente legato alla tecnologia del processo utilizzato per la realizzazione del transistor e non e’ legata alla natura del substrato. Per quanto riguarda la prova di stress accelerato, si e’ studiato l'effetto sulle prestazioni del dispositivo di elevate tensioni negative applicate al contatto di gate. Questo tipo di test solitamente porta all'individuazione di una tensione critica oltre la quale si verifica un brusco aumento della corrente di gate. Nella letteratura scientifica questo fenomeno e’ indicato come effetto piezoelettrico inverso (inverse piezoelectric effect) ed e’ associato alla creazione di difetti nel reticolo cristallino sottoposto a sollecitazione durante lo stress. Lo studio si e’ basato su un wafer con differenti metallizzazioni di gate (Ni/Au/Ni, ITO, Ni/ITO) e con passivazione dei dispositivi. I risultati ottenuti suggeriscono che la tensione critica non sia legata solo alla tensione che si induce nel reticolo; infatti anche il livello iniziale della corrente di perdita del gate sembra giocare un ruolo nel processo di degradazione. Inoltre l'evoluzione del degrado durante il test sembra indicare che il processo di invecchiamento avvenga per filtrazione dei difetti all'interno della barriera di AlGaN (percolation process)

La motivation de cette thèse est deux des principaux problèmes soulevés par la mise à l'échelle des appareils de la nouvelle ère dans la conception MOSFET contemporaine: le développement d'un modèle de courant de drain analytique et compact, valable dans toutes les régions d'opération, décrivant précisément les caractéristiques Id-Vg et Id-Vd des dispositifs FDSOI à canaux courts et l'étude des problèmes de fiabilité et de variabilité de ces transistors évolués à l'échelle nanométrique. Le chapitre II fournit une base théorique et technique pour une meilleure compréhension de cette thèse, en mettant l'accent sur les paramètres électriques MOSFET critiques et les techniques d'extraction. Il démontre les méthodologies de Y-Function et de Split-CV pour la caractérisation électrique dans divers types de semiconducteurs. L'influence du niveau de l'oscillateur du signal AC sur la mesure de la mobilité efficace par la technique Split-CV dans MOSFET est également analysée. Une nouvelle méthodologie basée sur la fonction Lambert W qui permet d'extraire les paramètres MOSFET sur la gamme de tension de grille complète, permettant de décrire la transition entre les regions en dessous et au dessus du seuil, malgré la réduction de la tension d'alimentation. Enfin, certains éléments de base concernant le bruit à basse fréquence (LFN) sur la caractérisation MOSFET sont décrits. Le chapitre III présente la modélisation analytique et compacte du courant de drain dans les MOSFET FDSOI à l'échelle nanométrique. Des modèles analytiques simples pour les tensions de seuil de la grille avant et arrière et les facteurs d'idéalité ont été développés en termes de paramètres de géométrie du dispositif et de tensions de polarisation appliquées avec contrôle de la grille arrière. Un modèle analytique et compact de courant de drain a été développé pour les MOSFET FDSOI UTBB légèrement dopés avec contrôle de la grille arrière, prenant en compte la géométrie réduite et d'autres effets importants dans ces technologies et implémenté en Verilog-A pour la simulation des circuits dans Cadence Spectre. Le chapitre IV traite des problèmes de fiabilité dans les transistors FDSOI. La dégradation par des porteurs chauds des nMOSFET UTBB FDSOI decananométrique a été étudiée dans différentes conditions de stress de drain et de grille. Les mécanismes de dégradation ont été identifiés grâce à des mesures LFN à température ambiante dans les domaines de la fréquence et du temps. Un modèle de vieillissement HC est proposé permettant de prédire la dégradation du dispositif stressé dans différentes conditions de polarisation, en utilisant de paramètres uniques déterminés pour chaque technologie extraits par des mesures. Enfin, les caractéristiques de stress NBTI et le comportement de relaxation après stress sous la polarisation positive des pMOSFET UTBB FDSOI de grille HfSiON ont été étudiés. Un modèle pour le NBTI a été développé en considérant les mécanismes de piégeage/dépiégeage des trous, en fonction de la température et de la tension de polarisation. Le chapitre V présente des études sur les problèmes de variabilité dans les dispositifs décananométriques. Les principales sources de courant de drain et de grille de la variabilité locale ont été étudiées. Dans cet aspect, un modèle de courant de drain de la variabilité locale, valable pour toute condition de polarisation de grille et de drain, a été développé. Les principaux paramètres MOSFET de variabilité locale et globale ont été extraits par ce modèle pour différentes technologies CMOS (Bulk 28nm, FDSOI 14nm, Si bulk FinFET 14nm, nanofils Si/SiGe sous 15nm). L’impact de la variabilité du courant de drain sur les circuits de Cadence Spectre est présenté. Un résumé de cette thèse est présenté au chapitre VI, qui souligne les principales contributions à la recherche et les orientations de recherche futures sont suggérées
Τhe motivation for this dissertation is two of the main issues brought up by the scaling of new-era devices in contemporary MOSFET design: the development of an analytical and compact drain current model, valid in all regions of operation describing accurately the transfer and output characteristics of short-channel FDSOI devices and the investigation of reliability and variability issues of such advanced nanoscale transistors. Chapter II provides a theoretical and technical background for the better understanding of this dissertation, focusing on the critical MOSFET electrical parameters and the techniques for their extraction. It demonstrates the so-called Y-Function and Split-CV methodologies for electrical characterization in diverse types of semiconductors. The influence of AC signal oscillator level on effective mobility measurement by split C-V technique in MOSFETs is also analyzed. A new methodology based on the Lambert W function which allows the extraction of MOSFET parameters over the full gate voltage range, enabling to fully capture the transition between subthreshold and above threshold region, despite the reduction of supply voltage Vdd is presented. Finally, some basic elements concerning the low frequency noise (LFN) on MOSFETs characterization are described. Chapter III presents the analytical drain current compact modeling in nanoscale FDSOI MOSFETs. Simple analytical models for the front and back gate threshold voltages and ideality factors have been derived in terms of the device geometry parameters and the applied bias voltages with back gate control. An analytical compact drain current model has been developed for lightly doped UTBB FDSOI MOSFETs with back gate control, accounting for small geometry and other significant in such technologies effects and implemented via Verilog-A code for simulation of circuits in Cadence Spectre. Chapter IV is dealing with reliability issues in FDSOI transistors. The hot-carrier degradation of nanoscale UTBB FDSOI nMOSFETs has been investigated under different drain and gate bias stress conditions. The degradation mechanisms have been identified by combined LFN measurements at room temperature in the frequency and time domains. Based on our analytical compact model of Chapter III, an HC aging model is proposed enabling to predict the device degradation stressed under different bias conditions, using a unique set of few model parameters determined for each technology through measurements. Finally, the NBTI stress characteristics and the recovery behavior under positive bias temperature stress of HfSiON gate dielectric UTBB FDSOI pMOSFETs have been investigated. A model for the NBTI has been developed by considering hole-trapping/detrapping mechanisms, capturing the temperature and bias voltage dependence. In Chapter V studies of variability issues in advanced nano-scale devices are presented. The main sources of drain and gate current local variability have been thoroughly studied. In this aspect, a fully functional drain current mismatch model, valid for any gate and drain bias condition has been developed. The main local and global variability MOSFET parameters have been extracted owing to this generalized analytical mismatch model. Furthermore, the impact of the source-drain series resistance mismatch on the drain current variability has been investigated for 28nm Bulk MOSFETs. A detailed statistical characterization of the drain current local and global variability in sub 15nm Si/SiGe Trigate nanowire pMOSFETs and 14nm Si bulk FinFETs has been conducted. Finally, a complete investigation of the gate and drain current mismatch in advanced FDSOI devices has been performed. Finally, the impact of drain current variability on circuits in Cadence Spectre is presented. An overall summary of this dissertation is presented in Chapter VI, which highlights the key research contributions and future research directions are suggested

Dans les technologies CMOS avancées, les défauts microscopiques localisées à l'interface Si (Nit) ou dans l'oxyde de grille (Nox) dégradent les performances des transistors CMOS, en augmentant le bruit de basse fréquence (LFN). Ces défauts sont généralement induits par le processus de fabrication ou par le vieillissement de l'appareil sous tension électrique (BTI, porteurs chauds). Dans des transistors canal SiGe ou III-V, leur densité est beaucoup plus élevé que dans le silicium et leur nature microscopique est encore inconnue. En outre, en sub 10 nm 3D comme nanofils, ces défauts répartis spatialement induisent des effets stochastiques typiques responsables de la "variabilité temporelle" de la performance de l'appareil. Cette nouvelle composante dynamique de la variabilité doit maintenant être envisagée en plus de la variabilité statique bien connu pour obtenir circuits fonctionnels et fiables. Aujourd'hui donc, il devient essentiel de bien comprendre les mécanismes de piégeage induites par ces défauts afin de concevoir et fabriquer des technologies CMOS robustes et fiables pour les nœuds de sub 10 nm
In advanced CMOS technologies, microscopic defects localized at the Si interface (Nit) or within the gate oxide (Nox) degrade the performance of CMOS transistors, by increasing the low frequency noise (LFN). These defects are generally induced by the fabrication process or by the ageing of the device under electrical stress (BTI, Hot Carriers). In SiGe or III-V channel transistors, their density is much higher than in silicon and their microscopic nature still is unknown. In addition, in sub 10nm 3D like nanowires, these spatially distributed defects induce typical stochastic effects responsible for “temporal variability” of the device performance. This new dynamic variability component must now be considered in addition of the well-known static variability to obtain functional and reliable circuits. Therefore today it becomes essential to well understand the trapping mechanisms induced by these defects in order to design & fabricate robust and reliable CMOS technologies for sub 10nm nodes

Le Nitrure de Gallium est devenu un matériau incontournable pour le développement de dispositifs semi-conducteurs aux performances très supérieures aux composants silicium. L'immense potentiel du dispositif HEMT AlGaN / GaN provient du gaz d'électrons à haute densité et à forte mobilité formé au niveau de son hétéro-structure. Cependant, le fonctionnement sous champ électrique, température et conditions de stress élevés rend le dispositif vulnérable aux problèmes de fiabilité qui limitent son efficacité et sa durée de vie. Les pièges présents dans la structure, qui limitent la densité porteurs du canal et pénalisent la réponse du dispositif, constituent le facteur majeur déterminant plusieurs effets électriques parasites et la fiabilité du dispositif. L’industrie du GaN est confrontée à la nécessité de disposer de dispositifs de haute fiabilité si bien qu’il est nécessaire de faire des progrès dans l’analyse de l’impact des pièges pour en déduire des solutions technologiques permettant leur inhibition.La motivation de ce travail est d’identifier les signatures électriques associées à l’activité de différents pièges ainsi que leurs conséquences sur les performances et la fiabilité des HEMT GaN grâce à une étude dédiée des dispositifs de la technologie GH-25 conçue pour des applications RF de puissance fonctionnant jusqu’à 20 GHz. L’étude utilise des simulations physiques TCAD. Une analyse détaillée des effets indépendants et interdépendants est réalisée afin d'identifier l'impact relatif des pièges pour des études de cas où les caractéristiques électriques présentent des écarts importants par rapport à la réponse idéale du dispositif.La méthodologie utilisée pour développer un modèle TCAD représentatif et dérivé de la physique interne est décrite en accordant une attention particulière au courant de fuite de grille qui reflète l'influence de processus physiques fondamentaux ainsi que les effets parasites couramment rencontrés dans les dispositifs GaN. Les simulations ciblées établissent un lien entre l'observation d'un problème de fiabilité et son origine sous-jacente dans les phénomènes de piégeage.L’établissement d’associations entre la localisation spatiale des pièges et les dégradations qu’ils pourraient provoquer est un objectif important de cette thèse.Plusieurs stratégies de simulation sont présentées, permettant d’explorer le comportement des pièges en régime permanent et en régime transitoire et donnant une perception détaillée de la manière dont les paramètres des pièges affectent les caractéristiques opérationnelles. Des approches pour distinguer les interactions de pièges différents sont également décrites. L’étude centrale de cette thèse est un phénomène de courant de fuite parasite complexe, identifié dans le procédé GH 25comme conséquence du vieillissement accéléré. Connu sous le nom de «belly-shape», il représente un exemple intéressant de la façon dont les stratégies développées peuvent être appliquées pour discerner la causalité, l'impact et l'évolution des pièges responsables du phénomène. Afin d'approfondir l'analyse des modes de piégeage, nous avons procédé à des tests de vieillissement accéléré et des caractérisations électro-optiques afin de modifier la dynamique générale du mécanisme de piégeage et d'observer la modulation du mécanisme du piégeage sur la réponse du dispositif
Gallium Nitride has emerged as a terrific contender to lead the future of the semiconductor industry beyond the performance limits of silicon.The immense potential of the AlGaN/GaN HEMT device is derived from the high density, high mobility electron gas formed at its hetero-structure. However, frequent subjection to high electric field, temperature and stress conditions makes the device vulnerable to reliability issues that restrict its efficiency and life time. A dominant contributor to several parasitic and reliability issues are traps present within the semiconductor structure which restrict the channel density and aggravate the device static and dynamic response. As the GaN industry addresses an increasing demand for superior devices, reliability analysis is of critical importance. There is a necessity to enable advancements in trap inhibition which would allow the realization of stronger, efficient devices.The motivation of this work is to recognize distinct ways in which various traps affect the performance and reliability metrics of GaN 0.25 µm HEMTs through a study of devices of the GH-25 process optimized for high power applications up to 20 GHz. The investigation employs physical TCAD simulations to provide insight and perspective to electrical and optical characterizations. Detailed analysis into independent and interrelated effects is performed to identify the relative impact of traps in circumstances presenting notable deviations from the ideal device response.The methodology to develop a representative TCAD model derived closely from internal physics is described with special focus on the sensitive gate leakage characteristic which reflects the influence of fundamental physical processes as well as parasitic effects commonly encountered in GaN HEMTs. Targeted simulations provide a pivotal link between the observation of a reliability issue and its underlying origin in trapping phenomena. Establishing associations between the spatial location of traps and the degradations they could trigger is an important objective of this thesis.Several simulation strategies that explore trapping behavior in various steady state and transient environments are discussed which allow detailed perception into the manner and extent to which trap attributes affect operational considerations. Approaches to distinguish disparate trap interactions are also described. The central case study in this thesis is an abstruse parasitic leakage phenomenon, identified in the GH 25 process as a consequence of aging stress. Referred to as the “belly shape”, it presents an interesting example of how the developed strategies can be applied to discern the causality, impact and evolution of the responsible traps. In order to take a deeper look into trapping modes, further aging and LASER characterizations are performed to alter the general occupational dynamics and observe the modulation of trap control over device response

Le celle solari organiche appartengono al fotovoltaico di terza generazione e i loro punti di forza risiedono nelle loro peculiarità, che le rendono molto adatte a molte applicazioni, come l'integrazione architettonica o l'elettronica indossabile. Nonostante i numerosi vantaggi, soffrono ancora di molti punti deboli. Il più significativo è la scarsa affidabilità, da cui deriva la necessità di studiare nuove procedure di indagine che conducano alla risoluzione dei problemi di affidabilità. Questa attività di ricerca mira a sviluppare una metodologia per la caratterizzazione e lo studio dell'affidabilità delle celle solari polimeriche. In particolare, sono qui sviluppati due modelli, insieme alla descrizione di una nuova tipologia di misura: la open circuit voltage decay (OCVD). Il primo modello si basa sull'analisi della fotocorrente prodotta da una cella solare organica e prende in considerazione il piegamento della banda elettronica vicino agli elettrodi causata da un accumulo di carica nell’active layer. Questi accumuli di carica hanno un forte impatto sulla fotocorrente prodotta dal dispositivo. Inoltre, il modello spiega diverse discrepanze che sorgono tra i risultati sperimentali e la predizione fatta da altri modelli precedentemente presentati in letteratura. Il secondo modello si basa sull'analisi delle OCVD (ovvero una misura non distruttiva per la cella solare che monitora il transitorio di decadimento della tensione di circuito aperto a partire dal momento in cui la luce sulla cella solare viene spenta). È dimostrato che la forma del transitorio del decadimento della tensione è correlata ai meccanismi di separazione e ricombinazione dei portatori liberi. Molti parametri che descrivono le celle solari polimeriche sono estrapolate dal modello: i tassi di ricombinazione, il numero di portatori intrinseci nell’active layer e il gap energetico dei materiali che compongono lo strato attivo. Al fine di migliorare il fit e l’estrapolazione dei parametri, nel modello OCVD viene aggiunta la considerazione della distribuzione di carica spaziale non costante all'interno dell’active layer. L'analisi è supportata da alcune simulazioni drift diffusion. Ciò consente di quantificare la carica accumulata sulle interfacce elettrodo/organico, ottenendo ulteriori informazioni sulla struttura della banda elettronica della cella solare, e in particolare sull'allineamento tra le funzioni lavoro dell'elettrodo e le bande di trasporto organiche. La seconda parte del lavoro fa uso dei modelli sviluppati nella prima parte. In particolare, sono applicati a dati sperimentali ottenuti da dispositivi solari. I modelli vengono applicati a due casi principali. Nel primo caso, i due modelli sono utilizzati per caratterizzare quattro tipi di celle solari, evidenziando le differenze tra i dispositivi. Nello specifico, vengono estrapolate diverse informazioni sui meccanismi di ricombinazione all'interno dello strato attivo e sul diagramma a bande dell’active layer. Inoltre, viene identificata l'origine delle prestazioni inferiori associate ad alcuni dispositivi rispetto ad altri, mostrando il motivo per cui alcuni dispositivi non si guastano durante stress elettrici. Inoltre, le misurazioni in temperatura consentono di estrapolare il diagramma a bande dei materiali che compongono le celle solari. Nel secondo caso, i modelli vengono utilizzati per monitorare alcune celle durante i test di vita accelerati, mostrando i principali fattori causa di degradazione. Lo stress elettrico danneggia solo lo strato attivo riducendo la velocità di generazione dei polaroni e la probabilità di separazione dei polaron. Dall'analisi della forma della curva di fotocorrente è stato anche osservato che lo stress termico degrada anche l'interfaccia con l'anodo.

The cohesive fracture of thin films is a concern for the reliability of many devices in microelectronics, MEMS, photovoltaics, and other applications. In microelectronic packaging the cohesive fracture toughness has become a concern with new low-k dielectric materials currently being used. To obtain the low-k values needed to meet electrical performance goals, the mechanical strength of the material has decreased. This has resulted in cohesive cracks occurring in the Back End of Line (BEoL) dielectric layers of the microelectronic packages. These cracks lead to electronic failures and occur after thermal loading (due to CTE mismatch of materials) and mechanical loading. To prevent these cohesive cracks, it is necessary to measure the cohesive fracture resistance of these thin films to implement during the design and analysis process. Many of the current tests to measure the cohesive fracture resistance of thin films are based on methods developed for larger scale specimens. These methods can be difficult to apply to thin films due to their size and require mechanical fixturing, physical contact near the crack tip, and complicated stress fields. Therefore, a fixtureless cohesive fracture resistance measurement technique has been developed that utilizes photolithography fabrication processes. This technique uses a superlayer thin film with a high intrinsic stress deposited on top of the desired test material to drive cohesive fracture through the thickness of test material. In addition to developing a technique to measure the fracture resistance of dielectric thin films, the use of carbon nanotube (CNT) forests as off-chip interconnects is investigated as a potential method to mitigate the fracture of these materials. The compressive and tensile modulus of CNT forests is characterized, and it is seen that the modulus is several orders of magnitude less than that of a single straight CNT. The low-modulus CNT forest will help mechanically decouple the chip from the board and reduce stress occurring in the dielectric layers as compared to the current technology of solder ball interconnects and therefore improve reliability. The mechanical performance of these CNT interconnects is investigated by creating a finite-element model of a flip chip electronic package utilizing CNT interconnects and comparing the chip stresses to a traditional solder ball interconnect scenario. Additionally, flip chips are fabricated with CNT forest interconnects, assembled to an FR4 substrate, and subjected to accelerated thermomechanical testing to experimentally investigate their performance.

Ce travail présente une évaluation des performances des transistors à effet de champ à base de graphène (GFET) grâce à des simulations électriques des modèles compact dédiés à des applications à haute fréquence. Les transistors à base de graphène sont parmi les nouvelles technologies et sont des candidats prometteurs pour de futures applications à hautes performances dans le cadre du plan d’action « au-delà du transistor CMOS ». Dans ce contexte, cette thèse présente une évaluation complète des transistors à base de graphène tant au niveau du dispositif que du circuit grâce au développement de modèles compacts précis pour des GFETs, de l’analyse de la fiabilité, en étudiant les mécanismes critiques de dégradation des GFETs, et de la conception des architectures de circuits basés sur des GFETs.Dans cette thèse nous présentons, à l’aide de certaines notions bien particulières de la physique, un modèle compact grand signal des transistors FET à double grille à base de graphène monocouche. Ainsi, en y incluant une description précise des capacités de grille et de l’environnement électromagnétique (EM), ce travail étend également les aptitudes de ce modèle à la simulation RF. Sa précision est évaluée en le comparant à la fois avec un modèle numérique et avec des mesures de différentes technologies GFET. Par extension, un modèle grand signal pour les transistors FET à double grille à base de graphène bicouche est présenté. Ce modèle considère la modélisation de l’ouverture et de la modulation de la bande interdite (bandgap) dues à la polarisation de la grille. La polyvalence et l’applicabilité de ces modèles compacts des GFETs monocouches et bicouches ont été évalués en étudiant les GFETs avec des altérations structurelles.Les aptitudes du modèle compact sont encore étendues en incluant des lois de vieillissement qui décrivent le piégeage de charges et la génération d’états d’interface qui sont responsables de la dégradation induite par les contraintes de polarisation. Enfin, pour évaluer les aptitudes du modèle compact grand signal développé, il a été implémenté au niveau de différents circuits afin de prédire les performances par simulations. Les trois architectures de circuits utilisées étaient un amplificateur triple mode, un circuit amplificateur et une architecture de circuit « balun »
This work presents an evaluation of the performances of graphene-based Field-Effect Transistors (GFETs) through electrical compact model simulation for high-frequency applications. Graphene-based transistors are one of the novel technologies and promising candidates for future high performance applications in the beyond CMOS roadmap. In that context, this thesis presents a comprehensive evaluation of graphene FETs at both device and circuit level through development of accurate compact models for GFETs, reliability analysis by studying critical degradation mechanisms of GFETs and design of GFET-based circuit architectures.In this thesis, an accurate physics-based large-signal compact model for dual-gate monolayer graphene FET is presented. This work also extends the model capabilities to RF simulation by including an accurate description of the gate capacitances and the electro-magnetic environment. The accuracy of the developed compact model is assessed by comparison with a numerical model and with measurements from different GFET technologies.In continuation, an accurate large-signal model for dual-gate bilayer GFETs is presented. As a key modeling feature, the opening and modulation of an energy bandgap through gate biasing is included to the model. The versatility and applicability of the monolayer and bilayer GFET compact models are assessed by studying GFETs with structural alterations.The compact model capabilities are further extended by including aging laws describing the charge trapping and the interface state generation responsible for bias-stress induced degradation.Lastly, the developed large-signal compact model has been used along with EM simulations at circuit level for further assessment of its capabilities in the prediction of the performances of three circuit architectures: a triple-mode amplifier, an amplifier circuit and a balun circuit architecture

Cette thèse porte sur l’étude de la stabilité et de la fiabilité de transistors organiques imprimés au CEA-Liten. Des OTFTs de type P ont été fabriqués sur plastique, avec un polymère semi-conducteur (SCO) de type P (SP400 de Merck) et un fluoropolymère en tant que diélectrique. Tout d’abord, un protocole expérimental pour la caractérisation électrique a été mis en place afin de s’affranchir de potentiels effets dus à l’environnement, la mesure ou le vieillissement des OTFTs. Puis un modèle basé sur l’expression de la charge d’accumulation dans le transistor a été développé. Ce modèle a permis l’extraction des paramètres des OTFTs lors de mesures à basses températures, qui ont mis en évidence un transport de charges en température dans le SCO. Enfin, l’impact du stress électrique de grille négatif sur les caractéristiques des transistors a été étudié. La stabilité électrique des P-OTFTs a été mesurée sur plusieurs empilements afin d’étudier l’influence du diélectrique ou de sa méthode de dépôt et l’influence de la grille (électrode en encre argent imprimée ou en or pulvérisée)
This thesis project is about the study of stability and reliability of organic transistors printed at CEA-Liten. P-Type OTFTs were manufactured on plastic substrate, with a p-type polymer semiconductor (SP400 from Merck) and a fluoropolymer as dielectric. First, an experimental protocol for electrical characterization was determined in order to overcome potential effects due to environment, measurements or aging of OTFTs. Then a model based on the expression of the accumulation charge in the transistor was developed. This model allowed the OTFT parameters’ extraction during low temperature measurements, which showed a temperature-activated charges transport in the OSC. Finally, the impact of negative gate bias stress on OTFTs’ characteristics was studied. The electrical stability of the P-OTFTs was measured on several stacks to study the influence of the dielectric material or its deposition method and the influence of the gate (printed silver ink or sputtered gold electrode)

Geotechnical engineering is strongly associated with large uncertainties. Exploring a medium (soil) that is almost entirely and completely hidden from us is no easy task. Investigations can be made only at discrete points, and the majority of a specific soil volume is never tested. All soils experience inherent spatial variability, which contributes to some uncertainty in the design process of a geotechnical structure. Furthermore, uncertainties also arise during testing and when design properties are inferred from these tests. To master the art of making decisions in the presence of uncertainties, probabilistic description of soil properties and reliability-based design play vital roles. Historically, the observational method (sometimes referred to as the “learn-as-you-go-approach”), sprung from ideas by Karl Terzaghi and later formulated by Ralph Peck, has been used in projects where the uncertainties are large and difficult to assess. The design approach is still highly suitable for numerous situations and is defined in Eurocode 7 for geotechnical design. In paper I, the Eurocode definition of the observational method is discussed. This paper concluded that further work in the probabilistic description of soil properties is highly needed, and, by extension, reliability-based design should be used in conjunction with the observational method. Although great progress has been made in the field of reliability-based design during the past decade, few geotechnical engineers are familiar with probabilistic approaches to design. In papers II and III, aspects of probabilistic descriptions of soil properties and reliability-based design are discussed. The connection between performing qualitative investigations and potential design savings is discussed in paper III. In the paper, uncertainties are assessed for two sets of investigations, one consisting of more qualitative investigations and hence with less uncertainty. A simplified Bayesian updating technique, referred to as “the multivariate approach”, is used to cross-validate data to reduce the evaluated total uncertainty. Furthermore, reliability-based design was used to compare the two sets of investigations with the calculated penetration depth for a sheet-pile wall. The study is a great example of how a small amount of both time and money (in the pre-investigation phase) can potentially lead to greater savings in the final design.

QC 20160201

TRUST, Transparent Underground Structures

Les mémoires à nanocristaux de silicium sont considérées comme l'une des solutions les plus intéressantes pour remplacer les grilles flottantes dans les mémoires Flash pour des applications de mémoires non-volatiles embarquées. Ces nanocristaux sont intéressants pour leur compatibilité avec les technologies de procédé CMOS, et la réduction des coûts de fabrication. De plus, la taille des nanocristaux garantie un faible couplage entre les cellules et la robustesse contre les effets de SILC. L'un des principaux challenges pour les mémoires embarquées dans des applications mobiles et sans contact est l'amélioration de la consommation d'énergie afin de réduire les contraintes de design de cellules. Dans cette étude, nous présentons l'état de l'art des mémoires Flash à grille flottante et à nanocristaux de silicium. Sur ce dernier type de mémoire une optimisation des principaux paramètres technologiques a été effectuée pour permettre l'obtention d'une fenêtre de programmation compatible avec les applications à faible consommation d'énergie. L'étude s'attache à l'optimisation de la fiabilité de la cellule à nanocristaux de silicium. On présente pour la première fois une cellule fonctionnelle après un million de cycles d'écriture et effacement dans une large gamme de températures [-40°C;150°C], et qui est capable de retenir l'information pendant dix ans à 150°C. Enfin, une analyse de la consommation de courant et d'énergie durant la programmation montre l'adaptabilité de la cellule pour des applications à faible consommation. Toutes les données expérimentales ont été comparées avec les résultats d'une cellule standard à grille flottante pour montrer les améliorations apportées
The silicon nanocrystal memories are one of the most attractive solutions to replace the Flash floating gate for nonvolatile memory embedded applications, especially for their high compatibility with CMOS process and the lower manufacturing cost. Moreover, the nanocrystal size guarantees a weak device-to-device coupling in an array configuration and, in addition, for this technology it has been shown the robustness against SILC. One of the main challenges for embedded memories in portable and contactless applications is to improve the energy consumption in order to reduce the design constraints. Today the application request is to use the Flash memories with both low voltage biases and fast programming operation. In this study, we present the state of the art of Flash floating gate memory cell and silicon nanocrystal memories. Concerning this latter device, we studied the effect of main technological parameters in order to optimize the cell performance. The aim was to achieve a satisfactory programming window for low energy applications. Furthermore, the silicon nanocrystal cell reliability has been investigated. We present for the first time a silicon nanocrystal memory cell with a good functioning after one million write/erase cycles, working on a wide range of temperature [-40°C; 150°C]. Moreover, ten years data retention at 150°C is extrapolated. Finally, the analysis concerning the current and energy consumption during the programming operation shows the opportunity to use the silicon nanocrystal cell for low power applications. All the experimental data have been compared with the results achieved on Flash floating gate memory, to show the performance improvement

Cette thèse concerne l’étude des procédés de fabrication des grilles HKMG des technologies FDSOI 14 et 28 nm sur les performances électriques des transistors MOS. Elle a porté spécifiquement sur l'aspect fiabilité et la maîtrise du travail de sortie effectif (WFeff), au travers de la diffusion des additifs comme le lanthane (La) et l’aluminium (Al). Ce travail combine des techniques de caractérisation électriques et physico-chimiques et leur développement. L'effet de l'incorporation de ces additifs sur la fiabilité et la durée de vie du dispositif a été étudié. Le lanthane dégrade les performances de claquage TDDB et de dérives suite aux tests aux tensions négatives. L’introduction d’aluminium améliore le claquage TDDB, mais dégrade les dérives aux tensions positives. Ces comportements ont été reliés à des mécanismes physiques. Par ailleurs, la diffusion de ces additifs dans l’empilement de grille a été étudiée pour différents matériaux high-k en fonction de la température et de la durée de recuit de diffusion. Les doses d’additifs ont pu être ainsi mesurées, comparées et corrélées au décalage de travail de sortie effectif de grille. On a également étudié, les influences des paramètres du procédé de dépôt de grille TiN sur leur microstructure et les propriétés électriques du dispositif, identifiant certaines conditions à même de réduire la taille de grain ou la dispersion d’orientation cristalline. Toutefois, les modulations obtenues sur le travail de sortie effectif de grille dépendent plus du ratio Ti/N, suggérant un changement du dipôle à l'interface SiO2 / high-k. Enfin, une technique éprouvée de mesure de spectroscopie à rayon X sous tension a pu être mise en place grâce des dispositifs spécifiques et une méthodologie adaptée. Elle permet de mesurer les positions relatives des bandes d’énergie à l'intérieur de l’empilement de grille. Cette technique a démontré que le décalage du travail de sortie effectif induits par des additifs (La or Al) ou par des variations d'épaisseur de grille métallique TiN provient de modifications du dipôle à l'interface SiO2/ high-k
This Ph.D. thesis is focused on the impact of the 14 and 28 nm FDSOI technologies HKMG stack processes on the electrical performance of MOS transistors. It concerns specifically the reliability aspect and the engineering of effective workfunction (WFeff ), through diffusion of lanthanum (La) and aluminum (Al) additives. This work combines electrical and physicochemical characterization techniques, and their development. The impact of La and Al incorporation, in the MOS gate stack, on reliability and device lifetime has been studied. La addition has a significant negative impact on device lifetime related to both NBTI and TDDB degradations. Addition of Al has a significant negative impact on lifetime related to PBTI, but on the contrary improves the lifetime for TDDB degradation. These impacts on device lifetime have been well correlated to the material changes inside the gate oxides. Moreover, diffusion of these additives into the HKMG stack with annealing temperature and time has been studied on different high-k materials. The diffused dose has been compared with the resulting shift in effective workfunction (WFeff), evidencing clear correlation. In addition, impact of TiN metal gate RF-PVD parameters on its crystal size and orientation, and device electrical properties has been studied. XRD technique has been used to obtain the crystal size and orientation information. These properties are significantly modulated by TiN process, with a low grain size and a unique crystal orientation obtained in some conditions. However, the WFeff modulations are rather correlated to the Ti/N ratio change, suggesting a change in the dipole at SiO2/high-k interface. Lastly, using specific test structures and a new test methodology, a robust and accurate XPS under bias technique has been developed to determine the relative band energy positions inside the HKMG stack of MOS devices. Using this technique, we demonstrated that WFeff shift induced by La and Al or by variations in gate thickness originates due to modifications of the dipole at SiO2/high-k interface

O trabalho propõe um circuito para caracterização estatística do fenômeno Bias Temperature Instability (BTI). O circuito tem como base uma matriz de transistores para caracterização eficiente em larga escala de BTI. O design proposto visa o estudo da variabilidade de BTI dependente do tempo em dispositivos altamente miniaturizados. Para tanto se necessita medir centenas de dispositivos, a fim de se obter uma amostra estatisticamente significante. Uma vez que variações nos tempos de estresse e medida dos dispositivos podem gerar erros no processo de caracterização, o circuito implementa em chip (on-chip) o controle dos tempos de estresse e de medida, para que ocorra uma caracterização estatística precisa. O circuito de controle implementado faz com que todos dispositivos testados tenham os mesmos tempos de estresse e os mesmos tempos de recuperação (relaxamento). Desta forma, o circuito proposto melhora significantemente tanto a área utilizada quanto o tempo de medida, quando comparado a alternativas anteriormente implementadas. O leiaute do circuito foi realizado no novo nó tecnológico de 28 nanômetros do IMEC.
This work proposes an array-based evaluation circuit for efficient and massively parallel characterization of Bias Temperature Instability (BTI). This design is highly efficient when studying the BTI time-dependent variability in deeply-scaled devices, where hundreds of devices should be electrically characterized in order to obtain a statistically significant sample size. The circuit controls stress and measurement times for accurate statistical characterization, making sure all the devices characterized have the same stress and recovery times. It significantly improves both area and measurement time. The circuit layout is laid out in the new 28nm node IMEC technology.

Les mémoires non-volatiles sont devenues récemment un moteur clé de la croissance du secteur des semiconducteurs, et constituent un pivot pour les nouvelles applications et les nouveaux concepts dans le domaine des technologies de l'information et de la communication (TIC). Afin de surmonter les limites en termes de miniaturisation, de consommation électrique et de complexité de fabrication des mémoires non-volatiles à grille flottante (FLASH), l'industrie des semiconducteurs évalue actuellement des solutions alternatives. Parmi celles-ci, les mémoires résistives à pont conducteur ou CBRAM (Conductive Bridge Random Access Memory), qui reposent sur la commutation de résistance d'un électrolyte par migration et oxydo/réduction d'ions métalliques, semblent être des plus prometteuses. L'attractivité de cette technologie innovante vient d'une part de la simplicité de sa structure à deux terminaux et d'autre part de ses performances électriques très prometteuses en termes de consommation électrique et vitesse d'écriture/effacement. De surcroît la CBRAM is une technology mémoire qui s'intègre facilement dans le back end of line (BEOL) du procédé CMOS standard. Dans cette thèse, nous étudions les performances électriques et la fiabilité de deux technologies CBRAM, utilisant des chalcogénures (GeS2) ou un oxyde métallique pour l'électrolyte. Tout d'abord nous nous concentrons sur les CBRAM à base de GeS2, ou l'effet du dopage de l'électrolyte avec de l'argent (Ag) ou de l'antimoine (Sb) est étudié à la lumière d'une analyse des caractérisations électriques. Les mécanismes physiques gouvernant la cinétique de commutation et la stabilité thermique sont aussi discutés sur la base de mesures électrique, d'un modèle empirique et des résultats de calculs ab initio. L'influence des différentes conditions de set/reset est étudiée sur une CBRAM à base d'oxyde métallique. Grâce à cette analyse, les conditions permettant de maximiser la fenêtre mémoire, améliorer l'endurance et minimiser la variabilité sont déterminées
Non-volatile memory technology has recently become the key driver for growth in the semiconductor business, and an enabler for new applications and concepts in the field of information and communication technologies (ICT). In order to overcome the limitations in terms of scalability, power consumption and fabrication complexity of Flash memory, semiconductor industry is currently assessing alternative solutions. Among them, Conductive Bridge Memories (CBRAM) rely on the resistance switching of a solid electrolyte induced by the migration and redox reactions of metallic ions. This technology is appealing due to its simple two-terminal structure, and its promising performances in terms of low power consumption, program/erase speed. Furthermore, the CBRAM is a memory technology that can be easily integrated with standard CMOS technology in the back end of line (BEOL). In this work we study the electrical performances and reliability of two different CBRAM technologies, specifically using chalcogenides (GeS2) and metal oxide as electrolyte. We first focus on GeS2-based CBRAM, where the effect of doping with Ag and Sb of GeS2 electrolyte is extensively investigated through electrical characterization analysis. The physical mechanisms governing the switching kinetics and the thermal stability are also addressed by means of electrical measurements, empirical model and 1st principle calculations. The influence of the different set/reset programming conditions is studied on a metal oxide based CBRAM technology. Based on this analysis, the programming conditions able to maximize the memory window, improve the endurance and minimize the variability are determined

This thesis encompasses a set of different subjects related to metocean variables but studied from different perspectives. The metocean variables are mainly significant wave heights and wind velocities and, to a lesser extent, wave periods. The extreme value theory is used to probabilistically characterized the metocean variables by means of the generalized extreme value distribution (GEV). The effect of seasonality is included by considering monthly maxima and using harmonic and subharmonic functions (i.e., time dependency in the GEV model is incorporated). Although Mexican information was not available to this study, the studies are considered applicable to Mexican coasts in the Gulf of Mexico and the Pacific, since available public information from U.S. buoys located in the Atlantic and Pacific oceans relatively close to the Mexican coasts is employed. For the Pacific region, the GEV model accounting for seasonality is applied to data from a buoy (this is reported in an article in the appendix and summarized as a book chapter in the compendium of publications) and comparisons are carried out versus analogous results for buoys in the Gulf of Mexico obtained in a previous study (included also in the appendix). In other part of the thesis (another book chapter in the compendium), but also for the buoy in the Pacific Ocean, a study is carried out to assess the impact of including or excluding an atypical wave height in the seasonality and in future projections (i.e., wave heights associated with given return periods), since an atypically large significant wave heigh was observed for the considered buoy. One more study (an article in the compendium) introduces the wind velocity as a Metocean variable to be characterized with the time-dependent GEV model from data of a buoy in the Gulf of Mexico. This wind velocity is not for monthly maxima, but for the recorded wind velocity which simultaneously occurred with the maximum significant wave heights. This allowed to propose a simplified approach to determined concurrent significant wave heights and associated wind velocities for given return periods, while accounting for seasonality and quantitatively establishing the uncertainty in the correlated metocean variables in question. This proposal can be potentially used for design and engineering purposes, if the metocean are considered as hazards which imposed demands on coastal (and structural) engineering systems. Additionally, the effect of varying the considered time window for the extreme projections is explored. In a final study (also an article in the compendium), an introduction to the reliability of coastal (and also structural) engineering systems is presented; a breakwater is used as case-study. The coastal structure is subjected to the action of wave heights with different wave periods, for which the joint Longuet-Higgins distribution is used, and the overtopping probability of failure is computed by using classical and revisited reliability approaches. Future studies could combine the characterization of metocean variables as time-dependent GEV models and the used reliability approaches to further investigate the reliability of coastal and offshore systems.
Esta tesis abarca diferentes temas relacionados con variables meteoceanográficas (metocean) pero estudiadas desde diversas perspectivas. Estas variables son principalmente el oleaje significativo y la velocidad de viento, y en menor medida el período de oleaje. Se emplea la teoría de valores extremos para caracterizar probabilísticamente las variables meteoceanográficas mediante el uso de la distribución de extremos generalizada (GEV, por sus siglas en inglés), incluyendo el efecto de la estacionalidad al considerar máximos valores mensuales, así como funciones armónicas y subarmónicas, lo que significa que el modelo GEV es función del tiempo. Aunque no se contó con información mexicana para el presente trabajo, se considera que lo desarrollado aquí puede aplicarse a las costas mexicanas, ya que se usaron datos de boyas estadounidenses situadas en los océanos Atlántico y Pacífico y relativamente cercanas a costas mexicanas. Para la región del Pacífico se aplica el modelo GEV a una boya (esto se describe en un artículo en el apéndice y resumido como capítulo de libro en el compendio de publicaciones) y los resultados se comparan con resultados análogos de un estudio previo, pero para boyas localizadas en el Golfo de México (dicho estudio también está contenido en el apéndice). En otra parte de la tesis, pero también para la boya del Pacífico (otro capítulo de libro en el compendio), mediante un estudio se estima el impacto de incluir o excluir un dato atípico de la altura de oleaje en la estacionalidad y proyecciones a futuro (i.e., las alturas de oleaje asociadas a periodos de retorno dados), ya que se observó una ola atípicamente alta para la boya considerada. Un estudio más (un artículo del compendio) incorpora a las velocidades de viento como variable meteoceanográfica para también caracterizarla como un modelo GEV que depende del tiempo, con datos de una boya situada en el Golfo de México. Estas velocidades de viento no corresponden a las máximas reportadas en cada mes, sino a aquellas que ocurrieron simultáneamente con las máximas alturas significativas generadas por oleaje. Esto conllevó a proponer un método simplificado para determinar alturas de oleaje significativo concurrentes con los vientos asociados a la misma boya y tiempo y para un periodo de retorno dado, y al mismo tiempo incorporando efectos de estacionalidad y estableciendo de manera cuantitativa la incertidumbre para las variables correlacionadas mencionadas. Esta propuesta es potencialmente útil para propósitos de diseño e ingenieriles, si las variables meteoceanográficas se consideran como peligros que imponen demandas a sistemas de ingeniería costeros (y estructurales). Adicionalmente, se explora el efecto de utilizar diferentes ventanas de tiempo en las proyecciones de valores extremos. En un estudio final (también un artículo del compendio) se presenta una introducción a la confiabilidad de sistemas de ingeniería costera (y también estructural), usando un rompeolas como caso de estudio. La estructura costera se somete a la acción de oleaje con diferentes periodos, mediante el uso de la distribución de Longuet-Higgins, y se calculan las probabilidades de falla por rebase aplicando métodos de confiabilidad clásicos, y otros métodos consultados en retrospectiva y reconsiderados prospectivamente. Estudios futuros podrían combinar el uso de modelos GEV como función del tiempo para caracterizar variables meteoceanográficas con el uso de métodos de confiabilidad, para investigar más a fondo la confiabilidad de sistemas costeros y costa afuera.

Les produits issus des technologies Silicium tendent à exploiter au maximum les performancesdes transistors MOS tout en les soumettant à des profils de mission très agressifs du point de vuede la fiabilité. Les concepteurs sont ainsi à la recherche du meilleur compromis entre performanceet fiabilité.Historiquement, l’étude de la fiabilité du transistor MOS et le développement des modèlessous jacents ont été menés sur la base de contrainte de vieillissement statique. Avec le développementdes produits à hautes performances dans le domaine de la radiofréquence (RF), laquestion de la fiabilité pour ce type d’application se pose. Ainsi, une extension des modèles defiabilité doit être réalisée afin de quantifier le vieillissement des paramètres clés RF soumis àdes contraintes statiques mais également RF. C’est cette extension de la fiabilité des transistorsMOS dans le domaine RF qui constitue le sujet de ce travail de thèse.Dans ce manuscrit, le fonctionnement du transistor MOS est décrit et sa fiabilité est introduite.Les différents mécanismes de dégradation sont étudiés et leurs modèles associés décrits.Sont ensuite présentés un banc de mesure et une méthodologie nécessaire à l’étude du vieillissementdes transistors dans le domaine RF, ainsi qu’à l’extension des modèles de fiabilité audomaine RF
Products using nowadays silicon technology are generally targeting aggressive specificationsand push the developers to determine the best compromise between performance and reliability.Main front-end degradation mechanisms are historically studied and modeled under static stressconditions and focus on the static MOS transistor parameters.With the development of product targeting high performances in the radio frequency (RF)domain, the reliability is becoming a first order concern. Thus an extension of the actual staticreliability models must be done to quantify the aging of key RF parameters under static andRF stress. In this context, this work focuses on the extension of the MOS transistor reliabilityregarding the study of RF parameters and also the application of RF stress.After describing the MOS transistor properties, the reliability aspect is introduced and theemphasis is put on the different degradation mechanisms and their associated models. Thisallows the development of an experimental setup and the required methodology to investigatethe device aging in the RF domain and to extend actual static models